CN112164720A - Power semiconductor device - Google Patents

Power semiconductor device Download PDF

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Publication number
CN112164720A
CN112164720A CN202011071299.1A CN202011071299A CN112164720A CN 112164720 A CN112164720 A CN 112164720A CN 202011071299 A CN202011071299 A CN 202011071299A CN 112164720 A CN112164720 A CN 112164720A
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type
region
layer
heavily doped
semiconductor device
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杨信佳
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thyristors (AREA)

Abstract

The invention provides a power semiconductor device, which comprises an N-type semiconductor layer, a P-type well region, an N-type heavily doped region, an insulating layer and a gate layer. The P-type well region is arranged in the N-type semiconductor layer and surrounds the C-shaped N-type region of the N-type semiconductor layer. The N-type heavily doped region is arranged in the P-type well region and surrounds the C-shaped N-type region. The insulating layer is arranged on the N-type semiconductor layer and covers part of the P-type well region, part of the N-type heavily doped region and the C-shaped N-type region. The gate layer is arranged on the insulating layer, and the shape of the gate layer is the same as that of the C-shaped N-type area. The invention reduces the probability of heat energy generation by increasing the cross section area of current passing and the perimeter of the gate layer.

Description

Power semiconductor device
Technical Field
The present invention relates to a semiconductor device, and more particularly, to a power semiconductor device.
Background
The semiconductor and semiconductor industries have evolved into a sophisticated, highly inventive and high-yield industry, and a number of front-end processes and equipment, coupled with optical lithography, have been successfully used to fabricate electronic devices and integrated circuits. However, heat is an inevitable issue, which is caused by ohmic heat generation, such as the speed requirement of devices or low-cost communication Integrated Circuits (ICs), or power devices. Generally, heat is generated substantially by friction caused by collision and is therefore seen everywhere. Unfortunately, it is the major source of energy consumption, but suffers from recoverable efficiencies below about 40%. Rather than conducting the heat produced, efforts have been made to reduce the chance of heat generation. The generation of electric heat is caused by friction generated by the collision of the conductive current carrier with the internal crystal lattice of the conductive material.
Fig. 1 is a top view of a power semiconductor device in the prior art, and fig. 2 is a cross-sectional view of the power semiconductor device taken along line a-a' of fig. 1, referring to fig. 1 and fig. 2. In the prior art, the power semiconductor device 1 includes an N-type substrate 10, a P-well 12, an N-type heavily doped region 14, an insulating layer 16 and a gate layer 18. The P-well 12 is disposed in the N-substrate 10 and surrounds an N-region 19 of the N-substrate 10, and the heavily N-doped region 14 is disposed in the P-well 12 and also surrounds the N-region 19. The insulating layer 16 is disposed on the P-well 12, the heavily doped N-type region 14 and the N-type region 19, and the gate layer 18 is disposed on the insulating layer 16. When a positive voltage is applied to the N-type substrate 10 and the N-type heavily doped region 14 is grounded, a current flows from the N-type substrate 10 to the N-type heavily doped region 14 through the N-type region 19 and the P-type well 12 in sequence. Assume that the periphery of the P-well 12 is a square with a side length of 14 microns, the gate layer 18 is a square with a side length of 10 microns, and the N-region 19 is a square with a side length of 2 microns. Since both the outer circumference of the gate layer 18 and the cross-sectional area of the N-type region 19 are positively correlated with the probability of heat generation, assuming that the cross-sectional area of the power semiconductor device 1 is considered to be 14 × 14 micrometers, the outer circumference of the gate layer 18 is 10 × 4 micrometers, and the cross-sectional area of the N-type region 19 is 22Square micron. Therefore, the perimeter of the power semiconductor device 1 through which current flows per unit area is 10 × 4/1420.2041 (microns)-1) The cross-sectional area of the power semiconductor device 1 through which current flows per unit area is 22/1420.020408. When 0.2041 × 0.020408 is 0.004165, 0.004165 is too low, which means that the power semiconductor device 1 is likely to generate thermal energy.
Therefore, the present invention is directed to a power semiconductor device to solve the above-mentioned problems.
Disclosure of Invention
The invention provides a power semiconductor device, which can reduce the probability of heat energy generation.
The invention provides a power semiconductor device, which comprises an N-type semiconductor layer, a P-type well region, an N-type heavily doped region, an insulating layer and a gate layer. The P-type well region is arranged in the N-type semiconductor layer, wherein the P-type well region surrounds the C-shaped N-type region of the N-type semiconductor layer. The N-type heavily doped region is arranged in the P-type well region and surrounds the C-shaped N-type region. The insulating layer is arranged on the N-type semiconductor layer and covers part of the P-type well region, part of the N-type heavily doped region and all the C-shaped N-type regions. The gate layer is arranged on the insulating layer, and the shape of the gate layer is the same as that of the C-shaped N-type area.
Optionally, the N-type semiconductor layer is an N-type lightly doped substrate.
Optionally, the power semiconductor device further comprises a heavily doped semiconductor layer disposed at the bottom of the N-type semiconductor layer.
Optionally, an outer sidewall of the P-type well region is spaced apart from an outer sidewall of the N-type heavily doped region.
Optionally, each of the gate layer and the C-shaped N-type region has a first recess portion and a second recess portion communicating with each other, and a width of the first recess portion is different from a width of the second recess portion.
Optionally, the first recess has a fixed width and the second recess has a tapered width.
Optionally, the outer perimeter of the gate layer comprises at least two straight lines, all of which are of equal length.
Optionally, each line is 30 microns.
Optionally, the gate layer has a recess having a fixed width or a tapered width.
Optionally, the shape of the insulating layer is the same as the shape of the gate layer.
Optionally, the P-type well region has an outer perimeter of 136 microns.
Optionally, the power semiconductor device further comprises a P-type heavily doped region and a P-type heavily doped semiconductor layer. The P-type heavily doped region is arranged in the P-type well region and surrounds the N-type heavily doped region, and the P-type heavily doped semiconductor layer is arranged at the bottom of the N-type semiconductor layer.
Optionally, the N-type semiconductor layer is an N-type substrate.
Optionally, the N-type semiconductor layer further includes a semiconductor substrate and an N-type epitaxial layer disposed on the semiconductor substrate, the N-type epitaxial layer has a C-shaped N-type region, the P-type well region is disposed in the N-type epitaxial layer, and the insulating layer is disposed on the N-type epitaxial layer.
Based on the above, the power semiconductor device reduces the probability of generating heat energy by increasing the cross-sectional area through which the current passes and the perimeter of the gate layer.
In order to provide a better understanding and appreciation for the structural features and advantages of the invention, reference should be made to the accompanying drawings, which are illustrated in the accompanying drawings, wherein:
drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without inventive exercise.
FIG. 1 is a top view of a prior art power semiconductor device;
FIG. 2 is a cross-sectional view of the structure of FIG. 1 taken along line A-A';
FIG. 3 is a top view of a power semiconductor device according to a first embodiment of the present invention;
FIG. 4 is a cross-sectional view of the structure taken along line B-B' of FIG. 3;
FIG. 5 is a cross-sectional view of the alternative construction taken along line B-B' of FIG. 3;
FIG. 6 is a cross-sectional view of a power semiconductor device according to a second embodiment of the present invention;
FIG. 7 is a cross-sectional view of the structure of FIG. 6 taken along line C-C';
FIG. 8 is a cross-sectional view of the alternate construction taken along line C-C' of FIG. 6;
fig. 9 is a structural sectional view of a third embodiment of a power semiconductor device of the present invention;
FIG. 10 is a cross-sectional view of the structure of FIG. 9 taken along line D-D';
FIG. 11 is a cross-sectional view of the alternate construction taken along line D-D' of FIG. 9;
FIG. 12 is a top view of a fourth embodiment of the power semiconductor device of the present invention;
FIG. 13 is a cross-sectional view of the structure of FIG. 12 taken along line E-E';
FIG. 14 is a cross-sectional view of an alternative construction taken along line E-E' of FIG. 12;
fig. 15 is a structural sectional view of a fifth embodiment of a power semiconductor device of the present invention;
FIG. 16 is a cross-sectional view of the structure of FIG. 15 taken along line F-F';
FIG. 17 is a cross-sectional view of the alternate construction taken along line F-F' of FIG. 15;
fig. 18 is a structural sectional view of a sixth embodiment of a power semiconductor device of the invention;
FIG. 19 is a cross-sectional view of the structure of FIG. 18 taken along line G-G';
fig. 20 is a cross-sectional view of the alternate construction taken along line G-G' of fig. 18.
Description of the symbols
1 … power semiconductor device, 10 … N type substrate, 12 … P type well region, 14 … N type heavily doped region, 16 … insulating layer, 18 … gate layer, 19 … N type region,
2 … power semiconductor device, 20 … N type semiconductor layer, 201 … C-shaped N type region, 202 … semiconductor substrate, 203.. N type epitaxial layer, 21 … P type well region, 22 … N type heavily doped region, 23 … insulating layer, 24 … gate layer, 25 … heavily doped semiconductor layer, 26 … P type heavily doped region, 27 … P type heavily doped semiconductor layer,
d1 … side length, D2 … side length, D3 … width, D4 … width, D5 … width, D6 … width.
Detailed Description
Embodiments of the invention will be further explained by the following description in conjunction with the related drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts. In the drawings, the shape and thickness may be exaggerated for simplicity and convenience of illustration. It is to be understood that elements not specifically shown in the drawings or described in the specification are in a form known to those skilled in the art. Many variations and modifications may be made by one of ordinary skill in the art in light of the teachings of the present invention.
Unless otherwise specified, certain conditional sentences or words, such as "may", "might" or "might", are generally intended to mean that an embodiment of the invention has, but may also be interpreted as functions, elements or steps that may not be required. In other embodiments, these features, elements or steps may not be required.
The following description of "one embodiment" or "an embodiment" refers to a particular element, structure, or characteristic described in connection with at least one embodiment. Thus, the appearances of the phrase "one embodiment" or "an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
Certain terms are used throughout the description and claims to refer to particular components. Those skilled in the art recognize that components may be referred to by different names. This disclosure is not intended to distinguish between components that differ in name but not function. In the description and claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "including, but not limited to. The phrases "coupled to," "coupled to," and "coupled to" are intended to include any indirect or direct connection. Thus, if the present disclosure refers to a first device being coupled to a second device, it is meant that the first device may be connected to the second device through an electrical connection, wireless communication, optical communication, or other signal connection, with/without directly or indirectly utilizing other intermediate devices or connections.
Increasing the cross-sectional area of the current carrier (carrier) path is also important to increase the conduction current or reduce the resistance to improve the electrical performance of the device or Integrated Circuit (IC), and thus if it is possible to fabricate power devices, particularly vertical transistors such as double diffused metal oxide semiconductor field effect transistors (VMOSFETs), which effectively increase the total number of cross-sectional areas per unit area of silicon chip when the current carrier is vertically moved from the bottom of the transistor to the top of the transistor, the resistance can be simultaneously reduced to reduce ohmic heat generation, thereby protecting the designed or fabricated device or IC from thermal photons or thermophonons, and even maintaining the good electrical performance of the device.
Fig. 3 is a top view of a power semiconductor device according to a first embodiment of the present invention, and fig. 4 is a cross-sectional view of the power semiconductor device taken along line B-B' of fig. 3. Referring to fig. 3 and 4, a first embodiment of the power semiconductor device of the present invention is described. The power semiconductor device 2 includes an N-type semiconductor layer 20, a P-well 21, an N-type heavily doped region 22, an insulating layer 23 and a gate layer 24, wherein the N-type semiconductor layer 20 can be an N-type lightly doped substrate or a normal N-type substrate. P-type well region 21 is formed in N-type semiconductor layer 20, and P-type well region 21 surrounds C-shaped N-type region 201 of N-type semiconductor layer 20. The heavily doped N-type region 22 is disposed in the P-well 21, and the heavily doped N-type region 22 surrounds the N-type C-shaped region 201. The outer sidewall of the P-well 21 may not only be spaced apart from the outer sidewall of the heavily doped N-type region 22, but also be in contact with the outer sidewall of the heavily doped N-type region 22. The insulating layer 23 is disposed on the N-type semiconductor layer 20 and covers a portion of the P-well 21, a portion of the heavily doped N-type region 22, and the entire N-type C-region 201. The gate layer 24 is formed on the insulating layer 23, such that the gate layer 24 also covers a portion of the P-well 21, a portion of the heavily doped N-type region 22, and the entire C-shaped N-type region 201, the insulating layer 23 has the same shape as the gate layer 24, and the outer circumference of the gate layer 24 overlaps the heavily doped N-type region 22, so that the gate layer 24 has the same shape as the C-shaped N-type region 201, i.e., the gate layer 24 has a C-shape. For example, the outer perimeter of the gate layer 24 includes at least two straight lines, which are equal in length, such as 30 microns, but the invention is not limited thereto. In addition, the gate layer 24 has a recess portion having a fixed width or a tapered width, but the present invention is not limited thereto. In order to form ohmic contact, the power semiconductor device 2 further includes a heavily doped semiconductor layer 25 of N-type or P-type disposed at the bottom of the N-type semiconductor layer 20.
When a positive voltage is applied to the heavily doped semiconductor layer 25 and the N-type heavily doped region 22 is grounded, a current flows from the heavily doped semiconductor layer 25 to the N-type heavily doped region 22 through the N-type semiconductor layer 20, the C-shaped N-type region 201 and the P-type well region 21 in sequence. The periphery of P-well region 21 is assumed to be square with a side length D1 of 34 microns and a perimeter of 136 microns. The gate layer 24 has three mutually perpendicular equal length sidesD2, which is 30 microns. The fixed width D3 of the recess of the gate layer 24 is 10 microns. The closest horizontal distance between the sidewall of the C-shaped N-type region 201 and the sidewall of the gate layer 24 is 8 microns. In order to increase the cross-sectional area through which current flows, both the outer peripheral length of the gate layer 24 and the cross-sectional area of the C-shaped N-type region 201 are positively correlated with the probability of heat generation, assuming that the cross-sectional area of the power semiconductor device 2 is 34 micrometers × 34 micrometers, the outer peripheral length of the gate layer 24 is (10 × 5+30 × 3+20) micrometers, and the cross-sectional area of the C-shaped N-type region 201 is (2 × 5+30 × 3+20) micrometers2X 10 x 3) square microns. Therefore, the perimeter of the power semiconductor device 2 through which current flows per unit area is (10 × 5+30 × 3+20)/3420.1384 (micrometers)-1) The cross-sectional area of the power semiconductor device 2 through which current flows per unit area is (2)2×10×3)/3420.103806. Compared with 0.004165 in fig. 1, 0.1384 × 0.103806 is 0.014368, which is much higher, so that the probability of generating heat energy can be reduced.
Fig. 5 is another sectional view of the structure taken along line B-B' of fig. 3. The difference between fig. 5 and fig. 4 is that the N-type semiconductor layer 20 includes a semiconductor substrate 202 and an N-type epitaxial layer 203, the semiconductor substrate 202 can be an N-type semiconductor substrate or a P-type semiconductor substrate, the N-type epitaxial layer 203 is disposed on the semiconductor substrate 202, the N-type epitaxial layer 203 has a C-shaped N-type region 201, the P-type well 21 is disposed in the N-type epitaxial layer 203, the insulating layer 23 is disposed on the N-type epitaxial layer 203, and the heavily doped semiconductor layer 25 is disposed at the bottom of the semiconductor substrate 202.
Fig. 6 is a sectional view of a power semiconductor device according to a second embodiment of the present invention, and fig. 7 is a sectional view of the power semiconductor device of fig. 6 taken along line C-C'. Referring to fig. 6 and 7, a second embodiment of the power semiconductor device of the present invention will be described. Compared with the first embodiment, the gate layer 24, the insulating layer 23 and each C-shaped N-type region 201 of the power semiconductor device 2 of the second embodiment have a first concave portion and a second concave portion which are communicated with each other, and the width of the first concave portion is different from the width of the second concave portion, so as to increase the cross-sectional area through which current passes.
When a positive voltage is applied to the heavily doped semiconductor layer 25 and the N-type heavily doped region 22 is grounded, a current flows from the heavily doped semiconductor layer 25 through the N-type semiconductor layer 20 and the C-shaped N-type region in sequenceThe region 201 and the P-type well 21 flow toward the heavily doped N-type region 22. The periphery of P-well region 21 is assumed to be square with a side length D1 of 34 microns and a perimeter of 136 microns. The gate layer 24 has three mutually perpendicular equal length sides D2, D2 being 30 microns. The first recess of the gate layer 24 has a constant width D3 of 10 microns and the second recess has a constant width D4 that is much smaller than the width D3. The C-shaped N-type region 201 is located at the center of the gate layer 24, and the C-shaped N-type region 201 is 2 μm. Assuming that the cross-sectional area of the power semiconductor device 2 is 34 micrometers × 34 micrometers, the outer circumference of the gate layer 24 is (10 × 4+30 × 4) micrometers, and the cross-sectional area of the C-shaped N-type region 201 is (2)2X 10 x 4) square microns. Therefore, the perimeter of the power semiconductor device 2 through which current flows per unit area is (10 × 4+30 × 4)/3420.1384 (micrometers)-1) The cross-sectional area of the power semiconductor device 2 through which current flows per unit area is (2)2×10×4)/3420.1384085. Compared with 0.014368 of the first embodiment, the method of 0.1384 × 0.1384085 is higher than 0.019156, so that the probability of generating heat energy is reduced.
Fig. 8 is a cross-sectional view of the alternative construction taken along line C-C' of fig. 6. The difference between FIG. 8 and FIG. 7 is that the N-type semiconductor layer 20 includes a semiconductor substrate 202 and an N-type epitaxial layer 203, the semiconductor substrate 202 can be an N-type semiconductor substrate or a P-type semiconductor substrate, the N-type epitaxial layer 203 is disposed on the semiconductor substrate 202, the N-type epitaxial layer 203 has a C-shaped N-type region 201, the P-type well 21 is disposed in the N-type epitaxial layer 203, the insulating layer 23 is disposed on the N-type epitaxial layer 203, and the heavily doped semiconductor layer 25 is disposed at the bottom of the semiconductor substrate 202.
Fig. 9 is a sectional view of a power semiconductor device according to a third embodiment of the present invention, and fig. 10 is a sectional view of the power semiconductor device of fig. 9 taken along line D-D'. Referring to fig. 9 and 10, a third embodiment of the power semiconductor device of the present invention is described. In comparison with the first embodiment, each of the gate layer 24, the insulating layer 23 and the C-shaped N-type region 201 of the power semiconductor device 2 of the third embodiment has a first recess and a second recess which are communicated with each other, and the width of the first recess is different from the width of the second recess, so as to increase the cross-sectional area through which current passes. In the third embodiment, the first recess of the gate layer 24 has a fixed width D5 and the second recess of the gate layer 24 has a tapered width D6. Since the outer perimeter of the gate layer 24 is increased compared to the cross-sectional area of the C-shaped N-type region 201 in fig. 1, the probability of heat generation is also reduced.
Fig. 11 is a cross-sectional view of the alternate construction taken along line D-D' of fig. 9. The difference between FIG. 11 and FIG. 10 is that the N-type semiconductor layer 20 includes a semiconductor substrate 202 and an N-type epitaxial layer 203, the semiconductor substrate 202 can be an N-type semiconductor substrate or a P-type semiconductor substrate, the N-type epitaxial layer 203 is disposed on the semiconductor substrate 202, the N-type epitaxial layer 203 has a C-shaped N-type region 201, the P-type well 21 is disposed in the N-type epitaxial layer 203, the insulating layer 23 is disposed on the N-type epitaxial layer 203, and the heavily doped semiconductor layer 25 is disposed at the bottom of the semiconductor substrate 202.
Fig. 12 is a top view of a power semiconductor device according to a fourth embodiment of the present invention. Fig. 13 is a cross-sectional view of the structure of fig. 12 taken along line E-E'. Referring to fig. 4, 12 and 13, a fourth embodiment of the power semiconductor device of the present invention is described. Compared with the first embodiment, the power semiconductor device 2 of the fourth embodiment further includes a P-type heavily doped region 26, and the heavily doped semiconductor layer 25 of the first embodiment is replaced by a P-type heavily doped semiconductor layer 27. The heavily doped P-type region 26 is disposed in the P-type well region 21 and surrounds the heavily doped N-type region 26. The outer sidewall of the P-well 21 may not only be spaced apart from the outer sidewall of the P-type heavily doped region 26, but also be in contact with the outer sidewall of the P-type heavily doped region 26. The P-type heavily doped semiconductor layer 27 is disposed at the bottom of the N-type semiconductor layer 20. The heavily doped P-type region 26, the P-type well region 21, the N-type semiconductor layer 20 and the heavily doped P-type semiconductor layer 27 form a PNP bipolar junction transistor. When a positive voltage is applied to the P-type heavily doped semiconductor layer 27 and the P-type heavily doped region 26 and the N-type heavily doped region 22 are grounded, a current flows from the heavily doped semiconductor layer 25 to the N-type heavily doped region 22 through the N-type semiconductor layer 20, the C-shaped N-type region 201 and the P-type well region 21 in sequence, and a current also flows from the P-type heavily doped semiconductor layer 27 to the P-type heavily doped region 26 through the N-type semiconductor layer 20 and the P-type well region 21 in sequence, so as to increase the current driving capability of the power semiconductor device 2.
Fig. 14 is a cross-sectional view of the alternate construction taken along line E-E' of fig. 12. The difference between FIG. 14 and FIG. 13 is that the N-type semiconductor layer 20 includes a semiconductor substrate 202 and an N-type epitaxial layer 203, the semiconductor substrate 202 can be an N-type semiconductor substrate or a P-type semiconductor substrate, the N-type epitaxial layer 203 is disposed on the semiconductor substrate 202, the N-type epitaxial layer 203 has a C-shaped N-type region 201, the P-type well 21 is disposed in the N-type epitaxial layer 203, the insulating layer 23 is disposed on the N-type epitaxial layer 203, and the heavily doped semiconductor layer 25 is disposed at the bottom of the semiconductor substrate 202.
Fig. 15 is a cross-sectional view of a fifth embodiment of the power semiconductor device of the present invention. Fig. 16 is a cross-sectional view of the structure of fig. 15 taken along line F-F'. Referring to fig. 7, fig. 15 and fig. 16, a fifth embodiment of the power semiconductor device of the present invention will be described. Compared with the second embodiment, the power semiconductor device 2 of the fifth embodiment further includes a P-type heavily doped region 26, and the heavily doped semiconductor layer 25 of the second embodiment is replaced by a P-type heavily doped semiconductor layer 27. The heavily doped P-type region 26 is disposed in the P-type well region 21 and surrounds the heavily doped N-type region 26. The outer sidewall of the P-well 21 may not only be spaced apart from the outer sidewall of the P-type heavily doped region 26, but also be in contact with the outer sidewall of the P-type heavily doped region 26. The P-type heavily doped semiconductor layer 27 is disposed at the bottom of the N-type semiconductor layer 20. The heavily doped P-type region 26, the P-type well region 21, the N-type semiconductor layer 20 and the heavily doped P-type semiconductor layer 27 form a PNP bipolar junction transistor. When a positive voltage is applied to the P-type heavily doped semiconductor layer 27 and the P-type heavily doped region 26 and the N-type heavily doped region 22 are grounded, a current flows from the heavily doped semiconductor layer 25 to the N-type heavily doped region 22 through the N-type semiconductor layer 20, the C-shaped N-type region 201 and the P-type well region 21 in sequence, and a current also flows from the P-type heavily doped semiconductor layer 27 to the P-type heavily doped region 26 through the N-type semiconductor layer 20 and the P-type well region 21 in sequence, so as to increase the current driving capability of the power semiconductor device 2.
FIG. 17 is a cross-sectional view of the alternate construction taken along line F-F' of FIG. 15. The difference between FIG. 17 and FIG. 16 is that the N-type semiconductor layer 20 includes a semiconductor substrate 202 and an N-type epitaxial layer 203, the semiconductor substrate 202 can be an N-type semiconductor substrate or a P-type semiconductor substrate, the N-type epitaxial layer 203 is disposed on the semiconductor substrate 202, the N-type epitaxial layer 203 has a C-shaped N-type region 201, the P-type well 21 is disposed in the N-type epitaxial layer 203, the insulating layer 23 is disposed on the N-type epitaxial layer 203, and the heavily doped semiconductor layer 25 is disposed at the bottom of the semiconductor substrate 202.
Fig. 18 is a cross-sectional view of a power semiconductor device according to a sixth embodiment of the present invention. Fig. 19 is a sectional view of the structure of fig. 18 taken along line G-G'. Referring to fig. 10, 18 and 19, a sixth embodiment of the power semiconductor device of the present invention will be described. Compared with the third embodiment, the power semiconductor device 2 of the sixth embodiment further includes a P-type heavily doped region 26, and the heavily doped semiconductor layer 25 of the third embodiment is replaced by a P-type heavily doped semiconductor layer 27. The heavily doped P-type region 26 is disposed in the P-type well region 21 and surrounds the heavily doped N-type region 26. The outer sidewall of the P-well 21 may not only be spaced apart from the outer sidewall of the P-type heavily doped region 26, but also be in contact with the outer sidewall of the P-type heavily doped region 26. The P-type heavily doped semiconductor layer 27 is disposed at the bottom of the N-type semiconductor layer 20. The heavily doped P-type region 26, the P-type well region 21, the N-type semiconductor layer 20 and the heavily doped P-type semiconductor layer 27 form a PNP bipolar junction transistor. When a positive voltage is applied to the P-type heavily doped semiconductor layer 27 and the P-type heavily doped region 26 and the N-type heavily doped region 22 are grounded, a current flows from the heavily doped semiconductor layer 25 to the N-type heavily doped region 22 through the N-type semiconductor layer 20, the C-shaped N-type region 201 and the P-type well region 21 in sequence, and a current also flows from the P-type heavily doped semiconductor layer 27 to the P-type heavily doped region 26 through the N-type semiconductor layer 20 and the P-type well region 21 in sequence, so as to increase the current driving capability of the power semiconductor device 2.
Fig. 20 is a cross-sectional view of the alternate construction taken along line G-G' of fig. 18. The difference between FIG. 20 and FIG. 19 is that the N-type semiconductor layer 20 includes a semiconductor substrate 202 and an N-type epitaxial layer 203, the semiconductor substrate 202 can be an N-type semiconductor substrate or a P-type semiconductor substrate, the N-type epitaxial layer 203 is disposed on the semiconductor substrate 202, the N-type epitaxial layer 203 has a C-shaped N-type region 201, the P-type well 21 is disposed in the N-type epitaxial layer 203, the insulating layer 23 is disposed on the N-type epitaxial layer 203, and the heavily doped semiconductor layer 25 is disposed at the bottom of the semiconductor substrate 202.
According to the embodiments, the power semiconductor device reduces the probability of heat generation by increasing the cross-sectional area through which current passes and the perimeter of the gate layer.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, so that equivalent variations and modifications in the shape, structure, characteristics and spirit of the present invention as described in the claims should be included in the scope of the present invention.

Claims (10)

1. A power semiconductor device, comprising:
an N-type semiconductor layer;
the P-type well region is arranged in the N-type semiconductor layer, wherein the P-type well region surrounds a C-shaped N-type region of the N-type semiconductor layer;
the N-type heavily doped region is arranged in the P-type well region and surrounds the C-shaped N-type region;
the insulating layer is arranged on the N-type semiconductor layer and covers part of the P-type well region, part of the N-type heavily doped region and all the C-shaped N-type regions;
and the gate layer is arranged on the insulating layer, and the shape of the gate layer is the same as that of the C-shaped N-type area.
2. The power semiconductor device of claim 1, wherein the N-type semiconductor layer is an N-type lightly doped substrate.
3. The power semiconductor device of claim 1, further comprising a heavily doped semiconductor layer disposed at a bottom of the N-type semiconductor layer.
4. The power semiconductor device of claim 1, wherein an outer sidewall of the P-well region is spaced apart from an outer sidewall of the heavily N-doped region.
5. The power semiconductor device according to claim 1, wherein each of the gate layer and the C-shaped N-type region has a first recess portion and a second recess portion communicating with each other, a width of the first recess portion is different from a width of the second recess portion, the first recess portion has a constant width, and the second recess portion has a gradual change width.
6. The power semiconductor device of claim 1, wherein the outer perimeter of the gate layer comprises at least two straight lines, the at least two straight lines being of equal length.
7. The power semiconductor device according to claim 1, wherein the gate layer has a recess having a constant width or a gradually varying width, and the insulating layer has the same shape as the gate layer.
8. The power semiconductor device of claim 1, further comprising:
the P-type heavily doped region is arranged in the P-type well region and surrounds the N-type heavily doped region;
and the P-type heavily doped semiconductor layer is arranged at the bottom of the N-type semiconductor layer.
9. The power semiconductor device of claim 1, wherein the N-type semiconductor layer is an N-type substrate.
10. The power semiconductor device of claim 1, wherein the N-type semiconductor layer further comprises:
a semiconductor substrate;
an N-type epitaxial layer disposed on the semiconductor substrate, the N-type epitaxial layer having the C-shaped N-type region, the P-type well region disposed in the N-type epitaxial layer, and the insulating layer disposed on the N-type epitaxial layer.
CN202011071299.1A 2020-10-09 2020-10-09 Power semiconductor device Pending CN112164720A (en)

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