CN111782574A

CN111782574A - Serial peripheral interface control method and serial peripheral interface controller

Info

Publication number: CN111782574A
Application number: CN202010676108.8A
Authority: CN
Inventors: 谢艳伟; 阎斌; 胡剑锋; 张国松
Original assignee: Beijing Sigbean Information Technology Co ltd
Current assignee: Beijing Sigbean Information Technology Co ltd
Priority date: 2020-07-14
Filing date: 2020-07-14
Publication date: 2020-10-16

Abstract

The embodiment of the invention discloses a serial peripheral interface control method and a serial peripheral interface controller, wherein the SPI controller comprises an interface circuit, a register and a time sequence control logic circuit, a configurable register value is obtained through the register, a command is converted into a time sequence required by SPI FLASH by taking the register value as a trigger value, and developers of the SPI controller can configure the time sequences required by different SPI FLASH external devices by only modifying the register value, so that data exchange can be carried out with SPI FLASH of most manufacturers on the market, and the SPI controller special for the SPI FLASH of each manufacturer is not required to be developed, thereby realizing a universal, highly compatible and configurable SPI controller.

Description

Serial peripheral interface control method and serial peripheral interface controller

Technical Field

The invention relates to the field of electronics, in particular to a serial peripheral interface control method and a serial peripheral interface controller.

Background

An SPI FLASH (Serial Peripheral Interface) is a Serial FLASH embedded with an SPI bus Interface, and has many models in the market, and SPI FLASH control methods of different manufacturers are different, and even SPI FLASH of different models produced by the same manufacturer are different in control method.

SPI (Serial Peripheral Interface) is a communication protocol. The SPI protocol operates in a Master-Slave mode (Master Slave), typically requiring one Master device (Master) and at least one Slave device (Slave).

The system on chip widely uses SPI FLASH as external equipment for loading program or reading and writing data for the system on chip. If a program is to be run on the SPI FLASH, the controller thereof must be dedicated, which makes it difficult for the conventional SPI controller (i.e., the serial peripheral device, i.e., the controller) to be compatible with the SPI FLASH of various models.

For an application occasion that an SPI FLASH external device which does not need to run a program only needs to use an SPI FLASH to read and write data, the traditional method is to use a general SPI controller, use software to configure a register of the SPI FLASH external device and use a standard SPI controller to send and receive data. However, this method takes much CPU time, and it is difficult to implement a SPI device with strict timing requirements to meet the timing requirements.

In the prior art, in an application occasion where an SPI FLASH external device of a program needs to be operated or data is read and written by using the SPI FLASH, since instruction systems of the SPI flashes produced by various manufacturers are not completely the same, a dedicated controller needs to be written for each SPI FLASH. The other type of SPI FLASH requires modification of the controller, the dedicated SPI controller is not flexible, and in actual operation, modification of the SPI controller consumes a lot of time and effort.

Disclosure of Invention

In view of the above, the present invention provides a method for controlling a serial peripheral interface and a serial peripheral interface controller, so as to improve the versatility of an SPI controller.

In a first aspect, an embodiment of the present invention provides a serial peripheral interface control method (SPI control method), including:

acquiring a system clock;

acquiring a clock configuration data value and an instruction configuration data value from a register;

adjusting the system clock to a working clock according to a clock configuration data value;

and acquiring an instruction, and analyzing a time sequence signal corresponding to the working clock according to the instruction and the instruction configuration data value.

Preferably, the analyzing the timing signal corresponding to the operating clock according to the instruction and the instruction configuration data value includes:

analyzing the instruction into an enabling signal, a protocol clock signal and an output time sequence signal; and

and receiving an input timing signal according to the instruction.

Preferably, adjusting the system clock to an operating clock comprises:

adjusting a polarity of the system clock; and

adjusting a clock period of the system clock.

In a second aspect, an embodiment of the present invention provides a serial peripheral interface controller (SPI controller), including:

an interface circuit;

a register for storing a clock configuration data value and an instruction configuration data value; and

a timing control logic circuit configured to perform the steps of:

acquiring a system clock through the interface circuit;

and acquiring an instruction through the interface circuit, and analyzing a time sequence signal corresponding to the working clock according to the instruction and the instruction configuration data value.

Preferably, the interface circuit includes a clock interface circuit, an output interface circuit, an input interface circuit, and an enable interface circuit.

and receiving an input timing signal according to the instruction.

Preferably, parsing the instruction into an enable signal, a protocol clock signal, and an output timing signal comprises:

wherein the protocol clock signal is configured to be output by the clock interface circuit; the input timing signal or the output timing signal is configured to be output through the output interface circuit; the enable signal is configured to be output by the enable interface circuit.

Preferably, receiving the input timing signal according to the instruction includes:

and acquiring the input time sequence signal through the input interface circuit.

The SPI controller comprises an interface circuit, a register and a time sequence control logic circuit, a configurable register value is obtained through the register, a command is converted into a time sequence required by the SPI FLASH by taking the register value as a trigger value, and developers of the SPI controller can configure the time sequences required by different SPI FLASH external devices by only modifying the register value, so that data exchange can be carried out with the SPI FLASH of most manufacturers on the market, and the development of a special SPI controller for the SPI FLASH of each manufacturer is not needed, so that the universal, high-compatibility and configurable SPI controller is realized. Therefore, the inconvenience that the special SPI controller can only communicate with the SPI FLASH of a specific manufacturer is solved. Through the SPI controller provided by the embodiment of the invention, SPIFLASH external equipment of most manufacturers on the market can be compatible only by modifying the configuration data value of the register, so that the development time of the SPI controller is greatly shortened, and the special SPI controller is prevented from being repeatedly developed.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

FIG. 1 is a schematic diagram of a system-on-chip SoC;

FIG. 2 is a pin diagram of an SPI FLASH;

FIG. 3 is a schematic diagram of an SPI controller communication system according to an embodiment of the present invention;

FIG. 4 is a timing diagram illustrating the data exchange between the SPI controller and the SPI FLASH according to the embodiment of the present invention;

fig. 5 is a flowchart of a control method of the SPI controller according to the embodiment of the present invention.

Detailed Description

The present invention will be described below based on examples, but the present invention is not limited to only these examples. In the following detailed description of the present invention, certain specific details are set forth. It will be apparent to one skilled in the art that the present invention may be practiced without these specific details. Well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the present invention.

Further, those of ordinary skill in the art will appreciate that the drawings provided herein are for illustrative purposes and are not necessarily drawn to scale.

Meanwhile, it should be understood that, in the following description, a "circuit" refers to a conductive loop constituted by at least one element or sub-circuit through electrical or electromagnetic connection. When an element or circuit is referred to as being "connected to" another element or element/circuit is referred to as being "connected between" two nodes, it may be directly coupled or connected to the other element or intervening elements may be present, and the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled" or "directly connected" to another element, it is intended that there are no intervening elements present.

Unless the context clearly requires otherwise, throughout the description, the words "comprise", "comprising", and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is, what is meant is "including, but not limited to".

In the description of the present invention, it is to be understood that the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance. In addition, in the description of the present invention, "a plurality" means two or more unless otherwise specified.

Fig. 1 is a schematic diagram of a system on chip SoC.

Referring to fig. 1, a System on a chip (SoC) generally includes a CPU3, an SPI controller 1, and a memory space 4. The CPU3 is communicatively connected to the SPI controller 1 and the memory space 4 via an on-chip bus 6. The on-chip Bus 6 may be an AHB Bus (Advanced High performance Bus), and the storage space 4 may be a DMA (Direct Memory Access), wherein the SPI controller 1 communicates with the external device SPI FLASH2 through the SPI Bus 7. In the system on chip, the SPI controller 1 converts parallel data transmitted by the CPU3 into serial data through the on-chip bus 6, and exchanges data with the external device SPIFLASH 2; and converts serial data transmitted from the slave SPI FLASH2 into parallel data, and transmits the parallel data to the CPU3 through the on-chip bus 6. The SPI controller 1 will exchange data with the system on chip if it is selected by the system on chip.

SPI FLASH2 is a non-volatile, erasable memory. The SPI FLASH2 is widely used in handheld devices such as mobile phones and tablet computers, and by storing data in the SPI FLASH2, the handheld devices such as mobile phones and tablet computers can provide a large storage space for users.

Since the command systems of the SPI FLASH2 produced by different external device manufacturers are not completely the same, when the SPI FLASH2 is selected, the corresponding command is converted into the timing sequence required by the corresponding SPI FLASH2 to perform data exchange. In the prior art, when a master needs to communicate with an SPI FLASH2 (slave), it is necessary to customize a dedicated SPI controller (master) for a specific manufacturer's SPI FLASH2 (slave), which is less flexible. Another implementation in the prior art is to develop the SPI controller 1 (virtual master) by means of software, but the driver of the software SPI controller 1 occupies the CPU3 resource and it is difficult to meet the timing requirement of the SPI FLASH2 (slave). In order to solve the problems that a dedicated SPI controller 1 (master device) is poor in flexibility and a software SPI controller 1 (virtual master device) is difficult to meet the timing requirements of SPIFLASH2 (slave devices) of multiple manufacturers and developers have to develop a specific SPI controller 1 for each SPI FLASH2 and consume energy, the embodiment of the invention discloses a general, highly compatible and configurable SPI controller 1 (master device).

The pin of the SPI FLASH is described in detail below with reference to fig. 2.

Fig. 2 is a pin diagram of an SPI FLASH. The SPI FLASH is a serial FLASH with an embedded SPI bus interface. Wherein, SPI (Serial Peripheral Interface) is a communication protocol; FLASH, also known as FLASH memory, is a type of non-volatile memory. The SPI protocol operates in a Master-Slave mode (Master Slave), typically requiring one Master device (Master) and at least one Slave device (Slave).

For an exemplary SPI Flash chip, pin VCC and pin VSS are power and ground, respectively, for powering the SPI Flash. The write protect pin WP and suspend pin HOLD are used for data protection and low power operation in idle mode. FCS, SO, SI, and FCLK are pins used to communicate with the master device SPI controller. Wherein, FCS is the chip selection signal of SPI FLASH, the low level is effective, the chip selection signal is provided by the master device; SO is a serial data output pin of the SPI FLASH, and data is output to the SPI controller of the main equipment from the SPI FLASH on the falling edge of a clock; the SI is a serial data input pin of the SPI FLASH and is used for receiving a transmission instruction, an address and data of the SPI controller of the main equipment and latching the transmission instruction, the address and the data into the SPI FLASH device at a rising edge; FCLK is the serial clock pin of SPIFLASH, and is usually provided by the master device and accesses the serial clock signal of the master device to the serial clock pin of SPI FLASH. The SPI FLASH of different manufacturers has different instruction systems, for example, the chip select signal is usually active low, and between two instructions, in order to distinguish the arrival of the next instruction, the chip select signal is usually pulled high for several clock cycles, and then pulled low again, so that the timing sequence of the chip select signal sent by the dedicated SPI controller is usually determined according to the parameters of the SPI FLASH of a specific manufacturer, and once determined, a specific hardware circuit is created, corresponding to the logic on the chip consisting of logic gates. By being not modifiable after fabrication into a chip. Therefore, the existing SPI controller can only accommodate SPI FLASH of a specific manufacturer. Different systems on chip may use SPIFLASH from different manufacturers, requiring developers to re-develop SPI controllers. In addition to the chip select signal, correspondingly, different manufacturers may have specific timing requirements, similarly, the requirements of the SPI FLASH of different manufacturers on the clock cycle may also be different, and the timing signal corresponding to the clock cycle sent by the dedicated SPI controller is also fixed, and once determined, the timing signal will be made into a hardware circuit, corresponding to the logic formed by the logic gates on the chip. By being not modifiable after fabrication into a chip. Therefore, a dedicated SPI controller can only accommodate SPI FLASH of a particular manufacturer.

The SPI controller is connected with the SPI FLASH through an SPI bus. The SPI bus requires 4 communication lines, MISO, MOSI, SCLK, and CS, respectively. Wherein the MISO is used for master input and slave output; MOSI is used for the master equipment to output the slave equipment input; SCLK is clock signal, provided by the master device; CS is a slave enable signal, controlled by the master.

In order to enable the SPI controller to adapt to various different SPI FLASH external devices, the SPI controller is required to be capable of outputting specific sequential signals to pins corresponding to the SPI FLASH through four communication lines of MISO, MOSI, SCLK and CS according to parameters of different SPI FLASH manufacturers, the SPI FLASH receives correct sequential signals and can respond to the SPI controller of the main device, and therefore data exchange is carried out between the SPI controller and the main device.

The embodiment of the invention discloses a configurable SPI controller, which is characterized in that the SPI controller is configured, configuration data are used as trigger values, and therefore a specific time sequence required by SPIFLASH can be input or output in four communication lines of MISO, MOSI, SCLK and CS, and data can be exchanged with most SPI FLASH in the market.

Fig. 3 is a schematic diagram of an SPI controller communication system according to an embodiment of the present invention.

Referring to fig. 3, the CPU and the memory space in the system on chip are simplified to the user side 8. The SPI controller 1 of the present embodiment communicates with the SPI FLASH2 through the SPI bus when selected by the user terminal 8. The pin correspondence of the SPI bus between the master device end of the SPI controller 1 and the slave device SPI FLASH2 is shown in table 1:

SPI bus	SPI controller pin	Pin of SPI FLASH
			MISO	SDI	SO
MOSI	SDO	SI
			SCLK	SCLK	FCLK
CS	CS	FCS

TABLE 1

The SPI controller 1 of the present embodiment includes an interface circuit 13, a register 11, and a timing control logic circuit 12. The interface circuit 13 includes a clock interface circuit SCLK, an output interface circuit SDO, an input interface circuit SDI, and an enable interface circuit CS.

The register 11 of the present embodiment is a parameter configuration register configured to acquire a clock configuration data value and an instruction configuration data value. The clock configuration data values include clock period, clock polarity, etc.; the instruction configuration data value comprises a clock phase and a continuously written data length; the parameter configuration register also includes a mode selection register.

For example, the following registers may be set as parameter configuration registers:

a LENGTH register for receiving a configurable data LENGTH, e.g. for the case of continuous writes being required, the total data LENGTH can be configured, e.g. 256 bits or 1024 bits.

A LATENCY register for receiving a configurable clock phase, e.g. the number of SCLK cycles required for a rising clock edge to arrive after CS of the SPI controller 2 is asserted

A DIV register to receive a configurable division number, such as: divide by 2,4, 8.

The MODE register is used for configuring the working MODE of the SPI controller, for example: 1 is the working mode of the SPI BUS, and 0 is the working mode of I2C (bidirectional two-wire synchronous serial BUS).

The CKP register is used to configure the clock polarity of the SPI controller, for example: 1 is the rising edge sample and 0 is the falling edge sample.

The following takes the clock cycle timing signal output from the SPI controller 1 to the SCLK pin as an example to explain how the SPI controller of this embodiment outputs the clock cycle (timing signal) required by the specific SPI FLASH at the corresponding interface circuit by setting the register as the parameter configuration register and using the value in the parameter configuration register as the trigger value, so that the SPI controller 1 of this embodiment can output the clock cycle required by the SPI FLASH of another manufacturer only by modifying the parameter configuration register when the SPI FLASH device of another manufacturer is replaced. By analogy, only the value of the parameter configuration register needs to be modified, and the time sequence signal required by the SPI FLASH of another manufacturer can be generated on the SPI bus, so that the SPI controller of the embodiment can adapt to SPI FLASH devices of different manufacturers in the market.

The SPI controller acquires the system clock, and acquires the clock configuration data in the register 11 through the sequential control logic circuit 12, so that the SPI controller 1 can adjust the system clock to the working clock, and output the working clock to the bus corresponding to the SPI FLASH2 through the interface circuit 13. In an alternative implementation manner, the SPI controller 1 of the present embodiment can obtain the system clock of the user terminal 8 through the timing control logic circuit 12. Specifically, the timing control logic 12 may obtain the system clock of the client 8 through the system-on-chip bus.

And adjusting the system clock to be a working clock according to the clock configuration data value, namely adjusting the clock period of the system clock according to the configuration value of the register, so as to output the clock period which can be responded by a manufacturer SPI FLASH2 on the SLCK port.

After acquiring the system clock, in an alternative implementation, the SPI controller 1 may acquire the configuration data value in the DIV register (for receiving a configurable frequency division number, for example,

frequency division

2,4, or 8), take the configuration data value in the DIV register as a trigger condition, and convert the frequency of the system clock into an operating clock frequency (the frequency is the reciprocal of the period) when the trigger condition is reached. Specifically, the frequency division number is obtained through the DIV register, so that the clock period of the system clock is divided to generate the clock period of the working clock.

The serial data exchange between the SPI controller 1 and the SPI FLASH2 can be performed only in the same clock cycle, and the highest operating frequency of the SPI FLASH2 of different manufacturers may be different. The system clock obtained by the SPI controller 1 through the system on chip is usually 200MHZ, however, the external device SPI FLASH2 cannot respond to the frequency of 200MHZ (the frequency is too high), and in order to communicate with the SPI FLASH2, the timing control logic 12 needs to divide the frequency of 200MHZ of the system clock according to the clock configuration data value in the register 11. That is, with the configuration data value in the DIV register as the trigger condition, when the trigger condition is reached, the frequency of the system clock is converted to the operating clock frequency, so that a clock cycle capable of operating normally by the SPI FLASH2 is given on the SCLK interface.

Specifically, the timing control logic circuit 12 obtains the value in the DIV register in the register 11. Adjusting the working clock to 100MHZ in response to being the value 2 in the DIV register; responding to the value in the DIV register being 4, adjusting the working clock to be 50 MHZ; by analogy, the operating clock is adjusted to 25MHZ in response to the value in the DIV register being 8.

In an alternative implementation, this can be achieved by the following circuit description language:

module spi _ controller (clk, rstn, sclk, sdo, sdi, cs); // define an SPI controller

Input clk; // acquire System clock 200MHZ

Input rstn; // acquiring reset signal

Output sclk; I/O sclk Pin output SPIFLASH clock

Output sdo; // output the instruction through the sdo pin

Output cs; // output SPIFLASH enable bit over cs pin

Input sdi; // receiving SPIFLASH data through sdi pin

The system clock is divided according to the clock configuration data value of the parameter register DIV, thereby generating the operating clock. DIV can receive clock configuration data values of 2,4 and 8, if DIV is 2, divide frequency for system clock 2; if DIV is 4, dividing the frequency of system clock by 4; if DIV is 8, divide the system clock by 8. Assuming that the working clock of the SPI FLASH of a specific manufacturer is 50MHZ, and the system clock is 200MHZ at this time, it is calculated that the system needs to be divided by 4. This can be achieved by the following circuit description language:

// defining a counter with an initial value of 0, a maximum value of 3,

reg DIV [3:0]// define register for receiving configurable divide number

reg [3:0] cnt; // define a counter

always @ (posegge clk or negegge rstn)// with the rising edge of the system clock or the falling edge of the reset signal as the trigger condition

begin

if (! rstn)// if spi _ controller is reset

cnt < (r) > 1' b 0; /clear the counter

else if (cnt)// when the counter counts to the maximum value, clear the counter

cnt < (r) > 1' b 0; the initial value of the counter is 0

else

(iii) clko < ═ cnt + 1; // counter increments by one each time it acquires a rising edge of the system clock

end

The counter CNT defined by the register DIV is used as a trigger condition for the inversion of the operating clock, so as to obtain the divided operating clock CLKO. This can be achieved by the following circuit description language:

reg clko; // define the working clock

begin

if (! rstn)// if spi _ controller is reset

(vii) clko < ═ 1' b 0; // the initial value of the operating clock is 0

else if cnt is equal to div// when the counter counts to 4,

(iii) clko < - > -clko; take the inverse of the working clock

end

By acquiring the value of the DIV register, taking the value of the DIV register as a trigger value, and responding to the trigger value, a working clock is generated, and the working clock has a clock cycle required by the specific SPI FLASH2, so that the SPI controller 1 of the present embodiment can provide the clock cycle required by the specific SPI FLASH2 on the SCLK interface. Assuming that a different clock cycle is required to replace the SPIFLASH2 of another manufacturer, the SPI controller 1 of the present embodiment can generate another clock cycle by only modifying the DIV register value without re-developing a new SPI controller 1. Similarly, in order to meet the special requirements of the new SPI FLASH2 on timing at other pins, data can be exchanged with the new SPI FLASH2 by modifying the values of other registers and generating the correct timing at the corresponding pins according to the corresponding register values.

In an alternative implementation, the following registers may be defined to implement the adjustment of the timing signals of other pins, for example:

reg LENGTH [7:0]// define registers for receiving configurable data LENGTH.

Reg LATENCY [2:0]// define registers for receiving configurable clock phases.

Reg MODE [1:0]// define the register, is used for disposing the MODE of operation of the SPI controller.

Reg CKP [7:0]// define registers to configure the SPI controller's clock polarities, for example: 1 is the rising edge sample and 0 is the falling edge sample.

Similarly, for whether the sampling time is a rising edge or a falling edge, specifically, a CKP register may be defined, and the sampling polarity of the SPI controller may be changed by using the configuration data value of the CKP register as a trigger condition.

The sequential control logic circuit 12 of this embodiment obtains the system clock, converts the system clock into the working clock according to the clock configuration data by the register 11, then analyzes the communication instruction of the user end 8 into the sequential signal corresponding to the working clock, and sends or receives the corresponding sequential signal through the interface circuit 13, thereby being able to exchange data with the external device SPI FLASH 2.

The SPI controller 1 of this embodiment can provide timing signals for normal operation of different manufacturers of SPI FLASH2 by changing the clock configuration data value and the instruction configuration data value of the register 11, and thus, it is not necessary to develop a dedicated SPI controller 1 for a specific manufacturer, and it is only necessary to modify the register to adapt to the timing of operation of different manufacturers of SPI FLASH 2.

And acquiring an instruction, and analyzing a time sequence signal corresponding to the working clock according to the instruction and the instruction configuration data value. Analyzing the instruction into an enabling signal, a protocol clock signal and an output time sequence signal; and receiving an input timing signal according to the instruction.

The following explains the analysis of the timing signal corresponding to the operating clock according to the instruction and the instruction configuration data value by taking a read instruction as an example.

Fig. 4 is a timing diagram of the data exchange between the SPI controller and the SPI FLASH according to the embodiment of the present invention.

The timing control logic 12 of the present embodiment can obtain the command through the client 8. The timing control logic circuit 12 resolves the timing signal corresponding to the working clock according to the instruction and the instruction configuration data value, including resolving the instruction into an enable signal, a protocol clock signal and an output timing signal. Wherein the protocol clock signal is configured to be output by the clock interface circuit; the input timing signal or the output timing signal is configured to be output through the output interface circuit; the enable signal is configured to be output by the enable interface circuit. And receiving an input timing signal according to the instruction. And acquiring the input time sequence signal through the input interface circuit.

Specifically, the CS pin of the SPI controller 1 is connected to the FCS pin of the SPI FLASH2, and the timing control logic circuit 12 transmits the enable signal through the CS pin. The SCLK pin of SPI controller 1 is connected to the FCLK pin of SPI FLASH2, and timing control logic circuit 12 sends working clock signal through SCLK. The SDI pin of the SPI controller 1 is connected to the SO pin of the SPI FLASH2, and the timing control logic 12 sends commands and addresses through the SDI pin. The SDI of the SPI controller 1 is used for connecting the SO pin of the SPI FLASH2, and the timing control logic circuit 12 receives feedback data of the SPI FLASH2 through the SDI. Wherein, the enable signal is active low, and the register 11 of the present embodiment can be configured to be active low; the working clock can also adjust the clock period through the register 11 of the embodiment; the transmission instruction and the address can be configured as a rising edge sample by the register 11 of the present embodiment, the feedback data can be configured as a rising edge sample by the register 11 of the present embodiment or the transmission instruction and the address can be configured as a falling edge sample by the register 11 of the present embodiment, and the feedback data can be configured as a falling edge sample by the register 11 of the present embodiment.

Referring to fig. 4, the SPI controller communicates with the SPI FLASH, first pulling the enable signal CS low.

The clock signal of the timing control logic circuit is sent to the SCLK pin through the interface circuit CLK, and the timing control logic circuit sends a read command and an address through the SDO pin at the rising edge of the clock signal CLK.

Specifically, S1 indicates that the SPI controller sends a read command through the SDO interface on the rising edge from the 0 th clock cycle to the 7 th clock cycle, and S2 indicates that the SPI controller sends an address through the SDO interface on the rising edge from the 8 th clock cycle to the 31 th clock cycle.

After receiving the read instruction and the address through the SI pin, the SPI FLASH feeds data in the address back to an SDI pin of the SPI controller through an SO pin, and the SDI of the SPI controller samples the feedback data at the rising edge of a working clock.

Specifically, S3 indicates that the SPI controller receives the data fed back by the SPI FLASH through the SDI pin of the SPI controller on the rising edge of the SPI controller from the 32 th clock cycle to the 39 th clock cycle.

Through S1, S2, and S3, the SPI controller implements one data exchange with the SPI FLASH.

When the SPI controller communicates with the SPI FLASH, the enable signal is active high or active low, the frequency, the transmission instruction, and the address of the operating clock can be configured to be sampling at a rising edge or sampling at a falling edge by the register 11 of this embodiment, and the feedback data can be configured to be sampling at a rising edge or sampling at a falling edge by the register 11 of this embodiment. That is, the specific parameters can be configured by the register, and the values in the register are used as the trigger signals, so as to obtain the timing signals of the SPI FLASH of different manufacturers. Thus, the present embodiment can provide a universal, configurable, highly compatible SPI controller.

Fig. 5 is a flowchart of a control method of the SPI controller according to the embodiment of the present invention. Referring to fig. 5, the control method of the present embodiment includes:

step 100: a system clock is acquired.

In an alternative implementation, the SPI controller can obtain the system clock via the on-chip bus.

Step 200: clock configuration data values and instruction configuration data values are obtained from the registers.

In an alternative implementation, the SPI controller can obtain the values through registers, such as obtaining clock configuration data values and command configuration data values.

Step 300: adjusting the system clock to a working clock according to a clock configuration data value; adjusting a polarity of the system clock; and adjusting a clock period of the system clock.

In an optional implementation manner, a clock configuration data value may be obtained, and the system clock is divided according to the clock configuration data value to adjust the clock period of the system clock, that is, the clock frequency of the system clock is adjusted to the clock frequency of the working clock. The polarity of the system clock may be adjusted by using the rising or falling edge of the system clock as a trigger.

Step 400: and acquiring an instruction, and analyzing a time sequence signal corresponding to the working clock according to the instruction and the instruction configuration data value. Analyzing the instruction into an enabling signal, a protocol clock signal and an output time sequence signal; and receiving an input timing signal according to the instruction.

In the SPI control method according to this embodiment, the clock configuration data value and the command configuration data value are acquired from the register, and the system clock is set as the operating clock, so that the command can be analyzed as the implementation signal corresponding to the operating clock according to the system clock, the command can be analyzed as the enable signal, the protocol clock signal, and the output timing signal, and the input timing signal is received, thereby acquiring the corresponding data. The SPI control method can acquire the clock configuration data value and the instruction configuration data value according to the register, so that the SPI control method can adapt to SPI FLASH of different manufacturers, and the technical problem that a traditional SPI controller can only communicate with the SPI FLASH of a specific manufacturer is solved; the SPI controller of the embodiment enters the working state only when the system on a chip is selected, so that the technical problem that the SPI controller developed in a software mode occupies CPU resources is solved.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for controlling a serial peripheral interface, the method comprising:

acquiring a system clock;

2. The method of claim 1, wherein resolving a timing signal corresponding to the operating clock from the instruction and the instruction configuration data value comprises:

and receiving an input timing signal according to the instruction.

3. The method of claim 1, wherein adjusting the system clock to an operating clock comprises:

adjusting a polarity of the system clock; and

adjusting a clock period of the system clock.

4. A serial peripheral interface controller, the controller comprising:

an interface circuit;

a timing control logic circuit configured to perform the steps of:

acquiring a system clock through the interface circuit;

5. The serial peripheral interface controller of claim 4, wherein the interface circuit comprises a clock interface circuit, an output interface circuit, an input interface circuit, and an enable interface circuit.

6. The SPI controller of claim 5, wherein resolving a timing signal corresponding to the operating clock from the instruction and the instruction configuration data value comprises:

and receiving an input timing signal according to the instruction.

7. The SPI controller of claim 6, wherein parsing the instructions into an enable signal, a protocol clock signal, and an output timing signal comprises:

8. The SPI controller of claim 6, wherein receiving an incoming timing signal according to the instruction comprises:

9. A system on a chip, comprising:

the serial peripheral interface controller of any of claims 4-8.