CN111640676A - Method for forming metal bump and semiconductor device - Google Patents
Method for forming metal bump and semiconductor device Download PDFInfo
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- CN111640676A CN111640676A CN202010531380.7A CN202010531380A CN111640676A CN 111640676 A CN111640676 A CN 111640676A CN 202010531380 A CN202010531380 A CN 202010531380A CN 111640676 A CN111640676 A CN 111640676A
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- 239000002184 metal Substances 0.000 title claims abstract description 291
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 291
- 238000000034 method Methods 0.000 title claims abstract description 75
- 239000004065 semiconductor Substances 0.000 title claims abstract description 33
- 238000002161 passivation Methods 0.000 claims description 25
- 238000009713 electroplating Methods 0.000 claims description 17
- 238000005530 etching Methods 0.000 claims description 10
- 238000004544 sputter deposition Methods 0.000 claims description 10
- 238000005272 metallurgy Methods 0.000 claims description 7
- 238000010586 diagram Methods 0.000 description 45
- 238000001312 dry etching Methods 0.000 description 5
- 238000001039 wet etching Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004952 Polyamide Substances 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910001080 W alloy Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229920002647 polyamide Polymers 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The application discloses a method for forming a metal bump and a semiconductor device. The method for forming the metal bump comprises the steps that an insulating layer is formed on the front surface of a wafer, a first through opening is formed in the insulating layer corresponding to a pad, the size of the first opening close to the pad is smaller than that of the first opening far away from the pad, and the size of the first opening close to the pad is smaller than that of the pad; then forming a metal bump in the first opening; and removing the insulating layer which is not covered by the orthographic projection of the metal bump on the wafer. The size of the position, close to the bonding pad, of the metal bump formed in the first opening is smaller than that of the bonding pad and is also smaller than that of the position, far away from the bonding pad, of the metal bump, so that the size of the metal bump is smaller than that of the metal bump with basically consistent sizes at two ends in the prior art, the usage amount of metal can be reduced on the premise that the electric connection contact area of the metal bump is not reduced, and the cost is saved on the premise that the reliability of a semiconductor device is not influenced.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and more particularly, to a method for forming a metal bump and a semiconductor device.
Background
In forming electrical connections between different semiconductor devices, metal bumps are generally used, and in the prior art, metal bumps are generally formed directly in through holes of a pre-formed mask layer by using an electroplating process. However, the metal bumps are usually made of metal materials with high cost, such as gold and copper, and in order to improve the reliability of the electrical connection between the semiconductor devices, the size of the metal bumps cannot be designed to be too small to ensure that the metal bumps have a contact area meeting the requirement, which results in high usage of metal in the method for forming the metal bumps in the prior art, thereby resulting in high cost.
Disclosure of Invention
The present application provides a method for forming a metal bump and a semiconductor device, which can reduce the amount of metal used in forming the metal bump and reduce the cost.
In order to solve the technical problem, the application adopts a technical scheme that:
provided is a method for forming a metal bump, including: forming a patterned insulating layer on the front surface of a wafer, wherein a through first opening is arranged at a pad position of the insulating layer corresponding to the front surface of the wafer, the size of the first opening close to the pad position is smaller than that of the first opening far away from the pad position, and the size of the first opening close to the pad position is smaller than that of the pad; forming a metal bump in the first opening; and removing the insulating layer which is not covered by the orthographic projection of the metal bump on the wafer.
The method comprises the following steps of forming a patterned insulating layer on the front surface of a wafer, wherein a through first opening is arranged at a pad position of the insulating layer corresponding to the front surface of the wafer, the size of the first opening close to the pad position is smaller than that of the first opening far away from the pad position, and the size of the first opening close to the pad position is smaller than that of the pad: forming a patterned first insulating layer on the front surface of the wafer, wherein at least one first through hole is formed in the position, corresponding to each bonding pad, of the first insulating layer, and the size of each first through hole is smaller than that of each bonding pad; and forming a patterned second insulating layer on the surface of one side, far away from the wafer, of the first insulating layer, wherein a second through hole is formed in the position, corresponding to each bonding pad, of the second insulating layer, the size of each second through hole is larger than that of each first through hole, the second through holes are communicated with the first through holes, and the second through holes and the first through holes form the first openings.
The method comprises the following steps of forming a patterned second insulating layer on the surface of one side, away from the wafer, of the first insulating layer, wherein the method comprises the following steps: forming a sputtering metal layer in the surface of one side of the first insulating layer, which is far away from the wafer, and the first through hole; the step of forming a metal bump in the first opening includes: and forming a metal bump on the sputtering metal layer in the first opening by utilizing an electroplating process, wherein the surface of the metal bump, which is far away from the front surface of the wafer, is flush with the surface of the second insulating layer, which is far away from the front surface of the wafer.
Wherein, after the step of forming the patterned second insulating layer on the surface of the first insulating layer on the side far away from the wafer, the method comprises the following steps: forming a sputtered metal layer in the first opening; the step of forming a metal bump in the first opening includes: and forming a metal bump on the sputtering metal layer in the first opening by utilizing an electroplating process, wherein the surface of the metal bump, which is far away from the front surface of the wafer, is flush with the surface of the second insulating layer, which is far away from the front surface of the wafer.
Wherein, before the step of forming the patterned insulating layer on the front surface of the wafer, the method further comprises the following steps: forming a patterned passivation layer on the front surface of the wafer, wherein a through second opening is formed in the passivation layer at a position corresponding to the pad, and the size of the second opening is smaller than or equal to that of the pad; forming an under bump metal layer on the surface of one side, away from the wafer, of the passivation layer and in the second opening; after the step of removing the insulating layer not covered by the orthographic projection of the metal bump on the wafer, the method further comprises the following steps: and etching to remove the under bump metal layer which is not covered by the orthographic projection of the metal bump on the wafer.
Wherein the size of the second opening is smaller than or equal to the size of the second through hole; and/or at least one side wall of the first through hole is aligned with the under bump metal layer at the position of the side wall of the second opening.
In order to solve the above technical problem, another technical solution adopted by the present application is:
provided is a semiconductor device including: the front surface of the wafer is provided with a plurality of bonding pads; the metal bumps are correspondingly arranged at the positions of the bonding pads, the size of one end, close to the bonding pads, of each metal bump is smaller than that of one end, far away from the bonding pads, of each metal bump, and the size of one end, close to the bonding pads, of each metal bump is smaller than that of the bonding pads; the patterned first insulating layer is positioned on the periphery of one end, close to the bonding pad, of the metal bump, and the first insulating layer is only distributed in an area covered by the orthographic projection of the metal bump on the wafer.
Wherein the metal bump includes: at least one first metal column, around which the first insulating layer is disposed, one end of which is electrically connected to the pad at a corresponding position; one end of the second metal column is electrically connected with the other end of the at least one first metal column at the corresponding position; in a direction parallel to the front surface of the wafer, the sum of the cross-sectional dimensions of all the first metal columns corresponding to each pad is smaller than the cross-sectional dimension of the second metal column, and the cross-sectional dimension of each first metal column is smaller than 1/2 of the cross-sectional dimension of the second metal column.
The metal bump comprises a plurality of first metal columns, and the plurality of first metal columns are symmetrically arranged around a central axis of the second metal column.
Wherein, the semiconductor device further comprises: the passivation layer covers the front surface of the wafer, a through second opening is arranged at a position corresponding to the pad, and the size of the second opening is smaller than or equal to that of the pad; and the patterned under bump metal layer is arranged in the second opening and is electrically connected with the bonding pad at the corresponding position, and the under bump metal layer is only distributed in an area covered by the orthographic projection of the metal bump on the wafer.
The beneficial effect of this application is: different from the situation of the prior art, the method for forming the metal bump provided by the application forms a patterned insulating layer on the front surface of the wafer, a through first opening is arranged at a bonding pad position of the insulating layer corresponding to the front surface of the wafer, the size of the first opening close to the bonding pad position is smaller than that of the first opening far away from the bonding pad position, and the size of the first opening close to the bonding pad position is smaller than that of the bonding pad; then forming a metal bump in the first opening; and removing the insulating layer which is not covered by the orthographic projection of the metal bump on the wafer. The size of the position, close to the bonding pad, of the metal bump formed in the first opening is smaller than that of the bonding pad and is also smaller than that of the position, far away from the bonding pad, of the metal bump, and therefore the size of the metal bump is smaller than that of the metal bump with the two ends of basically consistent in size in the prior art.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings without creative efforts. Wherein:
FIG. 1 is a schematic flow chart illustrating a method for forming a metal bump according to an embodiment of the present disclosure;
FIG. 2a is a schematic structural diagram of an embodiment corresponding to step S11 in FIG. 1;
FIG. 2b is a schematic structural diagram of an embodiment corresponding to step S12 in FIG. 1;
FIG. 2c is a schematic structural diagram of an embodiment corresponding to step S13 in FIG. 1;
FIG. 3 is a schematic flow chart illustrating one embodiment of the step included in step S11 in FIG. 1;
FIG. 4 is a schematic structural diagram of an embodiment corresponding to step S111 in FIG. 3;
FIG. 5 is a schematic flow chart illustrating another embodiment of a method for forming a metal bump according to the present application;
FIG. 6a is a schematic structural diagram of an embodiment corresponding to step S21 in FIG. 5;
FIG. 6b is a schematic structural diagram of an embodiment corresponding to step S22 in FIG. 5;
FIG. 6c is a schematic structural diagram of an embodiment corresponding to step S23 in FIG. 5;
FIG. 6d is a schematic structural diagram of an embodiment corresponding to step S24 in FIG. 5;
FIG. 6e is a schematic structural diagram of an embodiment corresponding to step S25 in FIG. 5;
FIG. 7 is a schematic flow chart illustrating another embodiment of a method for forming a metal bump according to the present application;
FIG. 8a is a schematic structural diagram of an embodiment corresponding to step S31 in FIG. 7;
FIG. 8b is a schematic structural diagram of an embodiment corresponding to step S32 in FIG. 7;
FIG. 8c is a schematic structural diagram of an embodiment corresponding to step S33 in FIG. 7;
FIG. 8d is a schematic structural diagram of an embodiment corresponding to step S34 in FIG. 7;
FIG. 8e is a schematic structural diagram of an embodiment corresponding to step S35 in FIG. 7;
FIG. 9 is a schematic flow chart illustrating another embodiment of a method for forming a metal bump according to the present application;
FIG. 10a is a schematic structural diagram of an embodiment corresponding to step S41 in FIG. 9;
FIG. 10b is a schematic structural diagram of an embodiment corresponding to step S42 in FIG. 9;
FIG. 10c is a schematic structural diagram of an embodiment corresponding to step S43 in FIG. 9;
FIG. 10d is a schematic structural diagram of an embodiment corresponding to step S44 in FIG. 9;
FIG. 10e is a schematic structural diagram of an embodiment corresponding to step S45 in FIG. 9;
FIG. 10f is a schematic structural diagram of an embodiment corresponding to step S46 in FIG. 9;
FIG. 10g is a schematic structural diagram of another embodiment corresponding to step S46 in FIG. 9;
fig. 11 is a schematic structural diagram of an embodiment corresponding to step S47 in fig. 9.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments that can be obtained by a person skilled in the art without making any inventive step based on the embodiments in the present application belong to the protection scope of the present application.
Referring to fig. 1, fig. 1 is a schematic flow chart illustrating an embodiment of a method for forming a metal bump according to the present application, the method including:
and S11, forming a patterned insulating layer on the front surface of the wafer, wherein a through first opening is arranged at a pad position of the insulating layer corresponding to the front surface of the wafer, the size of the first opening close to the pad position is smaller than that of the first opening far away from the pad position, and the size of the first opening close to the pad position is smaller than that of the pad.
Specifically, referring to fig. 2a, fig. 2a is a schematic structural diagram of an embodiment corresponding to step S11 in fig. 1, a patterned insulating layer 12 is formed on the front surface of the wafer 11, a through first opening a is disposed at a position of the insulating layer 12 corresponding to the pad 111 on the front surface of the wafer 11, a dimension L1 of the first opening a close to the pad 111 is smaller than a dimension L2 of the first opening a far from the pad 111 (i.e., a dimension of a lower end of the first opening a in fig. 2a is smaller than a dimension of an upper end of the first opening a), and a dimension L1 of the first opening a close to the pad 111 is smaller than a dimension L0 of the pad 111. The wafer 11 includes a plurality of chips, a functional surface of each chip is provided with a plurality of pads 111, the functional surface of the chip is a front surface of the wafer 11, i.e. a surface of the wafer 11 facing upward in fig. 2a, and in the case that 3 pads 111 are schematically illustrated in fig. 2a, there are three first openings a. A specific method of forming the first opening a is described below.
And S12, forming a metal bump in the first opening.
Specifically, please refer to fig. 2b in conjunction with fig. 2a, and fig. 2b is a schematic structural diagram of an embodiment corresponding to step S12 in fig. 1. After the insulating layer 12 with the first opening a is formed, a metal bump 13 is formed in the first opening a, and the shape of the metal bump 13 will follow the shape of the first opening a, i.e. the size L1 of the lower end of the metal bump 13 is smaller than the size L2 of the upper end thereof and smaller than the size L0 of the pad 111, and the metal bump 13 can be formed by electroplating. Before the metal bump 13 is formed by electroplating, a sputtered metal layer may be formed by sputtering in the first opening a as a seed layer of the electroplating process.
And S13, removing the insulating layer which is not covered by the orthographic projection of the metal bump on the wafer.
Specifically, please refer to fig. 2c in conjunction with fig. 2a and fig. 2b, and fig. 2c is a schematic structural diagram of an embodiment corresponding to step S13 in fig. 1. After forming the metal bump 13 in the first opening a, the insulating layer 12 not covered by the orthographic projection of the metal bump 13 on the wafer 11 is removed. Since the dimension L1 of the lower end of the metal bump 13 is smaller than the dimension L2 of the upper end thereof, the orthographic projection of the metal bump 13 on the wafer 11 can cover part of the insulating layer 12, in order to better protect the metal bump 13, a mask layer can be formed on the insulating layer 12 and the metal bump 13, a via hole is disposed on the mask layer to expose part of the insulating layer 12, and then the patterned mask layer is used as a mask to remove the insulating layer 12 which is not covered by the orthographic projection of the metal bump 13 on the wafer 11 by a dry etching process.
The dimension L1 of the metal bump 13 formed in the first opening a at the position close to the pad 111 is smaller than the dimension L0 of the pad 111 and smaller than the dimension L2 of the metal bump at the position far from the pad 111 in the present embodiment, which shows that the volume of the metal bump 13 is smaller than the volume of the metal bump with the two ends having the substantially same dimension in the prior art.
Specifically, referring to fig. 3, fig. 3 is a flowchart illustrating an embodiment of the step S11 in fig. 1, and the step S11 may include a step of forming the insulating layer 12 with the first opening a on the front surface of the wafer 11.
And S111, forming a patterned first insulating layer on the front surface of the wafer, wherein at least one first through hole is formed in the position, corresponding to each pad, of the first insulating layer, and the size of each first through hole is smaller than that of each pad.
Specifically, referring to fig. 4, fig. 4 is a schematic structural diagram of an embodiment corresponding to step S111 in fig. 3. A patterned first insulating layer 121, which may be made of polyamide or the like, is formed on the front surface of the wafer 11, and then at least one first via a1 is disposed at a position corresponding to each pad 111 in the first insulating layer 121 by using a photolithography process and an etching process, wherein a dimension L1 of the first via a1 is smaller than a dimension L0 of the pad 111. For example, one first via a1 is formed at each pad 111 alignment position, and may be located at an edge position of the pad 111, or may be located at a center position of the pad 111, for example, two or more first vias a1 are formed, and are located at edge positions of the pad 111, and are symmetrical or asymmetrical with respect to a perpendicular bisector of the pad 111. Fig. 4 schematically shows a case where two first vias a1 symmetrical with respect to the midperpendicular of the pad 111 are provided at each pad 111 counterpoint position.
And S112, forming a patterned second insulating layer on the surface of one side, away from the wafer, of the first insulating layer, wherein a second through hole is formed in the position, corresponding to each pad, of the second insulating layer, the size of each second through hole is larger than that of each first through hole, the second through holes are communicated with the first through holes, and the second through holes and the first through holes form first openings.
Specifically, with reference to fig. 2a, after the patterned first insulating layer 121 is formed on the wafer 11, a patterned second insulating layer 122 is formed on a side surface of the first insulating layer 121 away from the wafer 11, a second via a2 is disposed at a position of the second insulating layer 122 corresponding to each pad 111, a dimension L2 of the second via a2 is greater than a dimension L1 of the first via a1, the second via a2 is connected to the first via a1, and the second via a2 and the first via a1 form a first opening a. The material of the second insulating layer 122 is preferably the same as that of the first insulating layer 121, and the method of forming the second via a2 is similar to that of forming the first via a 1. The second via a2 at the corresponding position of each pad 111 is communicated with one or more first vias a1, forming a first opening a shown in fig. 2a, a size of a lower end of the first opening a, i.e., a size L1 of the first via a1, and a size of an upper end of the first opening a, i.e., a size L2 of the second via a 2. It is preferable that the size L2 of the second via a2 is equivalent to the size L0 of the pad 111 to ensure that the contact area between the metal bumps is not reduced during electrical connection, thereby improving the reliability of the electrical connection of the semiconductor device.
In the embodiment, the first opening A with the lower end size smaller than the upper end size is formed by two times of photoetching and etching processes, so that the using amount of metal in forming the metal bumps can be reduced on the premise of not reducing the contact area between the metal bumps in electric connection, and the cost is saved.
In another embodiment, referring to fig. 5, fig. 5 is a schematic flow chart illustrating another embodiment of a method for forming a metal bump according to the present application, the method including the steps of:
and S21, forming a patterned first insulating layer on the front surface of the wafer, wherein at least one first through hole is arranged at the position, corresponding to each pad, of the first insulating layer, and the size of each first through hole is smaller than that of each pad.
Specifically, referring to fig. 6a, fig. 6a is a schematic structural diagram of an embodiment corresponding to step S21 in fig. 5. A patterned first insulating layer 221 is formed on the front surface of the wafer 21, at least one first through hole B1 is disposed at a position of the first insulating layer 221 corresponding to each pad 211, and the size of the first through hole B1 is smaller than that of the pad 211. Step S21 is the same as step S111 described above, and is not described here again. Fig. 6a schematically shows a situation where one first through hole B1 is provided at an edge position of the pad 211.
And S22, forming a sputtered metal layer on the surface of the first insulating layer far away from the wafer and the first through hole.
Specifically, please refer to fig. 6b, wherein fig. 6b is a schematic structural diagram of an embodiment corresponding to step S22 in fig. 5. After the patterned first insulating layer 221 is formed, the sputtered metal layer 24 is formed on the surface of the first insulating layer 221 away from the wafer 21 and within the first through hole B1 to serve as a seed layer for a subsequent electroplating process for forming a metal bump.
And S23, forming a patterned second insulating layer on the surface of one side of the sputtered metal layer, which is far away from the wafer, wherein a second through hole is formed in the position, corresponding to each pad, of the second insulating layer, the size of each second through hole is larger than that of each first through hole, the second through holes are communicated with the first through holes, and a first opening is formed between each second through hole and each first through hole.
Specifically, please refer to fig. 6c, wherein fig. 6c is a schematic structural diagram of an embodiment corresponding to step S23 in fig. 5. After the formation of the sputtered metal layer 24, a patterned second insulating layer 222 is formed on a surface of the sputtered metal layer 24 away from the wafer 21, a second through hole B2 is formed in a position of the second insulating layer 222 corresponding to each pad 211, the size of the second through hole B2 is larger than that of the first through hole B1, the second through hole B2 is communicated with the first through hole B1, and the first opening B is formed by the second through hole B2 and the first through hole B1. That is, the size of the lower end of the first opening B, that is, the size of the first through hole B1, the size of the upper end of the first opening B, that is, the size of the second through hole B2, and the size of the lower end of the first opening B are smaller than the size of the upper end thereof and also smaller than the size of the pad 211. The second insulating layer 222 is formed in a similar manner to the first insulating layer 221, and the sputtered metal layer 24 is not on the sidewalls of the second via B2.
And S24, forming a metal bump on the sputtered metal layer in the first opening by using an electroplating process, wherein the surface of the metal bump far away from the front surface of the wafer is flush with the surface of the second insulating layer far away from the front surface of the wafer.
Specifically, please refer to fig. 6d in conjunction with fig. 6c, and fig. 6d is a schematic structural diagram of an embodiment corresponding to step S24 in fig. 5. The first opening B is formed by a first through hole B1 and a second through hole B2, wherein the inner wall of the first through hole B1 is provided with a sputtered metal layer 24, the sputtered metal layer 24 can be used as a seed layer to form a metal bump 23 in the first opening B by an electroplating process, and the surface of the metal bump 23 away from the front surface of the wafer 21 is flush with the surface of the second insulating layer 222 away from the front surface of the wafer 21. The shape of the metal bump 23 thus formed follows the shape of the first opening B, and the lower end size is smaller than the upper end size and smaller than the size of the pad 211.
And S25, removing the insulating layer which is not covered by the orthographic projection of the metal bump on the wafer.
Specifically, please refer to fig. 6e in conjunction with fig. 6d, and fig. 6e is a schematic structural diagram of an embodiment corresponding to step S25 in fig. 5. After the metal bump 23 is formed, the insulating layer 22 not covered by the orthogonal projection of the metal bump 23 on the wafer 21 is removed, and the insulating layer 22 includes a first insulating layer 221 and a second insulating layer 222. Because the size of the lower end of the metal bump 23 is smaller than the size of the upper end thereof, the orthographic projection of the metal bump 23 on the wafer 21 can cover part of the insulating layer 22, in order to better protect the metal bump 23, a mask layer can be formed on the insulating layer 22 and the metal bump 23, a via hole is arranged on the mask layer to expose the insulating layer 22 which is not covered by the orthographic projection of the metal bump 23 on the wafer 21, and then the exposed insulating layer 22 is removed by adopting a dry etching process by taking the patterned mask layer as a mask. During the etching process, the second insulating layer 222 is completely removed, a portion of the first insulating layer 221 is removed, and a portion of the sputtered metal layer 24 located between the first insulating layer 221 and the second insulating layer 222 is also removed.
In other embodiments, when the first through holes are multiple and symmetrically distributed about the perpendicular bisector of the pad, the metal bumps may also be directly used as the mask layer, and a wet etching process is used to remove all the insulating layers, and only the metal bumps are remained.
The size of the metal bump 23 formed in the first opening B at the position close to the pad 211 is smaller than the size of the pad 211 and also smaller than the size of the metal bump at the position far from the pad 211, which means that the volume of the metal bump 23 is smaller than the volume of the metal bump with the two ends having basically consistent size in the prior art.
In another embodiment, referring to fig. 7, fig. 7 is a schematic flow chart illustrating another embodiment of a method for forming a metal bump according to the present application, the method including the steps of:
and S31, forming a patterned first insulating layer on the front surface of the wafer, wherein at least one first through hole is arranged at the position, corresponding to each pad, of the first insulating layer, and the size of each first through hole is smaller than that of each pad.
Specifically, referring to fig. 8a, fig. 8a is a schematic structural diagram of an embodiment corresponding to step S31 in fig. 7. A patterned first insulating layer 321 is formed on the front surface of the wafer 31, at least one first via C1 is disposed at a position of the first insulating layer 321 corresponding to each pad 311, and a size of the first via C1 is smaller than a size of the pad 311. Step S31 is the same as step S111 described above, and is not described here again. Fig. 8a schematically shows a situation where one first via C1 is provided at an edge position of the pad 311.
And S32, forming a patterned second insulating layer on the surface of one side, away from the wafer, of the first insulating layer, wherein a second through hole is formed in the position, corresponding to each pad, of the second insulating layer, the size of each second through hole is larger than that of each first through hole, the second through holes are communicated with the first through holes, and the second through holes and the first through holes form first openings.
Specifically, please refer to fig. 8b, wherein fig. 8b is a schematic structural diagram of an embodiment corresponding to step S32 in fig. 7. After the patterned first insulating layer 321 is formed on the wafer 31, a patterned second insulating layer 322 is formed on a surface of the first insulating layer 321 away from the wafer 31, a second through hole C2 is disposed at a position of the second insulating layer 322 corresponding to each pad 311, a size of the second through hole C2 is larger than a size of the first through hole C1, the second through hole C2 is connected to the first through hole C1, and the second through hole C2 and the first through hole C1 form a first opening C. Step S32 is the same as step S112 described above, and is not described here again.
And S33, forming a sputtering metal layer in the first opening.
Specifically, please refer to fig. 8c in conjunction with fig. 8b, and fig. 8c is a schematic structural diagram of an embodiment corresponding to step S33 in fig. 7. After forming the first opening C formed by the first via C1 and the second via C2, the sputtered metal layer 34 is formed within the first opening C as a seed layer for a subsequent electroplating process to form a metal bump. When the sputtered metal layer 34 is formed by sputtering, in addition to the inner wall of the first opening C, the sputtered metal layer 34 is also formed on the surface of the second insulating layer 322 on the side away from the wafer 31, and may be removed by etching.
And S34, forming a metal bump on the sputtered metal layer in the first opening by using an electroplating process, wherein the surface of the metal bump far away from the front surface of the wafer is flush with the surface of the second insulating layer far away from the front surface of the wafer.
Specifically, please refer to fig. 8d in conjunction with fig. 8c, and fig. 8d is a schematic structural diagram of an embodiment corresponding to step S34 in fig. 7. And forming a metal bump 33 in the first opening C by using the sputtered metal layer 34 on the inner wall of the first opening C as a seed layer and using an electroplating process, wherein the surface of the metal bump 33 away from the front surface of the wafer 31 is flush with the surface of the second insulating layer 322 away from the front surface of the wafer 31. The shape of the metal bump 33 thus formed follows the shape of the first opening C, and the lower end size is smaller than the upper end size and smaller than the size of the pad 311.
And S35, removing the insulating layer which is not covered by the orthographic projection of the metal bump on the wafer.
Specifically, please refer to fig. 8e in conjunction with fig. 8a to 8d, and fig. 8e is a schematic structural diagram of an embodiment corresponding to step S35 in fig. 7. After the metal bump 33 is formed, the insulating layer 32 not covered by the orthogonal projection of the metal bump 33 on the wafer 31 is removed, and the insulating layer 32 includes a first insulating layer 321 and a second insulating layer 322. Since the size of the lower end of the metal bump 33 is smaller than the size of the upper end thereof, the orthographic projection of the metal bump 33 on the wafer 31 can cover a part of the insulating layer 32, in order to better protect the metal bump 33, a mask layer can be formed on the insulating layer 32 and the metal bump 33, a via hole is formed on the mask layer to expose the insulating layer 32 which is not covered by the orthographic projection of the metal bump 33 on the wafer 31, and then the exposed insulating layer 32 is removed by using the patterned mask layer as a mask and adopting a dry etching process, so as to obtain the structure shown in fig. 8 e. During the etching process, the second insulating layer 322 is completely removed, a portion of the first insulating layer 321 is removed, and the sputtered metal layer 34 on the surface of the second insulating layer 322 and the sputtered metal layer 34 on the sidewall of the second via C2 are also removed.
The size of the metal bump 33 formed in the first opening C at the position close to the pad 311 is smaller than the size of the pad 311 and is also smaller than the size of the pad 311, and it can be seen that the volume of the metal bump 33 is smaller than the volume of the metal bump with the two ends having the same size in the prior art.
In another embodiment, referring to fig. 9, fig. 9 is a schematic flow chart of another embodiment of a method for forming a metal bump according to the present application, including the steps of:
and S41, forming a patterned passivation layer on the front surface of the wafer, wherein a through second opening is formed in the passivation layer at a position corresponding to the pad, and the size of the second opening is smaller than or equal to that of the pad.
Specifically, referring to fig. 10a, fig. 10a is a schematic structural diagram of an embodiment corresponding to step S41 in fig. 9. And forming a patterned passivation layer 45 on the front surface of the wafer 41, wherein the passivation layer 45 is provided with a through second opening E at a position corresponding to the pad 411, and the size of the second opening E is smaller than or equal to that of the pad 411. Fig. 10a schematically shows the case where the size of the passivation layer 45 is smaller than the size of the pad 411. Specifically, a passivation layer 45 may be deposited on the front surface of the wafer 41, and the material of the passivation layer may be silicon oxide, silicon nitride, or the like, and then a second opening E is formed at a position of the passivation layer 45 corresponding to the pad 411 by using a photolithography process and an etching process. The passivation layer can protect the front surface of the wafer, and the reliability of the semiconductor device is improved.
And S42, forming an under bump metal layer on the surface of the passivation layer far away from the wafer and in the second opening.
Specifically, please refer to fig. 10b in conjunction with fig. 10a, and fig. 10b is a schematic structural diagram of an embodiment corresponding to step S42 in fig. 9. After the patterned passivation layer 45 is formed, an under bump metallurgy layer 46, which may be titanium-tungsten alloy and may be formed by a sputtering process, is formed in the surface of the passivation layer 45 on the side away from the wafer 41 and in the first opening E. The under bump metallurgy 46 can form an electrical path between the pad 411 and the metal bump, and can increase the adhesion between the metal bump and the pad 411, so that the metal bump is not easy to fall off.
And S43, forming a patterned first insulating layer on the front surface of the wafer, wherein at least one first through hole is arranged at the position, corresponding to each pad, of the first insulating layer, and the size of each first through hole is smaller than that of each pad.
Specifically, please refer to fig. 10c in conjunction with fig. 10b, and fig. 10c is a schematic structural diagram of an embodiment corresponding to step S43 in fig. 9. After the passivation layer 45 and the under bump metal layer 46 are formed on the front surface of the wafer 41, a patterned first insulating layer 421 is formed on a surface of the under bump metal layer 46 away from the wafer 41, at least one first via D1 is disposed on the first insulating layer 421 corresponding to each pad 411, and the size of the first via D1 is smaller than that of the pad 411. Fig. 10c schematically shows a case where two first through holes D1 are provided at each pad 411 position, and the first through holes D1 are symmetrically distributed about the perpendicular bisector of the pad 411. Step S43 is similar to the method for forming the first insulating layer in the above embodiments, and is not repeated here.
And S44, forming a patterned second insulating layer on the surface of one side, away from the wafer, of the first insulating layer, wherein a second through hole is formed in the position, corresponding to each pad, of the second insulating layer, the size of each second through hole is larger than that of each first through hole, the second through holes are communicated with the first through holes, and the second through holes and the first through holes form first openings.
Specifically, please refer to fig. 10d in conjunction with fig. 10c, and fig. 10d is a schematic structural diagram of an embodiment corresponding to step S44 in fig. 9. After the first insulating layer 421 with the first through hole D1 is formed, a patterned second insulating layer 422 is formed on a surface of the first insulating layer 421 on a side away from the wafer 41, a second through hole D2 is disposed on the second insulating layer 422 corresponding to each pad 411, a size of the second through hole D2 is larger than a size of the first through hole D1, the second through hole D2 is communicated with the first through hole D1, and the second through hole D2 and the first through hole D1 form a first opening D. Step S44 is similar to the method for forming the second insulating layer in the above embodiments, and is not repeated here.
Among them, it is preferable that the size of the second opening E provided on the passivation layer 45 is smaller than or equal to the size of the second via hole D2, and fig. 10D schematically illustrates a case where the size of the second opening E is smaller than the size of the second via hole D2. And/or at least one sidewall of the first via D1 is aligned with the ubm layer 46 at the position of the sidewall of the second opening E, and each of the two first vias D1 in fig. 10D has a sidewall aligned with the ubm layer 46 at the position of the sidewall of the second opening E.
And S45, forming a metal bump in the first opening, wherein the surface of the metal bump far away from the front surface of the wafer is flush with the surface of the second insulating layer far away from the front surface of the wafer.
Specifically, please refer to fig. 10e in conjunction with fig. 10d, and fig. 10e is a schematic structural diagram of an embodiment corresponding to step S45 in fig. 9. A metal bump 43 is formed in the first opening D by an electroplating process, and a surface of the metal bump 43 away from the front surface of the wafer 41 is flush with a surface of the second insulating layer 422 away from the front surface of the wafer 41. The shape of the metal bump 43 thus formed follows the shape of the first opening D, and the lower end size is smaller than the upper end size and smaller than the size of the pad 411. Before forming the second insulating layer 422, the sputtered metal layer 44 may be formed in the first via hole D1 as a seed layer of an electroplating process for forming the metal bump 43, and the specific forming manner is similar to the method for forming the metal bump in the foregoing embodiments, and is not described herein again.
And S46, removing the insulating layer which is not covered by the orthographic projection of the metal bump on the wafer.
Specifically, please refer to fig. 10f in conjunction with fig. 10e, and fig. 10f is a schematic structural diagram of an embodiment corresponding to step S46 in fig. 9. After the metal bump 43 is formed, the insulating layer 42 not covered by the orthogonal projection of the metal bump 43 on the wafer 41 is removed, and the insulating layer 42 includes a first insulating layer 421 and a second insulating layer 422. Since the size of the lower end of the metal bump 43 is smaller than the size of the upper end thereof, the orthographic projection of the metal bump 43 on the wafer 41 can cover part of the insulating layer 42, in order to better protect the metal bump 43, a mask layer can be formed on the insulating layer 42 and the metal bump 43, a via hole is arranged on the mask layer to expose the insulating layer 42 which is not covered by the orthographic projection of the metal bump 43 on the wafer 41, and then the exposed insulating layer 42 is removed by using the patterned mask layer as a mask and adopting a dry etching process, so as to obtain the structure shown in fig. 10 f. During the etching process, the second insulating layer 422 is completely removed, a portion of the first insulating layer 421 is removed, and a portion of the sputtered metal layer 44 located between the first insulating layer 421 and the second insulating layer 422 is also removed.
In other embodiments, when the first through holes are symmetrically distributed about the perpendicular bisector of the pad, the metal bump may be directly used as a mask, and a wet etching process is used to remove all the insulating layer, so that only the metal bump remains. Referring to fig. 10g in conjunction with fig. 10f, fig. 10g is a schematic structural diagram of another embodiment corresponding to step S46 in fig. 9. When the first through holes are multiple and are symmetrically distributed about the perpendicular bisector of the bonding pad 411 'on the chip 41', the metal bump 43 'may also be directly used as a mask layer, and a wet etching process is used to remove all the insulating layers, so that only the metal bump 43' remains, and the structure shown in fig. 10g is obtained.
And S47, etching to remove the under bump metal layer which is not covered by the orthographic projection of the metal bump on the wafer.
Specifically, please refer to fig. 11 in conjunction with fig. 10f, and fig. 11 is a schematic structural diagram of an embodiment corresponding to step S47 in fig. 9. After removing part of the insulating layer 42, the mask layer disposed above the metal bump 43 may be used as a mask to remove the under bump metallurgy layer 46 that is not covered by the orthographic projection of the metal bump 43 on the wafer 41 by using a dry etching process, so as to obtain the semiconductor device shown in fig. 11, i.e., the semiconductor device formed by using the method for forming a metal bump provided in the present application.
The size of the metal bump 43 formed in the first opening D at the position close to the pad 411 is smaller than the size of the pad 411 and also smaller than the size of the metal bump at the position far from the pad 411, which means that the volume of the metal bump 43 is smaller than the volume of the metal bump with the two ends having basically the same size in the prior art.
Referring to fig. 11 with continued reference to fig. 10a to 10f, the present application further provides a semiconductor device including a metal bump formed by the method described in the above embodiments, and fig. 11 is a schematic structural diagram of an embodiment of the semiconductor device of the present application, where the semiconductor device specifically includes: wafer 41, a plurality of metal bumps 43, and patterned first insulating layer 421. Wherein the front side of the wafer 41 is provided with a plurality of pads 411; the metal bump 43 is correspondingly arranged at each pad 411, the size of one end of the metal bump 43 close to the pad 411 is smaller than that of one end of the metal bump far away from the pad 411, and the size of one end of the metal bump 43 close to the pad 411 is also smaller than that of the pad 411; the first insulating layer 421 is located on the periphery of one end of the metal bump 43 close to the pad 411, and the first insulating layer 421 is only distributed in the area covered by the orthographic projection of the metal bump 43 on the wafer 41.
Specifically, the metal bump 43 includes at least one first metal pillar 431 and one second metal pillar 432. Wherein a first insulating layer 421 is disposed around the first metal pillar 431, and one end of the first insulating layer is electrically connected to the pad 411 at the corresponding position; one end of the second metal pillar 432 is electrically connected to the other end of the at least one first metal pillar 431 at the corresponding position. Fig. 11 schematically illustrates a case where the metal bump 43 includes two first metal pillars 431 and one second metal pillar 432, where the downward ends of the two first metal pillars 431 are electrically connected to the pad 411, and the upward ends are electrically connected to the second metal pillar 432.
In this embodiment, the size of the lower end of the metal bump 43 is smaller than the size of the upper end and smaller than the size of the pad 411, and the first insulating layer 421 is further distributed in the area covered by the orthographic projection of the metal bump 43 on the wafer 41, which is equivalent to the first insulating layer 421 distributed in the volume space where the second metal pillar 432 is more than the first metal pillar 431, that is, the first insulating layer 421 is used to replace part of the volume of the metal bump 43, so as to reduce the usage amount of metal without reducing the connection area of the metal bump, save the cost, and not affect the reliability of the electrical connection.
Preferably, in the semiconductor device provided by the present application, in a direction parallel to the front surface of the wafer, the sum of the cross-sectional dimensions of all the first metal pillars corresponding to each pad is smaller than the cross-sectional dimension of the second metal pillar, and the cross-sectional dimension of each first metal pillar is smaller than 1/2 of the cross-sectional dimension of the second metal pillar. With reference to fig. 11, in the present embodiment, two first metal pillars 431 are provided, the sum of the cross-sectional dimensions of the two first metal pillars 431 is smaller than the cross-sectional dimension of the second metal pillar 432, and the cross-sectional dimension of each of the two first metal pillars 431 is smaller than 1/2 of the cross-sectional dimension of the second metal pillar 432. With such an arrangement, the first insulating layer 421 can be disposed in the volume space where the second metal pillar 432 is more than the first metal pillar 431, so that the structural stability of the semiconductor device of the present application is increased and the amount of metal used is reduced.
Further, in the semiconductor device provided by the present application, when the metal bump includes a plurality of first metal pillars, the plurality of first metal pillars are symmetrically disposed about a central axis of the second metal pillar. Referring to fig. 11, in the present embodiment, two first metal posts 431 are disposed, and the two first metal posts 431 are disposed symmetrically with respect to a central axis of a second metal post 432. The arrangement can further increase the structural stability of the semiconductor device, and the first insulating layer 421 can be removed in some application scenarios to improve the heat dissipation performance of the semiconductor device.
Further, referring to fig. 11 with continuing reference to fig. 10a to fig. 10f, the semiconductor device of the present embodiment further includes: a patterned passivation layer 45 and a patterned under bump metallization layer 46. The passivation layer 45 covers the front surface of the wafer 41, and a through second opening E is disposed at a position corresponding to the pad 411, where the size of the second opening E is smaller than or equal to the size of the pad 411; the under bump metallurgy 46 is disposed in the second opening E and electrically connected to the bonding pad 411 at the corresponding position, and the under bump metallurgy 46 is only distributed in the area covered by the orthographic projection of the metal bump 43 on the wafer 41. The passivation layer 45 can protect the front surface of the wafer 41, and the reliability of the semiconductor device of the present application is improved. The under bump metallurgy 46 can improve the adhesion between the metal bump 43 and the pad 411, and improve the structural stability of the semiconductor device of the present application.
In addition, the semiconductor device in this embodiment mode further includes a sputtered metal layer 44. The first insulating layer 421 is disposed around the first metal pillars 431, which corresponds to a plurality of first vias D1 formed on the first insulating layer 421, and one first metal pillar 431 is distributed in one first via D1. The sputtered metal layer 44 is disposed on a side surface of the first insulating layer 421 away from the pad 411 and in the first through hole D1, and serves as a seed layer for forming the metal bump 43 by electroplating. Wherein the metal bump 43, the sputtered metal layer 44, the under bump metal layer 46 and the pad 411 are electrically connected.
In the semiconductor device including the metal bump 43 provided in this embodiment, the size of the metal bump 43 near the pad 411 is smaller than the size of the pad 411 and is also smaller than the size of the metal bump far from the pad 411, and it can be seen that the volume of the metal bump 43 is smaller than the volume of the metal bump with the two ends having substantially the same size in the prior art, so that the usage amount of metal is reduced on the premise of not reducing the electrical connection contact area of the metal bump, and the cost is saved on the premise of not affecting the reliability of the semiconductor device.
The above description is only for the purpose of illustrating embodiments of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings of the present application or are directly or indirectly applied to other related technical fields, are also included in the scope of the present application.
Claims (10)
1. A method for forming a metal bump, comprising:
forming a patterned insulating layer on the front surface of a wafer, wherein a through first opening is arranged at a pad position of the insulating layer corresponding to the front surface of the wafer, the size of the first opening close to the pad position is smaller than that of the first opening far away from the pad position, and the size of the first opening close to the pad position is smaller than that of the pad;
forming a metal bump in the first opening;
and removing the insulating layer which is not covered by the orthographic projection of the metal bump on the wafer.
2. The method of claim 1, wherein the step of forming a patterned insulating layer on the front surface of the wafer, the insulating layer being provided with a first through opening at a pad position corresponding to the front surface of the wafer, the size of the first through opening near the pad position being smaller than that of the first through opening far from the pad position, and the size of the first through opening near the pad position being smaller than that of the pad position comprises:
forming a patterned first insulating layer on the front surface of the wafer, wherein at least one first through hole is formed in the position, corresponding to each bonding pad, of the first insulating layer, and the size of each first through hole is smaller than that of each bonding pad;
and forming a patterned second insulating layer on the surface of one side, far away from the wafer, of the first insulating layer, wherein a second through hole is formed in the position, corresponding to each bonding pad, of the second insulating layer, the size of each second through hole is larger than that of each first through hole, the second through holes are communicated with the first through holes, and the second through holes and the first through holes form the first openings.
3. The method of claim 2,
the method comprises the following steps of forming a patterned second insulating layer on the surface of one side, far away from the wafer, of the first insulating layer: forming a sputtering metal layer in the surface of one side of the first insulating layer, which is far away from the wafer, and the first through hole;
the step of forming a metal bump in the first opening includes: and forming a metal bump on the sputtering metal layer in the first opening by utilizing an electroplating process, wherein the surface of the metal bump, which is far away from the front surface of the wafer, is flush with the surface of the second insulating layer, which is far away from the front surface of the wafer.
4. The method of claim 2,
after the step of forming the patterned second insulating layer on the surface of the first insulating layer on the side far away from the wafer, the method comprises the following steps: forming a sputtered metal layer in the first opening;
the step of forming a metal bump in the first opening includes: and forming a metal bump on the sputtering metal layer in the first opening by utilizing an electroplating process, wherein the surface of the metal bump, which is far away from the front surface of the wafer, is flush with the surface of the second insulating layer, which is far away from the front surface of the wafer.
5. The method of claim 2,
before the step of forming the patterned insulating layer on the front surface of the wafer, the method further comprises the following steps:
forming a patterned passivation layer on the front surface of the wafer, wherein a through second opening is formed in the passivation layer at a position corresponding to the pad, and the size of the second opening is smaller than or equal to that of the pad;
forming an under bump metal layer on the surface of one side, away from the wafer, of the passivation layer and in the second opening;
after the step of removing the insulating layer not covered by the orthographic projection of the metal bump on the wafer, the method further comprises the following steps:
and etching to remove the under bump metal layer which is not covered by the orthographic projection of the metal bump on the wafer.
6. The method of claim 5,
the size of the second opening is smaller than or equal to that of the second through hole; and/or the presence of a gas in the gas,
at least one sidewall of the first via is aligned with the under bump metallurgy at a sidewall location of the second opening.
7. A semiconductor device, comprising:
the front surface of the wafer is provided with a plurality of bonding pads;
the metal bumps are correspondingly arranged at the positions of the bonding pads, the size of one end, close to the bonding pads, of each metal bump is smaller than that of one end, far away from the bonding pads, of each metal bump, and the size of one end, close to the bonding pads, of each metal bump is smaller than that of the bonding pads;
the patterned first insulating layer is positioned on the periphery of one end, close to the bonding pad, of the metal bump, and the first insulating layer is only distributed in an area covered by the orthographic projection of the metal bump on the wafer.
8. The semiconductor device of claim 7, wherein the metal bump comprises:
at least one first metal column, around which the first insulating layer is disposed, one end of which is electrically connected to the pad at a corresponding position;
one end of the second metal column is electrically connected with the other end of the at least one first metal column at the corresponding position;
in a direction parallel to the front surface of the wafer, the sum of the cross-sectional dimensions of all the first metal columns corresponding to each pad is smaller than the cross-sectional dimension of the second metal column, and the cross-sectional dimension of each first metal column is smaller than 1/2 of the cross-sectional dimension of the second metal column.
9. The semiconductor device according to claim 8,
the metal bump comprises a plurality of first metal columns, and the plurality of first metal columns are symmetrically arranged around a central axis of the second metal column.
10. The semiconductor device according to claim 8, further comprising:
the passivation layer covers the front surface of the wafer, a through second opening is arranged at a position corresponding to the pad, and the size of the second opening is smaller than or equal to that of the pad;
and the patterned under bump metal layer is arranged in the second opening and is electrically connected with the bonding pad at the corresponding position, and the under bump metal layer is only distributed in an area covered by the orthographic projection of the metal bump on the wafer.
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Application publication date: 20200908 |