CN111263166B

CN111263166B - Video image prediction method and device

Info

Publication number: CN111263166B
Application number: CN201811559686.2A
Authority: CN
Inventors: 魏紫威; 张娜; 余全合; 郑建铧; 何芸
Original assignee: Tsinghua University; Huawei Technologies Co Ltd
Current assignee: Tsinghua University; Huawei Technologies Co Ltd
Priority date: 2018-11-30
Filing date: 2018-12-19
Publication date: 2022-10-11
Anticipated expiration: 2038-12-19
Also published as: CN111263166A

Abstract

The application provides a video image prediction method and a video image prediction device, which are used for solving the problem of low prediction precision in the prior art. The method comprises the following steps: analyzing candidate motion information and an index identifier from the code stream, wherein the candidate motion information comprises a reference frame index and a candidate motion vector identifier of a block to be processed; when the index mark is a first value, determining a derived reference frame index according to the reference frame index; based on the distance between the reference frame and the current frame and the distance between the derived reference frame and the current frame, scaling the motion vector of the decoded block to obtain a derived motion vector of the candidate motion information; a pixel predictor for the block to be processed is determined based on the candidate motion information, the derived reference frame index, and the derived motion vector. Due to the fact that part of optimal motion information of the HMVP queue is lost due to motion information updating, the derived motion information can make up for the prediction accuracy loss caused by the motion information, and therefore prediction accuracy can be improved.

Description

Video image prediction method and device

The present application claims priority of chinese patent application with application number 201811452886.8 entitled "inter-frame prediction method and apparatus" filed in 2018, 11/30/2018, which is incorporated herein by reference in its entirety.

Technical Field

The present application relates to the field of image encoding and decoding technologies, and in particular, to an image prediction method and apparatus.

Background

With the development of information technology, video services such as high-definition televisions, web conferences, IPTV,3D televisions and the like are rapidly developed, and video signals become the most important way for people to acquire information in daily life with the advantages of intuitiveness, high efficiency and the like. Since the video signal contains a large amount of data, a large amount of transmission bandwidth and storage space are required. In order to effectively transmit and store video signals, the video signals need to be compressed and coded, and the video compression technology is becoming an indispensable key technology in the field of video application.

The basic principle of video coding compression is to remove redundancy as much as possible by using correlations between spatial domain, temporal domain and codewords. The current popular practice is to adopt a hybrid video coding framework according to image blocks, and implement video coding compression through the steps of prediction (including intra-frame prediction and inter-frame prediction), transformation, quantization, entropy coding and the like.

Currently, a history-based motion vector prediction (HMVP) mode is proposed by a video coding standard. The HMVP approach employs an HMVP queue for adding candidate motion information. When candidate motion information is added into an HMVP queue, if the number of the candidate motion information in the HMVP queue reaches or exceeds the maximum length of the HMVP queue, the first candidate motion information existing in the queue is removed by adopting a First In and First Out (FIFO) principle, and the candidate motion information to be added is stored at the tail of the HMVP queue.

For a P frame, only motion information of an encoded block of a forward reference frame can be referred to, and when candidate motion information is removed from the HMVP queue, motion information that can be adopted for the P frame may be removed, which results in less motion information that can be referred to when inter-frame prediction is performed on a block to be processed of the P frame, and thus results in lower prediction accuracy.

Disclosure of Invention

The application provides a video image prediction method and a video image prediction device, which are used for solving the problem of low prediction precision in the prior art.

In a first aspect, an embodiment of the present application provides a video image prediction method, including: analyzing candidate motion information and an index identifier from a code stream, wherein the candidate motion information comprises a reference frame index of a block to be processed and a candidate motion vector identifier, and the motion vector identifier is used for indicating a motion vector of a decoded block referred by the block to be processed; when the index mark is a first value, determining a derived reference frame index according to the reference frame index; based on the distance between the reference frame indicated by the reference frame index and the current frame where the block to be processed is located and the distance between the derived reference frame indicated by the derived reference frame index and the current frame, performing scaling processing on the motion vector of the decoded block to obtain a derived motion vector of the candidate motion information; determining a pixel predictor of the block to be processed based on the candidate motion information, the derived reference frame index, and the derived motion vector.

In the method, the newly generated derived motion information is included in addition to the selection of the candidate motion information included in the HMVP queue, so that the prediction accuracy of the pixel value of the coding unit can be further improved. According to the characteristics of the candidate motion information in the HMVP queue, any optimal motion information around the coding unit can be used for generating new motion information. Due to the fact that part of optimal motion information of the HMVP queue is lost due to motion information updating, the derived motion information can make up for the loss of prediction accuracy caused by the motion information, and therefore prediction accuracy can be improved.

In one possible design, the pixel predictor of the block to be processed is equal to a sum of a first weight and a second weight, the first weight being equal to a pixel predictor of the block to be processed determined based only on the candidate motion information multiplied by a first weight, the second weight being equal to a pixel predictor of the block to be processed determined based on the derived motion vector and the derived reference frame index multiplied by a second weight, a sum of the first weight and the second weight being equal to 1.

According to the design, the pixel prediction value of the block to be processed corresponding to the derived motion information is determined by adopting a weighted summation method, so that the prediction precision can be further improved, and the method is simple and easy to implement.

In one possible design, the first weight is equal to the second weight.

In one possible design, the method further includes, when the index is identified as the second value, determining a pixel prediction value of the image to be processed based only on the candidate motion information.

The design is simple to realize by determining whether to perform derivation through different index identifications.

In one possible design, the derived motion vector is obtained according to the following equation:

MV′＝(d0′/d0)MV；

wherein MV 'represents the derived motion vector, d0' represents the distance between the derived reference frame and the current frame, d0 represents the distance between the reference frame and the current frame, MV represents the motion vector of the decoded block.

In one possible design, determining a derived reference frame index from the reference frame indices includes:

when the reference frame index is zero, determining that the derived reference frame index is 1;

determining the derived reference frame index to be 0 when the reference frame index is non-zero.

The above design provides a simple and easy way to determine the derived reference frame index.

In a second aspect, the present application provides a method for decoding a motion vector, including:

analyzing the code stream to obtain first identification information, wherein the first identification information is used for identifying a first motion vector in a motion vector set corresponding to the image block to be processed; analyzing the code stream to obtain second identification information; when the second identification information is a second numerical value, obtaining a predicted value of the image block to be processed according to the first motion vector; and when the second identification information is a first numerical value, obtaining a predicted value of the image block to be processed according to the first motion vector and a second motion vector, wherein the second motion vector is obtained according to the first motion vector and a preset mapping relation, and the first numerical value is different from the second numerical value.

With reference to the second aspect, in a first possible implementation manner of the second aspect, before the parsing the code stream to obtain the second identification information, the method further includes:

determining the type of the strip of the image where the image block to be processed is located; and/or the presence of a gas in the gas,

determining a coding structure of a sequence in which the image block to be processed is located; and/or the presence of a gas in the gas,

determining a prediction mode of the image block to be processed;

correspondingly, the analyzing the code stream to obtain second identification information includes:

and when the strip type of the image where the image block to be processed is located, and/or the coding structure of the sequence where the image block to be processed is located, and/or the prediction mode of the image block to be processed meets a preset condition, analyzing the code stream to obtain the second identification information.

With reference to the first possible implementation manner of the second aspect, in a second possible implementation manner of the second aspect, the preset condition includes: the prediction mode is a skip mode or a direct mode, and/or the slice type is a P slice, and/or the coding structure is a Low latency P frame (Low Delay P) structure.

With reference to the second aspect or the first possible implementation manner or the second possible implementation manner of the second aspect, in a third possible implementation manner of the second aspect, the second motion vector is obtained by the following formula:

the motion vector of the image frame to be processed is a first motion vector, the motion vector of the image frame to be processed is a second motion vector, the MV1 is a first motion vector, the MV2 is a second motion vector, the d1 is a time-domain distance between a first reference frame corresponding to the first motion vector and the image frame where the image block to be processed is located, and the d2 is a time-domain distance between a second reference frame corresponding to the second motion vector and the image frame where the image block to be processed is located.

With reference to the third possible implementation manner of the second aspect, in a fourth possible implementation manner of the second aspect, the first identification information is further used to identify the first reference frame.

With reference to the third or fourth possible implementation manner of the second aspect, in a fifth possible implementation manner of the second aspect, the method further includes: and obtaining the index value of the second reference frame according to the index value of the first reference frame.

With reference to the fifth possible implementation manner of the second aspect, in a sixth possible implementation manner of the second aspect, the obtaining an index value of the second reference frame according to an index value of the first reference frame includes:

when the index value of the first reference frame is 0, the index value of the second reference frame is 1;

when the index value of the first reference frame is not 0, the index value of the second reference frame is 0.

With reference to the second aspect and any implementation manner of the first to sixth possible implementation manners of the second aspect, in a seventh possible implementation manner of the second aspect, the obtaining a prediction value of the image block to be processed according to the first motion vector and the second motion vector includes:

obtaining a first predicted value of the image block to be processed according to the first motion vector and the first reference frame;

obtaining a second predicted value of the image block to be processed according to the second motion vector and the second reference frame;

and calculating the average value of the first predicted value and the second predicted value to be used as the predicted value of the image block to be processed.

With reference to any implementation manner of the first to seventh possible implementation manners of the second aspect, in an eighth possible implementation manner of the second aspect, when a slice type of an image in which the to-be-processed image block is located, and/or a coding structure of a sequence in which the to-be-processed image block is located, and/or a prediction mode of the to-be-processed image block does not satisfy the preset condition, a prediction value of the to-be-processed image block is obtained according to the first motion vector.

In a third aspect, an embodiment of the present application provides a video image prediction method, which is applied to an encoding side and includes:

acquiring first candidate motion information from a historical motion vector prediction queue corresponding to a block to be processed, wherein the first candidate motion information comprises a prediction direction of a candidate coded block, a reference frame index of the block to be processed and a motion vector of the candidate coded block; when the prediction direction is forward and the number of reference frames in a reference frame list corresponding to the block to be processed is greater than 1, determining a derived reference frame index according to the reference frame index; scaling a motion vector included in the first candidate motion information to obtain a derived motion vector of the first candidate motion information based on a distance between a reference frame indicated by the reference frame index and a current frame where the block to be processed is located and a distance between a derived reference frame indicated by the derived reference frame index and the current frame; and determining a pixel prediction value of the block to be processed corresponding to the first candidate motion information based on the first candidate motion information, the derived reference frame index and the derived motion vector.

In one possible design, a pixel prediction value of the block to be processed corresponding to the first candidate motion information is equal to a minimum Sum of Absolute Transformed Differences (SATD) prediction value of the first prediction value and the second prediction value;

wherein the first predictor is equal to a pixel predictor of the block to be processed determined based only on the first candidate motion information, the second predictor is equal to a sum of the first weight and a second weight, the first weight is equal to the first predictor multiplied by a first weight, the second weight is equal to the pixel predictor of the block to be processed determined based on the derived motion vector and the derived reference frame index multiplied by a second weight, and the sum of the first weight and the second weight is equal to 1.

In one possible design, the first weight is equal to the second weight.

In one possible design, further comprising:

and when the prediction direction is backward or bidirectional, taking a pixel predicted value of the image to be processed determined only based on the first candidate motion information as the pixel predicted value of the block to be processed corresponding to the first candidate motion information.

In one possible design, the historical motion vector prediction queue includes N candidate motion information including the first candidate motion information, where N is an integer greater than or equal to 1, and the method further includes:

selecting a pixel predicted value with the minimum rate distortion cost from pixel predicted values respectively corresponding to the N candidate motion information;

encoding second candidate motion information and index identification corresponding to the pixel predicted value with the minimum rate distortion cost into a code stream;

wherein the index flag is a first value when the pixel predictor corresponding to the second candidate motion information is determined based on the second candidate motion information and a derived motion vector of the second candidate motion information;

when the pixel prediction value corresponding to the second candidate motion information is determined based on only the second candidate motion information, the index is identified as a second value.

In one possible design, the derived motion vector of the first candidate motion information satisfies the following condition:

MV′＝(d0′/d0)MV；

wherein MV 'represents a derived motion vector of the first candidate motion information, d0' represents a distance between the derived reference frame and the current frame, d0 represents a distance between the reference frame and the current frame, and MV represents a motion vector of the candidate coded block.

when the reference frame index is zero, the derived reference frame index is 1;

when the reference frame index is non-zero, the derived reference frame index is 0.

In a fourth aspect, an embodiment of the present application further provides a video image prediction apparatus, including:

the entropy decoding unit is used for analyzing candidate motion information and an index identifier from a code stream, wherein the candidate motion information comprises a reference frame index and a candidate motion vector identifier of a block to be processed, and the motion vector identifier is used for indicating a motion vector of a decoded block referred by the block to be processed;

an inter-frame prediction unit, configured to determine a derived reference frame index according to the reference frame index when the index identifier is a first value; based on the distance between the reference frame indicated by the reference frame index and the current frame where the block to be processed is located and the distance between the derived reference frame indicated by the derived reference frame index and the current frame, scaling the motion vector of the decoded block to obtain a derived motion vector of the candidate motion information; determining a pixel predictor of the block to be processed based on the candidate motion information, the derived reference frame index, and the derived motion vector.

In one possible design, the first weight is equal to the second weight.

In one possible design, the inter-prediction unit is further configured to:

when the index identifier is a second value, determining a pixel prediction value of the image to be processed based on the candidate motion information only.

MV′＝(d0′/d0)MV；

In one possible design, when determining the derived reference frame index from the reference frame index, the inter-prediction unit is specifically configured to:

when the reference frame index is zero, determining that the derived reference frame index is 1; or,

when the reference frame index is non-zero, determining the derived reference frame index to be 0.

In a fifth aspect, an embodiment of the present application provides an image prediction apparatus, including: a processor and a memory coupled to the processor; the processor is configured to perform the methods of the various designs of the first or second aspects.

In a sixth aspect, an embodiment of the present application provides an image prediction apparatus, which includes a processor and a memory coupled to the processor; the processor is configured to perform the method in various designs of the third aspect.

In a seventh aspect, an embodiment of the present application provides a video decoding apparatus, including a non-volatile storage medium and a processor, where the non-volatile storage medium stores an executable program, and the processor is mutually coupled with the non-volatile storage medium and executes the executable program to implement the method in the first aspect or the second aspect or various implementations thereof.

In an eighth aspect, an embodiment of the present application provides a video encoding apparatus, which includes a non-volatile storage medium and a processor, where the non-volatile storage medium stores an executable program, and the processor is mutually coupled with the non-volatile storage medium and executes the executable program to implement the method in the third aspect or various implementations thereof.

In a ninth aspect, embodiments of the present application provide a computer-readable storage medium, which stores instructions that, when executed on a computer, cause the computer to perform the method of the first aspect or its various implementations, or perform the method of the second aspect or its various implementations, or perform the method of the third aspect or its various implementations.

In a tenth aspect, embodiments of the present application provide a computer program product containing instructions, which when run on a computer, cause the computer to perform the method of the first aspect or its various implementations, or perform the method of the second aspect or its various implementations, or perform the method of the third aspect or its various implementations.

It should be understood that the second to tenth aspects of the present application are the same as or similar to the first technical solution of the present application, and the beneficial effects obtained by the aspects and the corresponding implementable design manners are similar, and are not repeated.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments or the background art of the present application, the drawings required to be used in the embodiments or the background art of the present application will be described below.

FIG. 1A is a block diagram of an example of a video encoding and decoding system 10 for implementing embodiments of the present application;

FIG. 1B is a block diagram of an example of a video coding system 40 for implementing embodiments of the present application;

FIG. 2 is a block diagram of an example structure of an encoder 20 for implementing embodiments of the present application;

FIG. 3 is a block diagram of an example structure of a decoder 30 for implementing embodiments of the present application;

FIG. 4 is a block diagram of an example of a video coding apparatus 400 for implementing embodiments of the present application;

FIG. 5 is a block diagram of another example of an encoding device or a decoding device for implementing embodiments of the present application;

fig. 6 is an exemplary diagram of a motion vector and a reference frame index for implementing an embodiment of the present application.

Fig. 7 is a schematic diagram of an HMVP queue update manner for implementing an embodiment of the present application;

fig. 8 is another schematic diagram of an HMVP queue update method for implementing an embodiment of the present application;

fig. 9 is another schematic diagram of an HMVP queue update manner for implementing an embodiment of the present application;

FIG. 10 is a flow chart of a video image prediction method for implementing an embodiment of the present application;

FIG. 11 is an exemplary diagram of a derived motion vector generation for implementing one of the embodiments of the present application;

FIG. 12 is a flow chart illustrating another video image prediction method for implementing embodiments of the present application;

FIG. 13 is a schematic diagram of an apparatus 1300 for implementing embodiments of the present application;

FIG. 14 is a schematic diagram of an apparatus 1400 for implementing embodiments of the present application;

fig. 15 is a schematic diagram of an apparatus 1500 for implementing embodiments of the present application.

Detailed Description

The embodiments of the present application will be described below with reference to the drawings. In the following description, reference is made to the accompanying drawings which form a part hereof and which show by way of illustration specific aspects of embodiments of the application or which may be used in the practice of the application. It should be understood that embodiments of the present application may be used in other ways and may involve structural or logical changes not depicted in the drawings. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present application is defined by the appended claims. For example, it should be understood that the disclosure in connection with the described methods may equally apply to the corresponding apparatus or system for performing the methods, and vice versa. For example, if one or more particular method steps are described, the corresponding apparatus may comprise one or more units, such as functional units, to perform the described one or more method steps (e.g., a unit performs one or more steps, or multiple units, each of which performs one or more of the multiple steps), even if such one or more units are not explicitly described or illustrated in the figures. On the other hand, for example, if a particular apparatus is described based on one or more units, such as functional units, the corresponding method may comprise one step to perform the functionality of the one or more units (e.g., one step performs the functionality of the one or more units, or multiple steps, each of which performs the functionality of one or more of the plurality of units), even if such one or more steps are not explicitly described or illustrated in the figures. Further, it should be understood that features of the various exemplary embodiments and/or aspects described herein may be combined with each other, unless explicitly stated otherwise.

The technical scheme related to the embodiment of the application can be applied to the existing video coding standards (such as H.264, HEVC and the like) and can also be applied to the future video coding standards (such as H.266 standard). The terminology used in the description of the embodiments section of the present application is for the purpose of describing particular embodiments of the present application only and is not intended to be limiting of the present application. Some concepts that may be involved in embodiments of the present application are briefly described below.

Video coding generally refers to processing a sequence of pictures that form a video or video sequence. In the field of video coding, the terms "picture", "frame" or "image" may be used as synonyms. Video encoding as used herein means video encoding or video decoding. Video encoding is performed on the source side, typically including processing (e.g., by compressing) the original video picture to reduce the amount of data required to represent the video picture for more efficient storage and/or transmission. Video decoding is performed at the destination side, typically involving inverse processing with respect to the encoder, to reconstruct the video pictures. Embodiments are directed to video picture "encoding" to be understood as referring to "encoding" or "decoding" of a video sequence. The combination of the encoding part and the decoding part is also called codec (encoding and decoding).

A video sequence comprises a series of images (pictures) which are further divided into slices (slices) which are further divided into blocks (blocks). Video coding performs the coding process in units of blocks, and in some new video coding standards, the concept of blocks is further extended. For example, in the h.264 standard, there are Macroblocks (MBs), which can be further divided into a plurality of prediction blocks (partitions) that can be used for predictive coding. In the High Efficiency Video Coding (HEVC) standard, basic concepts such as a Coding Unit (CU), a Prediction Unit (PU), and a Transform Unit (TU) are adopted, and various block units are functionally divided, and a brand new tree-based structure is adopted for description. For example, a CU may be partitioned into smaller CUs in a quadtree, and the smaller CUs may be further partitioned to form a quadtree structure, where a CU is a basic unit for partitioning and encoding an encoded image. There is also a similar tree structure for PU and TU, and PU may correspond to a prediction block, which is the basic unit of predictive coding. The CU is further partitioned into PUs according to a partitioning pattern. A TU may correspond to a transform block, which is a basic unit for transforming a prediction residual. However, CU, PU and TU are all concepts of blocks (or image blocks).

For example, in HEVC, a CTU is split into CUs by using a quadtree structure represented as a coding tree. The decision whether to encode a picture region using inter-picture (temporal) or intra-picture (spatial) prediction is made at the CU level. Each CU may be further split into one, two, or four PUs according to the PU split type. The same prediction process is applied within one PU and the relevant information is transmitted to the decoder on a PU basis. After obtaining the residual block by applying a prediction process based on the PU split type, the CU may be partitioned into Transform Units (TUs) according to other quadtree structures similar to the coding tree used for the CU. In recent developments of video compression techniques, the coding blocks are partitioned using Quad-tree and binary tree (QTBT) partition frames. In the QTBT block structure, a CU may be square or rectangular in shape.

Herein, for convenience of description and understanding, an image block to be encoded in a currently encoded image may be referred to as a current block, e.g., in encoding, referring to a block currently being encoded; in decoding, refers to the block currently being decoded. A decoded image block in a reference picture used for predicting the current block is referred to as a reference block, i.e. a reference block is a block that provides a reference signal for the current block, wherein the reference signal represents pixel values within the image block. A block in the reference picture that provides a prediction signal for the current block may be a prediction block, wherein the prediction signal represents pixel values or sample values or a sampled signal within the prediction block. For example, after traversing multiple reference blocks, a best reference block is found that will provide prediction for the current block, which is called a prediction block.

In the case of lossless video coding, the original video picture can be reconstructed, i.e., the reconstructed video picture has the same quality as the original video picture (assuming no transmission loss or other data loss during storage or transmission). In the case of lossy video coding, the amount of data needed to represent the video picture is reduced by performing further compression, e.g., by quantization, while the decoder side cannot fully reconstruct the video picture, i.e., the quality of the reconstructed video picture is lower or worse than the quality of the original video picture.

Several video coding standards of h.261 belong to "lossy hybrid video codec" (i.e., the spatial and temporal prediction in the sample domain is combined with 2D transform coding in the transform domain for applying quantization). Each picture of a video sequence is typically partitioned into non-overlapping sets of blocks, typically encoded at the block level. In other words, the encoder side typically processes, i.e., encodes, video at the block (video block) level, e.g., generates a prediction block by spatial (intra-picture) prediction and temporal (inter-picture) prediction, subtracts the prediction block from the current block (currently processed or block to be processed) to obtain a residual block, transforms the residual block and quantizes the residual block in the transform domain to reduce the amount of data to be transmitted (compressed), while the decoder side applies the inverse processing portion relative to the encoder to the encoded or compressed block to reconstruct the current block for representation. In addition, the encoder replicates the decoder processing loop such that the encoder and decoder generate the same prediction (e.g., intra-prediction and inter-prediction) and/or reconstruction for processing, i.e., encoding, subsequent blocks.

The system architecture to which the embodiments of the present application apply is described below. Referring to fig. 1A, fig. 1A schematically illustrates a block diagram of a video encoding and decoding system 10 applied in an embodiment of the present application. As shown in fig. 1A, video encoding and decoding system 10 may include a source device 12 and a destination device 14, source device 12 generating encoded video data, and thus source device 12 may be referred to as a video encoding apparatus. Destination device 14 may decode the encoded video data generated by source device 12, and thus destination device 14 may be referred to as a video decoding apparatus. Various implementations of source apparatus 12, destination apparatus 14, or both may include one or more processors and memory coupled to the one or more processors. The memory can include, but is not limited to, RAM, ROM, EEPROM, flash memory, or any other medium that can be used to store desired program code in the form of instructions or data structures that can be accessed by a computer, as described herein. Source apparatus 12 and destination apparatus 14 may comprise a variety of devices, including desktop computers, mobile computing devices, notebook (e.g., laptop) computers, tablet computers, set-top boxes, telephone handsets such as so-called "smart" phones, televisions, cameras, display devices, digital media players, video game consoles, on-board computers, wireless communication devices, or the like.

Although fig. 1A depicts source apparatus 12 and destination apparatus 14 as separate apparatuses, an apparatus embodiment may also include the functionality of both source apparatus 12 and destination apparatus 14 or both, i.e., source apparatus 12 or corresponding functionality and destination apparatus 14 or corresponding functionality. In such embodiments, source device 12 or corresponding functionality and destination device 14 or corresponding functionality may be implemented using the same hardware and/or software, or using separate hardware and/or software, or any combination thereof.

A communication connection may be made between source device 12 and destination device 14 over link 13, and destination device 14 may receive encoded video data from source device 12 via link 13. Link 13 may comprise one or more media or devices capable of moving encoded video data from source apparatus 12 to destination apparatus 14. In one example, link 13 may include one or more communication media that enable source device 12 to transmit encoded video data directly to destination device 14 in real-time. In this example, source apparatus 12 may modulate the encoded video data according to a communication standard, such as a wireless communication protocol, and may transmit the modulated video data to destination apparatus 14. The one or more communication media may include wireless and/or wired communication media such as a Radio Frequency (RF) spectrum or one or more physical transmission lines. The one or more communication media may form part of a packet-based network, such as a local area network, a wide area network, or a global network (e.g., the internet). The one or more communication media may include a router, switch, base station, or other apparatus that facilitates communication from source apparatus 12 to destination apparatus 14.

Source device 12 includes an encoder 20, and in the alternative, source device 12 may also include a picture source 16, a picture preprocessor 18, and a communication interface 22. In one implementation, the encoder 20, the picture source 16, the picture preprocessor 18, and the communication interface 22 may be hardware components of the source device 12 or may be software programs of the source device 12. Described below, respectively:

the picture source 16, which may include or be any type of picture capturing device, may be used, for example, to capture real-world pictures, and/or any type of picture or comment generating device (for screen content encoding, some text on the screen is also considered part of the picture or image to be encoded), such as a computer graphics processor for generating computer animated pictures, or any type of device for obtaining and/or providing real-world pictures, computer animated pictures (e.g., screen content, virtual Reality (VR) pictures), and/or any combination thereof (e.g., augmented Reality (AR) pictures). The picture source 16 may be a camera for capturing pictures or a memory for storing pictures, and the picture source 16 may also include any kind of (internal or external) interface for storing previously captured or generated pictures and/or for obtaining or receiving pictures. When picture source 16 is a camera, picture source 16 may be, for example, an integrated camera local or integrated in the source device; when the picture source 16 is a memory, the picture source 16 can be an integrated memory that is local or integrated, for example, in the source device. When the picture source 16 comprises an interface, the interface may for example be an external interface receiving pictures from an external video source, for example an external picture capturing device such as a camera, an external memory or an external picture generating device, for example an external computer graphics processor, a computer or a server. The interface may be any kind of interface according to any proprietary or standardized interface protocol, e.g. a wired or wireless interface, an optical interface.

The picture can be regarded as a two-dimensional array or matrix of pixel elements (picture elements). The pixels in the array may also be referred to as sampling points. The number of sample points in the array or picture in the horizontal and vertical directions (or axes) defines the size and/or resolution of the picture. To represent color, three color components are typically employed, i.e., a picture may be represented as or contain three sample arrays. For example, in RBG format or color space, a picture includes corresponding arrays of red, green, and blue samples. However, in video coding, each pixel is typically represented in a luminance/chrominance format or color space, e.g. for pictures in YUV format, comprising a luminance component (sometimes also indicated with L) indicated by Y and two chrominance components indicated by U and V. The luminance (luma) component Y represents luminance or gray level intensity (e.g., both are the same in a gray scale picture), while the two chrominance (chroma) components U and V represent chrominance or color information components. Accordingly, a picture in YUV format includes a luma sample array of luma sample values (Y) and two chroma sample arrays of chroma values (U and V). Pictures in RGB format can be converted or transformed into YUV format and vice versa, a process also known as color transformation or conversion. If the picture is black and white, the picture may include only an array of luma samples. In the embodiment of the present application, the pictures transmitted from the picture source 16 to the picture processor may also be referred to as raw picture data 17.

Picture pre-processor 18 is configured to receive original picture data 17 and perform pre-processing on original picture data 17 to obtain pre-processed picture 19 or pre-processed picture data 19. For example, the pre-processing performed by picture pre-processor 18 may include trimming, color format conversion (e.g., from RGB format to YUV format), toning, or denoising.

An encoder 20 (or video encoder 20) for receiving the pre-processed picture data 19, processing the pre-processed picture data 19 with a relevant prediction mode (such as the prediction mode in various embodiments herein), thereby providing encoded picture data 21 (structural details of the encoder 20 will be described further below based on fig. 2 or fig. 4 or fig. 5). In some embodiments, the encoder 20 may be configured to perform various embodiments described hereinafter to implement the application of the chroma block prediction method described herein on the encoding side.

A communication interface 22, which may be used to receive encoded picture data 21 and may transmit encoded picture data 21 over link 13 to destination device 14 or any other device (e.g., memory) for storage or direct reconstruction, which may be any device for decoding or storage. Communication interface 22 may, for example, be used to encapsulate encoded picture data 21 into a suitable format, such as a data packet, for transmission over link 13.

Destination device 14 includes a decoder 30, and optionally destination device 14 may also include a communication interface 28, a picture post-processor 32, and a display device 34. Described below, respectively:

communication interface 28 may be used to receive encoded picture data 21 from source device 12 or any other source, such as a storage device, such as an encoded picture data storage device. The communication interface 28 may be used to transmit or receive the encoded picture data 21 by way of a link 13 between the source device 12 and the destination device 14, or by way of any kind of network, such as a direct wired or wireless connection, any kind of network, such as a wired or wireless network or any combination thereof, or any kind of private and public networks, or any combination thereof. Communication interface 28 may, for example, be used to decapsulate data packets transmitted by communication interface 22 to obtain encoded picture data 21.

Both communication interface 28 and communication interface 22 may be configured as a one-way communication interface or a two-way communication interface, and may be used, for example, to send and receive messages to establish a connection, acknowledge and exchange any other information related to a communication link and/or data transfer, such as an encoded picture data transfer.

A decoder 30, otherwise referred to as decoder 30, for receiving the encoded picture data 21 and providing decoded picture data 31 or decoded pictures 31 (structural details of the decoder 30 will be described further below based on fig. 3 or fig. 4 or fig. 5). In some embodiments, the decoder 30 may be configured to perform various embodiments described hereinafter to implement the application of the chroma block prediction method described herein on the decoding side.

A picture post-processor 32 for performing post-processing on the decoded picture data 31 (also referred to as reconstructed picture data) to obtain post-processed picture data 33. Post-processing performed by picture post-processor 32 may include: color format conversion (e.g., from YUV format to RGB format), toning, trimming or resampling, or any other process may also be used to transmit post-processed picture data 33 to display device 34.

A display device 34 for receiving the post-processed picture data 33 for displaying pictures to, for example, a user or viewer. Display device 34 may be or may include any type of display for presenting the reconstructed picture, such as an integrated or external display or monitor. For example, the display may include a Liquid Crystal Display (LCD), an Organic Light Emitting Diode (OLED) display, a plasma display, a projector, a micro LED display, a liquid crystal on silicon (LCoS), a Digital Light Processor (DLP), or any other display of any kind.

Although fig. 1A depicts source device 12 and destination device 14 as separate devices, device embodiments may also include the functionality of both source device 12 and destination device 14 or both, i.e., source device 12 or corresponding functionality and destination device 14 or corresponding functionality. In such embodiments, source device 12 or corresponding functionality and destination device 14 or corresponding functionality may be implemented using the same hardware and/or software, or using separate hardware and/or software, or any combination thereof.

It will be apparent to those skilled in the art from this description that the existence and (exact) division of the functionality of the different elements or source device 12 and/or destination device 14 shown in fig. 1A may vary depending on the actual device and application. Source device 12 and destination device 14 may comprise any of a variety of devices, including any type of handheld or stationary device, such as a notebook or laptop computer, a mobile phone, a smartphone, a tablet or tablet computer, a camcorder, a desktop computer, a set-top box, a television, a camera, an in-vehicle device, a display device, a digital media player, a video game console, a video streaming device (e.g., a content service server or a content distribution server), a broadcast receiver device, a broadcast transmitter device, etc., and may not use or use any type of operating system.

Both encoder 20 and decoder 30 may be implemented as any of a variety of suitable circuits, such as one or more microprocessors, digital Signal Processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), discrete logic, hardware, or any combinations thereof. If the techniques are implemented in part in software, an apparatus may store instructions of the software in a suitable non-transitory computer-readable storage medium and may execute the instructions in hardware using one or more processors to perform the techniques of this disclosure. Any of the foregoing, including hardware, software, a combination of hardware and software, etc., may be considered one or more processors.

In some cases, the video encoding and decoding system 10 shown in fig. 1A is merely an example, and the techniques of this application may be applied to video encoding settings (e.g., video encoding or video decoding) that do not necessarily involve any data communication between the encoding and decoding devices. In other examples, the data may be retrieved from local storage, streamed over a network, and so on. A video encoding device may encode and store data to memory, and/or a video decoding device may retrieve and decode data from memory. In some examples, the encoding and decoding are performed by devices that do not communicate with each other, but only encode data to and/or retrieve data from memory and decode data.

Referring to fig. 1B, fig. 1B is an illustrative diagram of an example of a video coding system 40 including encoder 20 of fig. 2 and/or decoder 30 of fig. 3, according to an example embodiment. Video coding system 40 may implement a combination of the various techniques of the embodiments of the present application. In the illustrated embodiment, video coding system 40 may include an imaging device 41, an encoder 20, a decoder 30 (and/or a video codec implemented by logic 47 of a processing unit 46), an antenna 42, one or more processors 43, one or more memories 44, and/or a display device 45.

As shown in fig. 1B, the imaging device 41, the antenna 42, the processing unit 46, the logic circuit 47, the encoder 20, the decoder 30, the processor 43, the memory 44, and/or the display device 45 are capable of communicating with each other. As discussed, although video coding system 40 is depicted with encoder 20 and decoder 30, in different examples video coding system 40 may include only encoder 20 or only decoder 30.

In some instances, antenna 42 may be used to transmit or receive an encoded bitstream of video data. Additionally, in some instances, display device 45 may be used to present video data. In some examples, logic 47 may be implemented by processing unit 46. The processing unit 46 may comprise application-specific integrated circuit (ASIC) logic, a graphics processor, a general-purpose processor, or the like. Video decoding system 40 may also include an optional processor 43, which optional processor 43 similarly may include application-specific integrated circuit (ASIC) logic, a graphics processor, a general-purpose processor, or the like. In some examples, the logic circuit 47 may be implemented by hardware, such as video coding specific hardware, etc., and the processor 43 may be implemented by general purpose software, an operating system, etc. In addition, the Memory 44 may be any type of Memory, such as a volatile Memory (e.g., static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), etc.) or a nonvolatile Memory (e.g., flash Memory, etc.), and the like. In a non-limiting example, storage 44 may be implemented by an ultracache memory. In some examples, logic circuitry 47 may access memory 44 (e.g., to implement an image buffer). In other examples, logic 47 and/or processing unit 46 may include memory (e.g., cache, etc.) for implementing image buffers, etc.

In some examples, encoder 20, implemented by logic circuitry, may include an image buffer (e.g., implemented by processing unit 46 or memory 44) and a graphics processing unit (e.g., implemented by processing unit 46). The graphics processing unit may be communicatively coupled to the image buffer. The graphics processing unit may include an encoder 20 implemented by logic circuitry 47 to implement the various modules discussed with reference to fig. 2 and/or any other encoder system or subsystem described herein. The logic circuitry may be used to perform various operations discussed herein.

In some examples, decoder 30 may be implemented by logic circuitry 47 in a similar manner to implement the various modules discussed with reference to decoder 30 of fig. 3 and/or any other decoder system or subsystem described herein. In some examples, logic circuit implemented decoder 30 may include an image buffer (implemented by processing unit 2820 or memory 44) and a graphics processing unit (e.g., implemented by processing unit 46). The graphics processing unit may be communicatively coupled to the image buffer. The graphics processing unit may include a decoder 30 implemented by logic circuitry 47 to implement the various modules discussed with reference to fig. 3 and/or any other decoder system or subsystem described herein.

In some examples, antenna 42 may be used to receive an encoded bitstream of video data. As discussed, the encoded bitstream may include data related to the encoded video frame, indicators, index values, mode selection data, etc., discussed herein, such as data related to the encoding partition (e.g., transform coefficients or quantized transform coefficients, (as discussed) optional indicators, and/or data defining the encoding partition). Video coding system 40 may also include a decoder 30 coupled to antenna 42 and used to decode the encoded bitstream. The display device 45 is used to present video frames.

It should be understood that for the example described with reference to encoder 20 in the embodiments of the present application, decoder 30 may be used to perform the reverse process. With respect to signaling syntax elements, decoder 30 may be configured to receive and parse such syntax elements and decode the associated video data accordingly. In some examples, encoder 20 may entropy encode the syntax elements into an encoded video bitstream. In such instances, decoder 30 may parse such syntax elements and decode the relevant video data accordingly.

It should be noted that the method described in the embodiment of the present application is mainly used for the inter-frame prediction process, which exists in both the encoder 20 and the decoder 30, and the encoder 20 and the decoder 30 in the embodiment of the present application may be a video standard protocol such as h.263, h.264, HEVV, MPEG-2, MPEG-4, VP8, VP9, or the like, or a codec corresponding to the next-generation video standard protocol (e.g., h.266, etc.).

Referring to fig. 2, fig. 2 shows a schematic/conceptual block diagram of an example of an encoder 20 for implementing embodiments of the present application. In the example of fig. 2, encoder 20 includes a residual calculation unit 204, a transform processing unit 206, a quantization unit 208, an inverse quantization unit 210, an inverse transform processing unit 212, a reconstruction unit 214, a buffer 216, a loop filter unit 220, a Decoded Picture Buffer (DPB) 230, a prediction processing unit 260, and an entropy encoding unit 270. Prediction processing unit 260 may include inter prediction unit 244, intra prediction unit 254, and mode selection unit 262. Inter prediction unit 244 may include a motion estimation unit and a motion compensation unit (not shown). The encoder 20 shown in fig. 2 may also be referred to as a hybrid video encoder or a video encoder according to a hybrid video codec.

For example, the residual calculation unit 204, the transform processing unit 206, the quantization unit 208, the prediction processing unit 260, and the entropy encoding unit 270 form a forward signal path of the encoder 20, and, for example, the inverse quantization unit 210, the inverse transform processing unit 212, the reconstruction unit 214, the buffer 216, the loop filter 220, the Decoded Picture Buffer (DPB) 230, the prediction processing unit 260 form a backward signal path of the encoder, wherein the backward signal path of the encoder corresponds to a signal path of a decoder (see the decoder 30 in fig. 3).

The encoder 20 receives, e.g., via an input 202, a picture 201 or an image block 203 of a picture 201, e.g., a picture in a sequence of pictures forming a video or a video sequence. Image block 203 may also be referred to as a current picture block or a picture block to be encoded, and picture 201 may be referred to as a current picture or a picture to be encoded (especially when the current picture is distinguished from other pictures in video encoding, such as previously encoded and/or decoded pictures in the same video sequence, i.e., a video sequence that also includes the current picture).

Embodiments of the encoder 20 may include a partitioning unit (not shown in fig. 2) for partitioning the picture 201 into a plurality of blocks, such as image blocks 203, typically into a plurality of non-overlapping blocks. The partitioning unit may be used to use the same block size for all pictures in a video sequence and a corresponding grid defining the block size, or to alter the block size between pictures or subsets or groups of pictures and partition each picture into corresponding blocks.

In one example, prediction processing unit 260 of encoder 20 may be used to perform any combination of the above-described segmentation techniques.

Like picture 201, image block 203 is also or can be considered as a two-dimensional array or matrix of sample points having sample values, although its size is smaller than picture 201. In other words, the image block 203 may comprise, for example, one sample array (e.g., a luminance array in the case of a black and white picture 201) or three sample arrays (e.g., a luminance array and two chrominance arrays in the case of a color picture) or any other number and/or class of arrays depending on the color format applied. The number of sampling points in the horizontal and vertical directions (or axes) of the image block 203 defines the size of the image block 203.

The encoder 20 as shown in fig. 2 is used to encode a picture 201 block by block, e.g. performing encoding and prediction for each image block 203.

The residual calculation unit 204 is configured to calculate a residual block 205 based on the picture image block 203 and the prediction block 265 (further details of the prediction block 265 are provided below), e.g. by subtracting sample values of the prediction block 265 from sample values of the picture image block 203 sample by sample (pixel by pixel) to obtain the residual block 205 in the sample domain.

The transform processing unit 206 is configured to apply a transform, such as a Discrete Cosine Transform (DCT) or a Discrete Sine Transform (DST), on the sample values of the residual block 205 to obtain transform coefficients 207 in a transform domain. The transform coefficients 207 may also be referred to as transform residual coefficients and represent the residual block 205 in the transform domain.

The transform processing unit 206 may be configured to apply integer approximations of DCT/DST, such as the transform specified for HEVC/h.265. Such integer approximations are typically scaled by some factor compared to the orthogonal DCT transform. To maintain the norm of the residual block processed by the forward transform and the inverse transform, an additional scaling factor is applied as part of the transform process. The scaling factor is typically selected based on certain constraints, e.g., the scaling factor is a power of 2 for a shift operation, a trade-off between bit depth of transform coefficients, accuracy and implementation cost, etc. For example, a specific scaling factor may be specified for the inverse transform at the decoder 30 side by, for example, the inverse transform processing unit 212 (and for the corresponding inverse transform at the encoder 20 side by, for example, the inverse transform processing unit 212), and correspondingly, a corresponding scaling factor may be specified for the forward transform at the encoder 20 side by the transform processing unit 206.

Quantization unit 208 is used to quantize transform coefficients 207, e.g., by applying scalar quantization or vector quantization, to obtain quantized transform coefficients 209. Quantized transform coefficients 209 may also be referred to as quantized residual coefficients 209. The quantization process may reduce the bit depth associated with some or all of transform coefficients 207. For example, n-bit transform coefficients may be rounded down to m-bit transform coefficients during quantization, where n is greater than m. The quantization level may be modified by adjusting a Quantization Parameter (QP). For example, for scalar quantization, different scales may be applied to achieve finer or coarser quantization. Smaller quantization steps correspond to finer quantization and larger quantization steps correspond to coarser quantization. An appropriate quantization step size may be indicated by a Quantization Parameter (QP). For example, the quantization parameter may be an index of a predefined set of suitable quantization step sizes. For example, a smaller quantization parameter may correspond to a fine quantization (smaller quantization step size) and a larger quantization parameter may correspond to a coarse quantization (larger quantization step size), or vice versa. The quantization may comprise a division by a quantization step size and a corresponding quantization or inverse quantization, e.g. performed by inverse quantization 210, or may comprise a multiplication by a quantization step size. Embodiments according to some standards, such as HEVC, may use a quantization parameter to determine the quantization step size. In general, the quantization step size may be calculated based on the quantization parameter using a fixed point approximation of an equation that includes division. Additional scaling factors may be introduced for quantization and dequantization to recover the norm of the residual block that may be modified due to the scale used in the fixed point approximation of the equation for the quantization step size and quantization parameter. In one example implementation, the inverse transform and inverse quantization scales may be combined. Alternatively, a custom quantization table may be used and signaled from the encoder to the decoder, e.g., in a bitstream. Quantization is a lossy operation, where the larger the quantization step size, the greater the loss.

The inverse quantization unit 210 is configured to apply inverse quantization of the quantization unit 208 on the quantized coefficients to obtain inverse quantized coefficients 211, e.g., to apply an inverse quantization scheme of the quantization scheme applied by the quantization unit 208 based on or using the same quantization step as the quantization unit 208. Inverse quantized coefficients 211 may also be referred to as inverse quantized residual coefficients 211, corresponding to transform coefficients 207, although the loss due to quantization is typically not the same as transform coefficients.

The inverse transform processing unit 212 is configured to apply an inverse transform of the transform applied by the transform processing unit 206, for example, an inverse Discrete Cosine Transform (DCT) or an inverse Discrete Sine Transform (DST), to obtain an inverse transform block 213 in the sample domain. The inverse transform block 213 may also be referred to as an inverse transform dequantized block 213 or an inverse transform residual block 213.

The reconstruction unit 214 (e.g., summer 214) is used to add the inverse transform block 213 (i.e., the reconstructed residual block 213) to the prediction block 265 to obtain the reconstructed block 215 in the sample domain, e.g., to add sample values of the reconstructed residual block 213 to sample values of the prediction block 265.

Optionally, a buffer unit 216 (or simply "buffer" 216), such as a line buffer 216, is used to buffer or store the reconstructed block 215 and corresponding sample values, for example, for intra prediction. In other embodiments, the encoder may be used to use the unfiltered reconstructed block and/or corresponding sample values stored in buffer unit 216 for any class of estimation and/or prediction, such as intra prediction.

For example, embodiments of encoder 20 may be configured such that buffer unit 216 is used not only to store reconstructed block 215 for intra prediction 254, but also for loop filter unit 220 (not shown in fig. 2), and/or such that buffer unit 216 and decoded picture buffer unit 230 form one buffer, for example. Other embodiments may be used to use filtered block 221 and/or blocks or samples from decoded picture buffer 230 (neither shown in fig. 2) as input or basis for intra prediction 254.

Loop filter unit 220 (or simply "loop filter" 220) is used to filter reconstructed block 215 to obtain filtered block 221 to facilitate pixel transitions or to improve video quality. Loop filter unit 220 is intended to represent one or more loop filters such as a deblocking filter, a sample-adaptive offset (SAO) filter, or other filters such as a bilateral filter, an Adaptive Loop Filter (ALF), or a sharpening or smoothing filter, or a collaborative filter. Although loop filter unit 220 is shown in fig. 2 as an in-loop filter, in other configurations, loop filter unit 220 may be implemented as a post-loop filter. The filtered block 221 may also be referred to as a filtered reconstructed block 221. The decoded picture buffer 230 may store the reconstructed encoded block after the loop filter unit 220 performs a filtering operation on the reconstructed encoded block.

Embodiments of encoder 20 (correspondingly, loop filter unit 220) may be configured to output loop filter parameters (e.g., sample adaptive offset information), e.g., directly or after entropy encoding by entropy encoding unit 270 or any other entropy encoding unit, e.g., such that decoder 30 may receive and apply the same loop filter parameters for decoding.

Decoded Picture Buffer (DPB) 230 may be a reference picture memory that stores reference picture data for use by encoder 20 in encoding video data. DPB 230 may be formed from any of a variety of memory devices, such as Dynamic Random Access Memory (DRAM) including Synchronous DRAM (SDRAM), magnetoresistive RAM (MRAM), resistive RAM (RRAM), or other types of memory devices. The DPB 230 and the buffer 216 may be provided by the same memory device or separate memory devices. In a certain example, a Decoded Picture Buffer (DPB) 230 is used to store filtered blocks 221. Decoded picture buffer 230 may further be used to store other previously filtered blocks, such as previously reconstructed and filtered blocks 221, of the same current picture or of a different picture, such as a previously reconstructed picture, and may provide the complete previously reconstructed, i.e., decoded picture (and corresponding reference blocks and samples) and/or partially reconstructed current picture (and corresponding reference blocks and samples), e.g., for inter prediction. In a certain example, if reconstructed block 215 is reconstructed without in-loop filtering, decoded Picture Buffer (DPB) 230 is used to store reconstructed block 215.

Prediction processing unit 260, also referred to as block prediction processing unit 260, is used to receive or obtain image block 203 (current image block 203 of current picture 201) and reconstructed picture data, e.g., reference samples of the same (current) picture from buffer 216 and/or reference picture data 231 of one or more previously decoded pictures from decoded picture buffer 230, and to process such data for prediction, i.e., to provide prediction block 265, which may be inter-predicted block 245 or intra-predicted block 255.

The mode selection unit 262 may be used to select a prediction mode (e.g., intra or inter prediction mode) and/or a corresponding prediction block 245 or 255 used as the prediction block 265 to calculate the residual block 205 and reconstruct the reconstructed block 215.

Embodiments of mode selection unit 262 may be used to select prediction modes (e.g., from those supported by prediction processing unit 260) that provide the best match or minimum residual (minimum residual means better compression in transmission or storage), or that provide the minimum signaling overhead (minimum signaling overhead means better compression in transmission or storage), or both. The mode selection unit 262 may be configured to determine a prediction mode based on Rate Distortion Optimization (RDO), i.e., select a prediction mode that provides the minimum rate distortion optimization, or select a prediction mode in which the associated rate distortion at least meets the prediction mode selection criteria.

The prediction processing performed by the instance of the encoder 20 (e.g., by the prediction processing unit 260) and the mode selection performed (e.g., by the mode selection unit 262) will be explained in detail below.

As described above, the encoder 20 is configured to determine or select the best or optimal prediction mode from a set of (predetermined) prediction modes. The prediction mode set may include, for example, intra prediction modes and/or inter prediction modes.

The intra prediction mode set may include 35 different intra prediction modes, for example, non-directional modes such as DC (or mean) mode and planar mode, or directional modes as defined in h.265, or may include 67 different intra prediction modes, for example, non-directional modes such as DC (or mean) mode and planar mode, or directional modes as defined in h.266 under development.

In possible implementations, the set of inter Prediction modes may include, for example, an Advanced Motion Vector Prediction (AMVP) mode and a merge (merge) mode depending on available reference pictures (i.e., at least partially decoded pictures stored in the DBP 230, for example, as described above) and other inter Prediction parameters, e.g., depending on whether the entire reference picture or only a portion of the reference picture, such as a search window region of a region surrounding the current block, is used to search for a best matching reference block, and/or depending on whether pixel interpolation, such as half-pixel and/or quarter-pixel interpolation, is applied, for example. In a specific implementation, the inter prediction mode set may include an improved control point-based AMVP mode and an improved control point-based merge mode according to the embodiment of the present application. In one example, intra-prediction unit 254 may be used to perform any combination of the inter-prediction techniques described below.

In addition to the above prediction mode, embodiments of the present application may also apply a skip mode and/or a direct mode.

The prediction processing unit 260 may further be configured to partition the image block 203 into smaller block partitions or sub-blocks, for example, by iteratively using quad-tree (QT) partitions, binary-tree (BT) partitions, or ternary-tree (TT) partitions, or any combination thereof, and to perform prediction, for example, for each of the block partitions or sub-blocks, wherein the mode selection includes selecting a tree structure of the partitioned image block 203 and selecting a prediction mode to apply to each of the block partitions or sub-blocks.

The inter prediction unit 244 may include a Motion Estimation (ME) unit (not shown in fig. 2) and a Motion Compensation (MC) unit (not shown in fig. 2). The motion estimation unit is used to receive or obtain a picture image block 203 (current picture image block 203 of current picture 201) and a decoded picture 231, or at least one or more previously reconstructed blocks, e.g., reconstructed blocks of one or more other/different previously decoded pictures 231, for motion estimation. For example, the video sequence may comprise a current picture and a previously decoded picture 31, or in other words, the current picture and the previously decoded picture 31 may be part of, or form the sequence of pictures forming the video sequence.

For example, the encoder 20 may be configured to select a reference block from a plurality of reference blocks of the same or different one of a plurality of other pictures and provide the reference picture and/or an offset (spatial offset) between a position (X, Y coordinates) of the reference block and a position of the current block to a motion estimation unit (not shown in fig. 2) as an inter prediction parameter. This offset is also called a Motion Vector (MV).

The motion compensation unit is configured to obtain an inter prediction parameter and perform inter prediction based on or using the inter prediction parameter to obtain an inter prediction block 245. The motion compensation performed by the motion compensation unit (not shown in fig. 2) may involve taking or generating a prediction block based on a motion/block vector determined by motion estimation (possibly performing interpolation to sub-pixel precision). Interpolation filtering may generate additional pixel samples from known pixel samples, potentially increasing the number of candidate prediction blocks that may be used to encode a picture block. Upon receiving the motion vector for the PU of the current picture block, motion compensation unit 246 may locate the prediction block in one reference picture list to which the motion vector points. Motion compensation unit 246 may also generate syntax elements associated with the blocks and video slices for use by decoder 30 in decoding picture blocks of a video slice.

Specifically, the inter prediction unit 244 may transmit a syntax element including an inter prediction parameter (e.g., indication information for selecting an inter prediction mode for current block prediction after traversing a plurality of inter prediction modes) to the entropy encoding unit 270. In a possible application scenario, if there is only one inter prediction mode, the inter prediction parameters may not be carried in the syntax element, and the decoding end 30 can directly use the default prediction mode for decoding. It will be appreciated that the inter prediction unit 244 may be used to perform any combination of inter prediction techniques.

The intra prediction unit 254 is used to obtain, for example, a picture block 203 (current picture block) of the same picture and one or more previously reconstructed blocks, e.g., reconstructed neighboring blocks, to be received for intra estimation. For example, the encoder 20 may be configured to select an intra-prediction mode from a plurality of (predetermined) intra-prediction modes.

Embodiments of encoder 20 may be used to select the intra prediction mode based on optimization criteria, such as based on a minimum residual (e.g., the intra prediction mode that provides the prediction block 255 most similar to the current picture block 203) or a minimum rate distortion.

The intra-prediction unit 254 is further configured to determine the intra-prediction block 255 based on the intra-prediction parameters as the selected intra-prediction mode. In any case, after selecting the intra-prediction mode for the block, intra-prediction unit 254 is also used to provide intra-prediction parameters, i.e., information indicating the selected intra-prediction mode for the block, to entropy encoding unit 270. In one example, intra-prediction unit 254 may be used to perform any combination of intra-prediction techniques.

Specifically, the above-described intra prediction unit 254 may transmit a syntax element including an intra prediction parameter (such as indication information of selecting an intra prediction mode for current block prediction after traversing a plurality of intra prediction modes) to the entropy encoding unit 270. In a possible application scenario, if there is only one intra-prediction mode, the intra-prediction parameters may not be carried in the syntax element, and the decoding end 30 may directly use the default prediction mode for decoding.

Entropy encoding unit 270 is configured to apply an entropy encoding algorithm or scheme (e.g., a Variable Length Coding (VLC) scheme, a Context Adaptive VLC (CAVLC) scheme, an arithmetic coding scheme, a context adaptive binary arithmetic coding (SBAC), a syntax-based context-adaptive binary arithmetic coding (syntax-based) coding, a Probability Interval Partitioning Entropy (PIPE) coding, or other entropy encoding methods or techniques) to individual or all of quantized residual coefficients 209, inter-prediction parameters, intra-prediction parameters, and/or loop filter parameters (or not) to obtain encoded picture data 21 that may be output by output 272 in the form of, for example, encoded bitstream 21. The encoded bitstream may be transmitted to video decoder 30 or archived for later transmission or retrieval by video decoder 30. Entropy encoding unit 270 may also be used to entropy encode other syntax elements of the current video slice being encoded.

Other structural variations of video encoder 20 may be used to encode the video stream. For example, the non-transform based encoder 20 may quantize the residual signal directly without the transform processing unit 206 for certain blocks or frames. In another embodiment, the encoder 20 may have the quantization unit 208 and the inverse quantization unit 210 combined into a single unit.

Specifically, in the embodiment of the present application, the encoder 20 may be used to implement the inter prediction method described in the following embodiments.

It should be understood that other structural variations of video encoder 20 may be used to encode the video stream. For example, for some image blocks or image frames, video encoder 20 may quantize the residual signal directly without processing by transform processing unit 206 and, correspondingly, without processing by inverse transform processing unit 212; alternatively, for some image blocks or image frames, the video encoder 20 does not generate residual data and accordingly does not need to be processed by the transform processing unit 206, the quantization unit 208, the inverse quantization unit 210, and the inverse transform processing unit 212; alternatively, video encoder 20 may store the reconstructed image block directly as a reference block without processing by filter 220; alternatively, the quantization unit 208 and the inverse quantization unit 210 in the video encoder 20 may be merged together. The loop filter 220 is optional, and in the case of lossless compression coding, the transform processing unit 206, the quantization unit 208, the inverse quantization unit 210, and the inverse transform processing unit 212 are optional. It is to be understood that the inter prediction unit 244 and the intra prediction unit 254 may be selectively enabled according to different application scenarios.

Referring to fig. 3, fig. 3 shows a schematic/conceptual block diagram of an example of a decoder 30 for implementing embodiments of the present application. Video decoder 30 is operative to receive encoded picture data (e.g., an encoded bitstream) 21, e.g., encoded by encoder 20, to obtain a decoded picture 231. During the decoding process, video decoder 30 receives video data, such as an encoded video bitstream representing picture blocks of an encoded video slice and associated syntax elements, from video encoder 20.

In the example of fig. 3, decoder 30 includes entropy decoding unit 304, inverse quantization unit 310, inverse transform processing unit 312, reconstruction unit 314 (e.g., summer 314), buffer 316, loop filter 320, decoded picture buffer 330, and prediction processing unit 360. The prediction processing unit 360 may include an inter prediction unit 344, an intra prediction unit 354, and a mode selection unit 362. In some examples, video decoder 30 may perform a decoding pass that is substantially reciprocal to the encoding pass described with reference to video encoder 20 of fig. 2.

Entropy decoding unit 304 is to perform entropy decoding on encoded picture data 21 to obtain, for example, quantized coefficients 309 and/or decoded encoding parameters (not shown in fig. 3), such as any or all of inter-prediction, intra-prediction parameters, loop filter parameters, and/or other syntax elements (decoded). The entropy decoding unit 304 is further for forwarding the inter-prediction parameters, the intra-prediction parameters, and/or other syntax elements to the prediction processing unit 360. Video decoder 30 may receive video slice-level and/or video block-level syntax elements.

Inverse quantization unit 310 may be functionally identical to inverse quantization unit 110, inverse transform processing unit 312 may be functionally identical to inverse transform processing unit 212, reconstruction unit 314 may be functionally identical to reconstruction unit 214, buffer 316 may be functionally identical to buffer 216, loop filter 320 may be functionally identical to loop filter 220, and decoded picture buffer 330 may be functionally identical to decoded picture buffer 230.

Prediction processing unit 360 may include inter prediction unit 344 and intra prediction unit 354, where inter prediction unit 344 may be functionally similar to inter prediction unit 244 and intra prediction unit 354 may be functionally similar to intra prediction unit 254. The prediction processing unit 360 is typically used to perform block prediction and/or to obtain a prediction block 365 from the encoded data 21, as well as to receive or obtain (explicitly or implicitly) prediction related parameters and/or information about the selected prediction mode from, for example, the entropy decoding unit 304.

When the video slice is encoded as an intra-coded (I) slice, intra-prediction unit 354 of prediction processing unit 360 is used to generate a prediction block 365 for the picture block of the current video slice based on the signaled intra-prediction mode and data from previously decoded blocks of the current frame or picture. When a video frame is encoded as an inter-coded (i.e., B or P) slice, inter prediction unit 344 (e.g., a motion compensation unit) of prediction processing unit 360 is used to generate a prediction block 365 for the video block of the current video slice based on the motion vectors and other syntax elements received from entropy decoding unit 304. For inter prediction, a prediction block may be generated from one reference picture within one reference picture list. Video decoder 30 may construct the reference frame list using default construction techniques based on the reference pictures stored in DPB 330: list 0 and list 1.

Prediction processing unit 360 is used to determine prediction information for the video blocks of the current video slice by parsing the motion vectors and other syntax elements, and to generate a prediction block for the current video block being decoded using the prediction information. In an example of the present application, prediction processing unit 360 uses some of the syntax elements received to determine a prediction mode (e.g., intra or inter prediction) for encoding video blocks of a video slice, an inter prediction slice type (e.g., B-slice, P-slice, or GPB-slice), construction information for one or more of a reference picture list of the slice, a motion vector for each inter-coded video block of the slice, an inter prediction state for each inter-coded video block of the slice, and other information to decode video blocks of a current video slice. In another example of the present disclosure, the syntax elements received by video decoder 30 from the bitstream include syntax elements received in one or more of an Adaptive Parameter Set (APS), a Sequence Parameter Set (SPS), a Picture Parameter Set (PPS), or a slice header.

Inverse quantization unit 310 may be used to inverse quantize (i.e., inverse quantize) the quantized transform coefficients provided in the bitstream and decoded by entropy decoding unit 304. The inverse quantization process may include using quantization parameters calculated by video encoder 20 for each video block in the video slice to determine the degree of quantization that should be applied and likewise the degree of inverse quantization that should be applied.

Inverse transform processing unit 312 is used to apply an inverse transform (e.g., an inverse DCT, an inverse integer transform, or a conceptually similar inverse transform process) to the transform coefficients in order to produce a residual block in the pixel domain.

The reconstruction unit 314 (e.g., summer 314) is used to add the inverse transform block 313 (i.e., reconstructed residual block 313) to the prediction block 365 to obtain the reconstructed block 315 in the sample domain, e.g., by adding sample values of the reconstructed residual block 313 to sample values of the prediction block 365.

Loop filter unit 320 (either during or after the encoding cycle) is used to filter reconstructed block 315 to obtain filtered block 321 to facilitate pixel transitions or improve video quality. In one example, loop filter unit 320 may be used to perform any combination of the filtering techniques described below. Loop filter unit 320 is intended to represent one or more loop filters, such as a deblocking filter, a sample-adaptive offset (SAO) filter, or other filters, such as a bilateral filter, an Adaptive Loop Filter (ALF), or a sharpening or smoothing filter, or a collaborative filter. Although loop filter unit 320 is shown in fig. 3 as an in-loop filter, in other configurations, loop filter unit 320 may be implemented as a post-loop filter.

Decoded video block 321 in a given frame or picture is then stored in decoded picture buffer 330, which stores reference pictures for subsequent motion compensation.

Decoder 30 is used to output decoded picture 31, e.g., via output 332, for presentation to or viewing by a user.

Other variations of video decoder 30 may be used to decode the compressed bitstream. For example, decoder 30 may generate an output video stream without loop filter unit 320. For example, the non-transform based decoder 30 may inverse quantize the residual signal directly without the inverse transform processing unit 312 for certain blocks or frames. In another embodiment, video decoder 30 may have inverse quantization unit 310 and inverse transform processing unit 312 combined into a single unit.

Specifically, in the embodiment of the present application, the decoder 30 is configured to implement the inter prediction method described in the following embodiments.

It should be understood that other structural variations of video decoder 30 may be used to decode the encoded video bitstream. For example, video decoder 30 may generate an output video stream without processing by filter 320; alternatively, for some image blocks or image frames, the quantized coefficients are not decoded by entropy decoding unit 304 of video decoder 30 and, accordingly, do not need to be processed by inverse quantization unit 310 and inverse transform processing unit 312. Loop filter 320 is optional; and the inverse quantization unit 310 and the inverse transform processing unit 312 are optional for the case of lossless compression. It should be understood that the inter prediction unit and the intra prediction unit may be selectively enabled according to different application scenarios.

It should be understood that, in the encoder 20 and the decoder 30 of the present application, the processing result of a certain link may be further processed and then output to the next link, for example, after the links such as interpolation filtering, motion vector derivation, or loop filtering, the processing result of the corresponding link is further subjected to operations such as Clip or shift.

For example, the motion vector of the control point of the current image block, which is derived according to the motion vector of the adjacent affine coding block, may be further processed, which is not limited in the present application. For example, the value range of the motion vector is constrained to be within a certain bit width. Assuming that the allowed bit-width of the motion vector is bitDepth, the motion vector ranges from-2 ^ (bitDepth-1) to 2^ (bitDepth-1) -1, where the "^" symbol represents the power. If the bitDepth is 16, the value range is-32768-32767. If the bitDepth is 18, the value range is-131072-131071. The constraint can be made in two ways:

mode 1, the high bits of the motion vector overflow are removed:

ux＝(vx+2 ^bitDepth )％2 ^bitDepth

vx＝(ux>＝2 ^bitDepth-1 )？(ux-2 ^bitDepth ):ux

uy＝(vy+2 ^bitDepth )％2 ^bitDepth

vy＝(uy>＝2 ^bitDepth-1 )？(uy-2 ^bitDepth ):uy

for example, vx has a value of-32769, which is obtained by the above equation of 32767. Since in a computer the values are stored as two's complement, -32769's complement of 1,0111,1111 (17 bits), the computer discards the high bits for overflow processing, the vx has a value of 0111,1111, 32767, consistent with the results obtained by the formula processing.

In the method 2, the motion vector is clipped, as shown in the following formula:

vx＝Clip3(-2 ^bitDepth-1 ,2 ^bitDepth-1 -1,vx)

vy＝Clip3(-2 ^bitDepth-1 ,2 ^bitDepth-1 -1,vy)

where Clip3 is defined to mean clamping the value of z between the intervals [ x, y ]:

referring to fig. 4, fig. 4 is a schematic structural diagram of a video coding apparatus 400 (e.g., a video encoding apparatus 400 or a video decoding apparatus 400) provided in an embodiment of the present application. Video coding apparatus 400 is suitable for implementing the embodiments described herein. In one embodiment, video coding device 400 may be a video decoder (e.g., decoder 30 of fig. 1A) or a video encoder (e.g., encoder 20 of fig. 1A). In another embodiment, video coding device 400 may be one or more components of decoder 30 of fig. 1A or encoder 20 of fig. 1A described above.

Video coding apparatus 400 includes: an ingress port 410 and a reception unit (Rx) 420 for receiving data, a processor, logic unit or Central Processing Unit (CPU) 430 for processing data, a transmitter unit (Tx) 440 and an egress port 450 for transmitting data, and a memory 460 for storing data. Video coding device 400 may also include optical-to-Electrical (EO) components and optical-to-electrical (opto) components coupled with ingress port 410, receiver unit 420, transmitter unit 440, and egress port 450 for egress or ingress of optical or electrical signals.

The processor 430 is implemented by hardware and software. Processor 430 may be implemented as one or more CPU chips, cores (e.g., multi-core processors), FPGAs, ASICs, and DSPs. Processor 430 is in communication with inlet port 410, receiver unit 420, transmitter unit 440, outlet port 450, and memory 460. Processor 430 includes a coding module 470 (e.g., encoding module 470 or decoding module 470). The encoding/decoding module 470 implements embodiments disclosed herein to implement the chroma block prediction methods provided by embodiments of the present application. For example, the encode/decode module 470 implements, processes, or provides various encoding operations. Accordingly, substantial improvements are provided to the functionality of the video coding apparatus 400 by the encoding/decoding module 470 and affect the transition of the video coding apparatus 400 to different states. Alternatively, the encode/decode module 470 is implemented as instructions stored in the memory 460 and executed by the processor 430.

The memory 460, which may include one or more disks, tape drives, and solid state drives, may be used as an over-flow data storage device for storing programs when such programs are selectively executed, and for storing instructions and data that are read during program execution. The memory 460 may be volatile and/or nonvolatile, and may be Read Only Memory (ROM), random Access Memory (RAM), random access memory (TCAM), and/or Static Random Access Memory (SRAM).

Referring to fig. 5, fig. 5 is a simplified block diagram of an apparatus 500 that may be used as either or both of source device 12 and destination device 14 in fig. 1A according to an example embodiment. Apparatus 500 may implement the techniques of this application. In other words, fig. 5 is a schematic block diagram of an implementation manner of an encoding apparatus or a decoding apparatus (simply referred to as a decoding apparatus 500) of the embodiment of the present application. The decoding apparatus 500 may include, among other things, a processor 510, a memory 530, and a bus system 550. Wherein the processor is connected with the memory through the bus system, the memory is used for storing instructions, and the processor is used for executing the instructions stored by the memory. The memory of the coding device stores program code, and the processor may call the program code stored in the memory to perform various video encoding or decoding methods described herein, particularly various new inter-frame methods. To avoid repetition, it is not described in detail here.

In the embodiment of the present application, the processor 510 may be a Central Processing Unit (CPU), and the processor 510 may also be other general-purpose processors, digital Signal Processors (DSP), application Specific Integrated Circuits (ASIC), field Programmable Gate Arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, and so on. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.

The memory 530 may include a Read Only Memory (ROM) device or a Random Access Memory (RAM) device. Any other suitable type of memory device may also be used for memory 530. Memory 530 may include code and data 531 accessed by processor 510 using bus 550. Memory 530 may further include operating system 533 and application programs 535, the application programs 535 including at least one program that allows processor 510 to perform the video encoding or decoding methods described herein, and in particular the inter-prediction methods described herein. For example, the application programs 535 may include applications 1 through N, which further include a video encoding or decoding application (simply a video coding application) that performs the video encoding or decoding methods described herein.

The bus system 550 may include a power bus, a control bus, a status signal bus, and the like, in addition to a data bus. For clarity of illustration, however, the various buses are designated in the figure as bus system 550.

Optionally, the translator device 500 may also include one or more output devices, such as a display 570. In one example, the display 570 may be a touch-sensitive display that incorporates a display with a touch-sensitive unit operable to sense touch input. A display 570 may be connected to the processor 510 via the bus 550.

In the current stage, the video coding and decoding technology mainly adopts a hybrid coding architecture, and utilizes the correlation of video sequences in space and time dimensions to remove a large amount of redundant information existing in a video signal to be transmitted. The hybrid coding framework mainly comprises two parts of prediction coding and transformation coding. The predictive coding uses the coded pixel to predict the current pixel, then calculates the residual between the predicted value and the true value, and codes and transmits the residual. The core of predictive coding consists in the calculation of MVs (motion vectors) and in choosing the index of the reference frame in the reference list. The MV and reference frame indices are shown in fig. 6. The present stage is based on the type of coded frame and the difference of reference mode to obtain different types of MV (motion vector) and reference lists. Transform coding refers to obtaining transform coefficients from an image described in a spatial domain through a specific transform kernel (such as discrete cosine transform, hadamard transform, etc.), so as to achieve the purposes of changing data distribution and further reducing data amount. The inter-frame prediction referred to in the present application employs predictive coding.

The inter-frame Prediction targeted by the embodiment of the present application is a historical-based Motion Vector Prediction (HMVP).

In the current inter prediction process, a candidate motion vector list or a candidate prediction motion vector list, that is, an HMVP list, of a current coding and decoding block may be constructed according to motion information of a reconstructed block that is coded or decoded before the current coding and decoding block. The HMVP list stores candidate motion information in the form of a queue. The candidate motion information includes information such as MV, prediction direction, and reference frame index of the coded unit. Typically, the maximum length of the HMVP queue is set to 13. The first 5 candidate motion information in the HMVP queue respectively represent motion information corresponding to five modes of temporal skip (skip), B-frame forward, B-frame backward, B-frame bi-directional, and B-frame symmetric. When the pixel value of a block to be processed is predicted, traversing all candidate motion information from the generated HMVP queue of the block to be processed, calculating RDO, and selecting the motion information represented by the minimum RDO as the motion information of the block to be processed.

It should be noted that HMVP is only used for skip/direct (direct) mode.

In addition, when motion information of one coded unit is added into the HMVP queue, the HMVP continuously updates candidate motion information in the HMVP queue. The update rule of candidate motion information in the queue is as follows:

1. if the length of the HMVP queue does not reach the maximum length upper limit and the motion information is different from the candidate motion information in the HMVP queue, the motion information is stored at the end of the HMVP queue, as shown in fig. 7.

2. If the motion information is the same as the candidate motion information already existing in the HMVP queue, the candidate motion information identical to the motion information already existing in the HMVP queue is removed and stored at the end of the HMVP queue as the candidate motion information regardless of whether the length of the HMVP queue has reached the maximum length upper limit preset in the HMVP queue, as shown in fig. 8.

3. If the number of candidate motion information in the HMVP queue reaches or exceeds the maximum length limit, adopting FIFO principle to eliminate whether the motion information is the same as the candidate motion information in the HMVP queue or notRemoving candidate motion information existing in the HMVP queue and storing the motion information at the end of the HMVP queue as candidate motion information, as shown in fig. 9, removing HMVP0 in the HMVP queue and adding HMVP1-HMVP _L-1 And moving to the left in turn, and adding the motion information HMVP candidate to be added at the end of the HMVP queue.

For a P frame, only motion information of an encoded block of a forward reference frame can be referred to, and when candidate motion information is removed from the HMVP queue, motion information that can be adopted for the P frame may be removed, which results in less motion information that can be referred to when inter-frame prediction is performed on a block to be processed of the P frame, and thus results in lower prediction accuracy. In addition, the pixel value of the current block to be processed estimated from the motion information existing in the HMVP queue is not necessarily the optimal motion information, and motion information extraction has a lifting space as it is.

In order to improve the prediction accuracy, embodiments of the present application provide a method and an apparatus for video image prediction, where, on the basis that the HMVP technology has obtained a queue including multiple motion information, an additional motion information is derived for each candidate motion information meeting a specific requirement in the HMVP queue (for example, the reference direction of the current block to be processed is forward direction) to provide more candidate motion information.

The scheme provided by the embodiments of the present application will be described in detail below from the encoding end.

Referring to fig. 10, a flowchart of a video image prediction method provided in the embodiment of the present application is shown, and the method may be performed by a video image prediction apparatus, for example, the video image prediction apparatus may be the encoder 20 shown in fig. 2, or an inter-frame prediction unit 244 in the encoder 20, or one or more processors capable of performing encoding, or a chip system.

For example, the HMVP includes N candidate motion vectors, and the video image prediction apparatus traverses each candidate motion vector included in the HMVP queue, and specifically executes the following procedure:

s1001, obtaining first candidate motion information from a historical motion vector prediction queue corresponding to a block to be processed, wherein the first candidate motion information comprises a prediction direction of a candidate coded block, a reference frame index of the block to be processed and a motion vector of the candidate coded block.

The first candidate motion information is one of the historical motion vector prediction queues, and may be, for example, one candidate motion information traversed by the video image prediction apparatus.

Illustratively, the first candidate motion information is obtained from the historical motion vector prediction queue corresponding to the block to be processed, that is, the first candidate motion information corresponding to the currently traversed index is obtained from the HMVP corresponding to the block to be processed.

After the first candidate motion information is obtained, whether to execute a derivation procedure is determined according to a prediction direction of the candidate encoded block included in the first candidate motion information.

S1002, when the prediction direction is forward and the number of reference frames in the reference frame list corresponding to the block to be processed is greater than 1, determining a derived reference frame index according to the reference frame index.

As an example, the relationship of the reference frame index to the derived reference frame index is:

if the current reference frame index is 0, then the derived reference frame index is 1; or,

if the current reference frame index is not 0, then the derived reference frame index is 0.

Illustratively, the inter-frame prediction mode adopted by the block to be processed is a skip mode or a direct mode.

In a feasible example, if the inter prediction mode adopted by the block to be processed is not a skip mode and a direct mode, a derivation procedure is not executed, and a pixel prediction value of the image to be processed, which is determined only based on the first candidate motion information, is used as the pixel prediction value of the block to be processed corresponding to the first candidate motion information.

And S1003, performing scaling processing on the motion vector included in the first candidate motion information based on the distance between the reference frame indicated by the reference frame index and the current frame where the block to be processed is located and the distance between the derived reference frame indicated by the derived reference frame index and the current frame, to obtain a derived motion vector of the first candidate motion information.

It should be noted that the distance between different frames is defined as: the absolute position of the current frame in the video sequence minus the absolute position of the reference frame in the video sequence is the distance between the current frame and the reference frame.

S1004, determining a pixel predictor of the block to be processed corresponding to the first candidate motion information based on the first candidate motion information, the derived reference frame index, and the derived motion vector.

The following example illustrates an implementation manner for determining a pixel prediction value of the block to be processed corresponding to the first candidate motion information:

determining a pixel prediction value of the block to be processed according to the first candidate motion information, which is called a first prediction value for descriptive convenience; and determining a pixel predicted value of the block to be processed according to the derived motion vector and the derived reference frame index, for convenience of description, the pixel predicted value is called a derived pixel predicted value, then determining the sum of the first predicted value multiplied by a first weight and the derived pixel predicted value multiplied by a second weight as a second predicted value, and taking the predicted value with the minimum SATD value in the first predicted value and the second predicted value as the pixel predicted value of the block to be processed corresponding to the first candidate motion information.

In one possible example, the method may further include:

s1005, when the prediction direction is backward or bi-directional, taking (without performing derivation procedure) a pixel prediction value of the to-be-processed image determined based only on the first candidate motion information as a pixel prediction value of the to-be-processed block corresponding to the first candidate motion information.

In another possible example, the method may further include:

s1006, when the number of reference frames included in the reference frame list corresponding to the block to be processed is equal to 1, (without performing a derivation procedure), using a pixel prediction value of an image to be processed determined based on only the first candidate motion information as a pixel prediction value of the block to be processed corresponding to the first candidate motion information.

Illustratively, referring to fig. 11, a method of determining a derived motion vector is illustrated.

After obtaining the derived reference frame index, the derived motion vector may be further calculated. Illustratively, this may be achieved by:

assuming that the distance between the derived reference frame and the current frame is d0 'and the distance between the reference frame and the current frame of the first candidate motion information is d0, the derived scaling factor of the derived motion vector and the motion vector of the coded block in the first candidate motion information in the HMVP queue is d0'/d0, based on which the derived motion vector is determined to be MV '= (d 0'/d 0) MV.

For example, after determining the derived motion vector, the pixel predictor of the block to be processed corresponding to the first candidate motion information may be determined according to the first candidate motion information, the derived reference frame index and the derived motion vector as follows:

based on the derived motion vector and the derived reference frame index, a new pixel predictor, for example referred to as derived pixel predictor pred0', is obtained. The pixel predictor of the block to be processed, which is determined on the basis of the first candidate motion information, is referred to as a first predictor pred0, for example. The weighted sum of the derived pixel-based predictor and the first predictor will be referred to as the second predictor. The two predictors (first predictor and second predictor) are used to calculate corresponding SATD values and compare the SATD values. And taking the predicted value with the minimum SATD value as the pixel predicted value of the block to be processed corresponding to the first candidate motion information.

Illustratively, the second predictor is equal to the sum of the derived pixel predictor multiplied by a second weight (which may be referred to as a second weight) and the first predictor multiplied by a first weight (which may be referred to as a first weight). The sum of the first weight and the second weight is equal to 1, for example, the first weight = the second weight =0.5.

In the embodiment of the present application, after the pixel values corresponding to the candidate motion information in the HMVP queue are determined in the above manner, the pixel prediction value with the minimum rate distortion cost among the pixel prediction values corresponding to the N candidate motion information respectively may be selected, and the second candidate motion information and the index identifier corresponding to the pixel prediction value with the minimum rate distortion cost are encoded into the code stream. Wherein, when the pixel predicted value corresponding to the second candidate motion information is determined based on the second candidate motion information and the derived motion vector of the second candidate motion information, that is, the pixel predicted value corresponding to the second candidate motion information is determined by performing a deriving operation, the index is identified as a first value; when the pixel predictor corresponding to the second candidate motion information is determined based on only the second candidate motion information, that is, the pixel predictor corresponding to the second candidate motion information is not determined by performing the derivation operation, the index is identified as the second value. For example, the first value is 1 and the second value is 0. In the following description, the first value is 1, and the second value is 0.

As an example, when selecting a pixel prediction value with the minimum rate distortion cost from pixel prediction values corresponding to N pieces of candidate motion information, and determining an index identifier, the following steps may be performed:

the first method is a method of updating while traversing. For example, the HMVP includes N candidate motion information, HMVP0-HMVP _N-1 . This is achieved in the manner shown in fig. 10.

In the following, traversing two HMVP0 and HMVP1 is taken as an example:

a1, traversing to the HMVP0 in the HMVP queue, and determining whether the HMVP0 executes the derivation operation. If yes, execute A2, if no, predict the pixel prediction value of the block to be processed as pred0[0] based on HMVP 0.

A2: respectively predicting pixel predicted values of the processing blocks by using two types of motion information, calculating SATD according to the two predicted values, and comparing the two SATD values:

specifically, the HMVP0 calculates the predicted pixel value as pred0[0]. This HMVP0 is then used to derive new motion information. Finally, the pixel prediction value is calculated through the derived motion information and weighted and summed with pred0[0] to be used as a new pixel prediction value pred0[1]. SATD values SATD0[0] and SATD0[1] corresponding to the predicted pixel values pred0[0] and pred0[1] are calculated, respectively.

A3: and determining the pixel predicted value of the block to be processed according to the SATD value, and assigning the index identification Flag.

For example, if SATD0[0] is less than or equal to SATD0[1], the predicted pixel value is pred0[0], i.e. derivation operation is not adopted, flag is set to 0; if SATD0[0] > SATD0[1], the predicted pixel value is pred0[1], i.e., a derivation operation is used, and Flag is set to 1.

As an example, taking Flag as 1, the traversal of HMVP1 is continued in the above manner.

For example, the predicted pixel value corresponding to HMVP1 is pred1[1], that is, by taking a derivation operation as an example, if it is determined that the predicted value with the minimum rate distortion cost in the predicted pixel value pred0[1] corresponding to HMVP0 and the predicted pixel value pred1[1] corresponding to HMVP1 is pred1[1], the Flag value is not changed, and is also 1, the next HMVP2 is continuously traversed, and so on, and when performing comparison for HMVP2, the predicted value pred1[1] with the minimum rate distortion cost in the predicted pixel value pred0[1] corresponding to HMVP0 and the predicted value pred1[1] corresponding to HMVP1 are compared. If the predicted value with the minimum rate distortion cost in the pixel predicted value pred0[1] corresponding to the HMVP0 and the pixel predicted value pred1[1] corresponding to the HMVP1 is determined to be pred0[1], the Flag value is not changed, the next HMVP2 is continuously traversed, and when the HMVP2 is compared, the predicted value pred0[1] with the minimum rate distortion cost in the pixel predicted value pred0[1] corresponding to the HMVP0 and the predicted value pred0[1] with the minimum rate distortion cost in the pixel predicted value pred1[1] corresponding to the HMVP1 are compared.

For example, if the predicted pixel value corresponding to HMVP1 is pred1[0], that is, no derivation operation is adopted as an example, if it is determined that the predicted pixel value pred0[1] corresponding to HMVP0 and the predicted value with the minimum rate distortion cost in the predicted pixel value pred0[1] corresponding to HMVP1 are pred1[0], the Flag value is updated to 0, and the next HMVP2 is traversed, and so on. And when the comparison is performed for the HMVP2, the pixel prediction value pred0[1] corresponding to the determined HMVP0 and the prediction value pred1[0] with the smallest rate distortion cost in the pixel prediction value pred1[1] corresponding to the HMVP1 are compared.

The second way is: for N candidate motion information included in HMVP queueAnd after the completion of the calendar, assigning the index identifier. Such as determining HMVP0-HMVP _N-1 And respectively setting the predicted value with the minimum rate distortion cost in the corresponding pixel predicted values as HMVPk, if the pixel predicted value corresponding to the HMVPk does not adopt derivative operation, assigning the index identifier as 0, and if the derivative operation is adopted, assigning the index identifier as 1.

Illustratively, after determining the second candidate motion information and the index flag, the second candidate motion information (or the flag of the second candidate motion information) and the index flag are transmitted to the decoding side.

The following describes the video image prediction method provided in the embodiments of the present application in detail from the decoding side. The inventive concept adopted by the decoding side and the encoding side is similar, and repeated parts are not described again, specifically referring to the related description of the encoding side.

Referring to fig. 12, a schematic flow chart of a video image prediction method provided in the embodiment of the present application and corresponding to a decoding side is shown. The method may be performed by a video image prediction apparatus, which may be, for example, the encoder 30 shown in fig. 3, or the inter prediction unit 344 in the encoder 30, or one or more processors capable of performing decoding, or a chip system.

S1201, candidate motion information and an index identifier are determined, wherein the candidate motion information comprises a reference frame index of a block to be processed and a candidate motion vector identifier, and the motion vector identifier is used for indicating a motion vector of a decoded block referred by the block to be processed.

It should be noted that, if the motion information candidate corresponds to the encoding side, the motion information candidate here is the second motion information candidate.

For example, the candidate motion information and the index identifier may be determined by parsing the candidate motion information and the index identifier from the code stream by the entropy decoding unit, and transmitting the result to the video image prediction apparatus.

S1202, when the index mark is a first numerical value, determining a derived reference frame index according to the reference frame index.

S1203, based on a distance between a reference frame indicated by the reference frame index and a current frame where the block to be processed is located, and a distance between a derived reference frame indicated by the derived reference frame index and the current frame, performing scaling processing on the motion vector of the decoded block to obtain a derived motion vector of the candidate motion information.

S1204, determining a pixel predictor of the block to be processed based on the candidate motion information, the derived reference frame index, and the derived motion vector.

An implementation of determining a pixel prediction value of the block to be processed is as follows:

determining a pixel prediction value of the block to be processed according to the candidate motion information, which is called a first prediction value for descriptive convenience; and determining a pixel predicted value of the block to be processed according to the derived motion vector and the derived reference frame index, for the convenience of description, the pixel predicted value is called a derived pixel predicted value, and then the sum of the first predicted value multiplied by the first weight and the derived pixel predicted value multiplied by the second weight is determined as the pixel predicted value of the block to be processed.

Based on this, the pixel predictor of the block to be processed is equal to the sum of a first weight value and a second weight value, the first weight value is equal to the pixel predictor of the block to be processed determined based on the candidate motion information only multiplied by a first weight value, the second weight value is equal to the pixel predictor of the block to be processed determined based on the derived motion vector and the derived reference frame index multiplied by a second weight value, and the sum of the first weight value and the second weight value is equal to 1. For example, the first weight = the second weight =0.5.

In one possible example, the method may further include:

and S1205, when the index mark is a second numerical value, determining the pixel prediction value of the image to be processed only based on the candidate motion information.

Illustratively, the derived motion vector is obtained according to the following formula:

MV′＝(d0′/d0)MV；

where MV 'represents the derived motion vector, d0' represents the distance between the derived reference frame and the current frame, d0 represents the distance between the reference frame and the current frame, and MV represents the motion vector of the decoded block.

Exemplarily, determining a derived reference frame index from the reference frame index may be implemented as follows: when the reference frame index is zero, the derived reference frame index is 1; when the reference frame index is non-zero, the derived reference frame index is 0.

Based on the same inventive concept as the above method, as shown in fig. 13, an embodiment of the present application further provides an apparatus 1300, where the apparatus 1300 includes an entropy decoding unit 1301 and an inter-prediction unit 1302. The apparatus 1300 may specifically be a processor, or a chip or a system of chips, in a video decoder, or one or more modules in a video decoder.

An entropy decoding unit 1301, configured to parse candidate motion information and an index identifier from a code stream, where the candidate motion information includes a reference frame index of a block to be processed and a candidate motion vector identifier, and the motion vector identifier is used to indicate a motion vector of a decoded block referred to by the block to be processed;

an inter-frame prediction unit 1302, configured to determine a derived reference frame index according to the reference frame index when the index identifier is a first value; based on the distance between the reference frame indicated by the reference frame index and the current frame where the block to be processed is located and the distance between the derived reference frame indicated by the derived reference frame index and the current frame, scaling the motion vector of the decoded block to obtain a derived motion vector of the candidate motion information; determining a pixel predictor of the block to be processed based on the candidate motion information, the derived reference frame index, and the derived motion vector.

In one possible implementation, the pixel predictor of the block to be processed is equal to a sum of a first weight and a second weight, the first weight being equal to a pixel predictor of the block to be processed determined based only on the candidate motion information multiplied by a first weight, the second weight being equal to a pixel predictor of the block to be processed determined based on the derived motion vector and the derived reference frame index multiplied by a second weight, the sum of the first weight and the second weight being equal to 1.

In one possible implementation, the first weight is equal to the second weight.

In a possible implementation manner, the inter-frame prediction unit 1302 is further configured to:

when the index identifier is a second numerical value, determining a pixel prediction value of the image to be processed based on the candidate motion information only.

In one possible implementation, the derived motion vector is obtained according to the following formula:

MV′＝(d0′/d0)MV；

In a possible implementation manner, when determining the derived reference frame index according to the reference frame index, the inter-frame prediction unit 1302 is specifically configured to:

It should be noted that the entropy decoding unit 1301 and the inter prediction unit 1302 may be applied to a coding and decoding and/or an inter prediction process at a decoding end.

Exemplarily, at the decoding end, in fig. 13, the position of the entropy decoding unit 1301 corresponds to the position of the entropy decoding unit 304 in fig. 3, in other words, the function of the entropy decoding unit 1301 can be performed by the entropy decoding unit 304 in fig. 3. The location of the inter prediction unit 1302 corresponds to the location of the inter prediction unit 344 in fig. 3, in other words, the function of the inter prediction unit 1302 may be performed by the inter prediction unit 344 in fig. 3.

Based on the same inventive concept as the method embodiment, the embodiment of the present application further provides an apparatus, as shown in fig. 14, the apparatus 1400 may specifically be a processor, a chip or a chip system in a video encoder, or a module in the video encoder, such as the inter-frame prediction unit 244.

Illustratively, the apparatus may include an obtaining unit 1401, a determining unit 1402. An obtaining unit 1401, a determining unit 1402 executes the method steps shown in the embodiment corresponding to fig. 10.

The embodiment of the present application also provides another structure of the apparatus for a decoder, as shown in fig. 15, a communication interface 1510 and a processor 1520 may be included in an apparatus 1500. Optionally, the apparatus 1500 may further include a memory 1530. The memory 1530 may be provided inside the device or may be provided outside the device.

For example, the apparatus 1500 may be applied to a decoding side, and the entropy decoding unit 1301 and the inter prediction unit 1302 shown in fig. 13 may be implemented by the processor 1520. The processor 1520 sends or receives a video stream or a codestream through the communication interface 1510 and is configured to implement the method described in fig. 12. In implementation, the steps of the process flow may be implemented by instructions in the form of hardware integrated logic circuits or software in the processor 1520 to implement the method described in fig. 12.

For example, the apparatus 1500 may also be applied to the encoding side, and the obtaining unit 1401 and the determining unit 1402 described in fig. 14 may be implemented by the processor 1520. The processor 1520 sends or receives a video stream or a codestream through the communication interface 1510 and is configured to implement the method described in fig. 12. In implementation, the steps of the process flow may be implemented by instructions in the form of hardware integrated logic circuits or software in the processor 1520 to implement the method described in fig. 10.

In the illustrated embodiment, the communication interface 1510 may be a circuit, a bus, a transceiver, or any other device that can be used for information interaction. Illustratively, the other apparatus may be a device coupled to the apparatus 1500, for example, when the apparatus is a video decoder, the other apparatus may be a video encoder.

The processor 1520 in the embodiments of the present application may be a general purpose processor, a digital signal processor, an application specific integrated circuit, a field programmable gate array or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof, and may implement or perform the methods, steps, and logic blocks disclosed in the embodiments of the present application. A general purpose processor may be a microprocessor or any conventional processor or the like. The steps of a method disclosed in connection with the embodiments of the present application may be directly implemented by a hardware processor, or may be implemented by a combination of hardware and software elements in a processor. Program code executed by the processor 1520 to implement the above-described methods may be stored in the memory 1530. The memory 1530 and the processor 1520 are coupled.

The coupling in the embodiments of the present application is an indirect coupling or a communication connection between devices, units or modules, and may be an electrical, mechanical or other form for information interaction between the devices, units or modules.

The processor 1520 may operate in conjunction with the memory 1530. The memory 1530 may be a non-volatile memory, such as a hard disk (HDD) or a solid-state drive (SSD), and may also be a volatile memory, such as a random-access memory (RAM). The memory 1530 is any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer, but is not limited to such.

The specific connection medium between the communication interface 1510, the processor 1520 and the memory 1530 is not limited in this embodiment. In the embodiment of the present application, the memory 1530, the processor 1520, and the communication interface 1510 are connected by a bus in fig. 15, the bus is represented by a thick line in fig. 15, and the connection manner between other components is merely illustrative and not limited. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one thick line is shown in FIG. 15, but this is not intended to represent only one bus or type of bus.

Based on the above embodiments, the present application further provides a computer storage medium, where a software program is stored, and the software program can implement the method provided by any one or more of the above embodiments when read and executed by one or more processors. The computer storage medium may include: u disk, removable hard disk, read only memory, random access memory, magnetic or optical disk, etc. for storing program codes.

Based on the above embodiments, the present application further provides a chip, where the chip includes a processor, and is configured to implement the functions related to any one or more of the above embodiments, such as obtaining or processing information or messages related to the above methods. Optionally, the chip further comprises a memory for the processor to execute the necessary program instructions and data. The chip may be formed of a chip, or may include a chip and other discrete devices.

Those of skill in the art will appreciate that the functions described in connection with the various illustrative logical blocks, modules, and algorithm steps described in the disclosure herein may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions described in the various illustrative logical blocks, modules, and steps may be stored on or transmitted over as one or more instructions or code on a computer-readable medium and executed by a hardware-based processing unit. Computer-readable media may include computer-readable storage media, which corresponds to tangible media, such as data storage media, or communication media including any medium that facilitates transfer of a computer program from one place to another (e.g., according to a communication protocol). In this manner, a computer-readable medium may generally correspond to (1) a tangible computer-readable storage medium that is not transitory, or (2) a communication medium, such as a signal or carrier wave. A data storage medium may be any available medium that can be accessed by one or more computers or one or more processors to retrieve instructions, code and/or data structures for implementing the techniques described herein. The computer program product may include a computer-readable medium.

By way of example, and not limitation, such computer-readable storage media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, flash memory, or any other medium that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer. Also, any connection is properly termed a computer-readable medium. For example, if the instructions are transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. It should be understood, however, that the computer-readable storage media and data storage media do not include connections, carrier waves, signals, or other transitory media, but are instead directed to non-transitory tangible storage media. Disk and disc, as used herein, includes Compact Disc (CD), laser disc, optical disc, digital Versatile Disc (DVD), and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

The instructions may be executed by one or more processors, such as one or more Digital Signal Processors (DSPs), general purpose microprocessors, application Specific Integrated Circuits (ASICs), field programmable logic arrays (FPGAs), or other equivalent integrated or discrete logic circuitry. Thus, the term "processor," as used herein may refer to any of the foregoing structure or any other structure suitable for implementation of the techniques described herein. Additionally, in some aspects, the functions described by the various illustrative logical blocks, modules, and steps described herein may be provided within dedicated hardware and/or software modules configured for encoding and decoding, or incorporated in a combined codec. Also, the techniques may be fully implemented in one or more circuits or logic elements.

The techniques of this application may be implemented in a wide variety of devices or apparatuses, including a wireless handset, an Integrated Circuit (IC), or a set of ICs (e.g., a chipset). Various components, modules, or units are described herein to emphasize functional aspects of means for performing the disclosed techniques, but do not necessarily require realization by different hardware units. Indeed, as described above, the various units may be combined in a codec hardware unit, in conjunction with suitable software and/or firmware, or provided by an interoperating hardware unit (including one or more processors as described above).

In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

The above description is only an exemplary embodiment of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present application are intended to be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A method for video image prediction, comprising:

analyzing candidate motion information and an index identifier from a code stream, wherein the candidate motion information comprises a reference frame index and a candidate motion vector identifier of a block to be processed, a coding structure of an image where the block to be processed is located is a P frame, and the motion vector identifier is used for indicating a motion vector of a decoded block referred by the block to be processed; the candidate motion information belongs to one of a Historical Motion Vector Prediction (HMVP) queue;

when the index mark is a first value, determining a derived reference frame index according to the reference frame index;

based on the distance between the reference frame indicated by the reference frame index and the current frame where the block to be processed is located and the distance between the derived reference frame indicated by the derived reference frame index and the current frame, performing scaling processing on the motion vector of the decoded block to obtain a derived motion vector of the candidate motion information;

determining a pixel predictor of the block to be processed based on the candidate motion information, the derived reference frame index, and the derived motion vector.

2. The method of claim 1, wherein a pixel predictor of the block to be processed is equal to a sum of a first weight value and a second weight value, the first weight value being equal to a pixel predictor of the block to be processed determined based only on the candidate motion information multiplied by a first weight value, the second weight value being equal to a pixel predictor of the block to be processed determined based on the derived motion vector and the derived reference frame index multiplied by a second weight value, the sum of the first weight value and the second weight value being equal to 1.

3. The method of claim 2, in which the first weight is equal to the second weight.

4. The method of any of claims 1-3, further comprising:

when the index identifier is a second value, determining a pixel prediction value of the block to be processed based only on the candidate motion information.

5. A method according to any one of claims 1 to 3, wherein the derived motion vector is obtained according to the formula:

MV′＝(d0′/d0)MV；

6. A method according to any of claims 1-3, wherein determining a derived reference frame index from the reference frame indices comprises:

7. A video image prediction apparatus, comprising:

the entropy decoding unit is used for analyzing candidate motion information and index identification from a code stream, wherein the candidate motion information comprises a reference frame index and candidate motion vector identification of a block to be processed, a coding structure of an image where the block to be processed is located is a P frame, and the motion vector identification is used for indicating a motion vector of a decoded block referred by the block to be processed; the candidate motion information belongs to one of a Historical Motion Vector Prediction (HMVP) queue;

8. The apparatus of claim 7, wherein a pixel predictor of the block to be processed is equal to a sum of a first weight value and a second weight value, the first weight value being equal to a pixel predictor of the block to be processed determined based only on the candidate motion information multiplied by a first weight value, the second weight value being equal to a pixel predictor of the block to be processed determined based on the derived motion vector and the derived reference frame index multiplied by a second weight value, the sum of the first weight value and the second weight value being equal to 1.

9. The apparatus of claim 8, in which the first weight is equal to the second weight.

10. The apparatus of any of claims 7-9, wherein the inter prediction unit is further to:

11. The apparatus of any of claims 7-9, wherein the derived motion vector is obtained according to the following equation:

MV′＝(d0′/d0)MV；

12. The apparatus according to any of the claims 7-9, wherein the inter prediction unit, when determining a derived reference frame index from the reference frame indices, is specifically configured to:

13. A video encoding/decoding apparatus, comprising: a non-volatile memory and a processor coupled to each other, the processor calling program code stored in the memory to perform the method as described in any one of claims 1-6.