CN111107020A - Method for time synchronization of multi-core Ethernet switching chip - Google Patents
Method for time synchronization of multi-core Ethernet switching chip Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/10—Packet switching elements characterised by the switching fabric construction
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/10—Packet switching elements characterised by the switching fabric construction
- H04L49/109—Integrated on microchip, e.g. switch-on-chip
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/35—Switches specially adapted for specific applications
- H04L49/351—Switches specially adapted for specific applications for local area network [LAN], e.g. Ethernet switches
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Abstract
The invention discloses a method for time synchronization of a multi-core Ethernet switch chip, which completes the calibration between two cores by adding a set of self-synchronization mechanism on free counters of the two cores, solves the interoperation problem of the two cores on one package, and ensures that the switch chip designed by the scheme has no difference with the behavior of a single-core chip when supporting a time synchronization protocol.
Description
Technical Field
The invention belongs to the technical field of multi-core Ethernet switch chip time synchronization, and particularly relates to a method for time synchronization of a multi-core Ethernet switch chip.
Background
With the development of super-large scale cloud networks, storage networks, HPC (high performance computing) and other scenes, the data exchange volume on the network is larger and larger, and the highest single-chip processing capacity is continuously increased, and the level of Gbps is increased to the level of Tbps. However, in the current chip production process, the clock frequency at which the IP core (Intellectual Property core) can operate is up to 1.05GHz or 1.7GHz respectively at 14nm/12nm or 7nm/6 nm. Processing power up to 25.6Tbps cannot be supported on the premise of a single pipeline core.
From an engineering perspective, in order to cope with a rapidly rising message processing bandwidth, a multi-core design becomes a necessary direction in a case where a single core frequency is limited. From the application perspective, the system behavior exhibited by the chip during operation should not be aware of whether the chip architecture is a single-core or multi-core design. Therefore, state synchronization among a plurality of cores is necessary. On the other hand, Tape out (Tape out) costs are becoming higher and higher as chip production processes advance. To enrich the product line, both high bandwidth and ultra-high bandwidth switch chips need to be designed. Therefore, by using D2D (Die-to-Die) technology, a single stream can be realized to cover multiple product lines on the premise of dual core design: the ultra-high bandwidth single chip is packaged by using two Die (bare Die) connections; the high bandwidth chip uses a Die package.
And the ultra-high bandwidth Ethernet switching chip supports double Die (bare Die) interconnection packaging, and the two dice are symmetrical. That is, if only one Die is packaged, it can independently operate as a high bandwidth ethernet switch chip. For the time synchronization characteristic, a free counter is arranged on each Die to express the number of ticks passed after the Die is powered on. If the reference clock of this one free counter is 500MHz, then the counter increments by 2 every Tick, and 1 second can get a count of 1,000,000,000. In other words, the counter represents a real elapsed time of 1 second every 1,000,000,000. After the initialization is completed, because both the Dies have counters, the time for releasing the reset signals of the counters is not consistent, and therefore, even though the two counters can use the same reference clock, the counter values on the two Dies still have differences.
Therefore, in order to solve the above technical problems, it is necessary to provide a method and an apparatus for time synchronization of a multi-core ethernet switch chip.
Disclosure of Invention
In view of the above, the present invention is directed to a method for time synchronization of a multicore ethernet switch chip.
In order to achieve the above object, an embodiment of the present invention provides the following technical solutions:
a method of multi-core ethernet switch chip time synchronization, the method comprising:
s1, when the first core releases the reset signal, the counter of the first core self-increases under the drive of the reference clock, and simultaneously the first core sends a synchronizable message to the second core in each period;
s2, when the second core releases the reset signal, the counter of the second core keeps unchanged until it receives the synchronizable message sent by the first core for the first time, it starts to increase itself, and replies the synchronization request message to the first core in each period;
s3, when the first core receives the first synchronization request message, it stops sending the synchronizable message and records the current first counter value, and sends a synchronization end message to the second core;
s4, after receiving the synchronization end message, the second core replies the synchronization end message to the first core and positions itself as completion;
and S5, when the first core receives the synchronization end message, recording the current value of the second counter, calculating and adjusting the value of the second counter, and setting the second counter to be finished after adjustment.
In one embodiment, before S1, the first core and the second core are configured to be in a master operation mode and a slave operation mode, respectively.
In one embodiment, in S1, the first core sends a synchronizable message to the second core through a communication interface between the two cores.
In one embodiment, in S5, the first core performing the calculation adjustment on the second counter value includes:
s51, the first core subtracts the first time when the synchronization end message is received in S5 from the second time when the first synchronization request message is received in S3, and records the calculated time difference;
s52, subtracting the sum of the second time and the time difference/2 from the second counter value.
In one embodiment, the first core and the second core are driven using the same reference clock.
In one embodiment, the method further comprises: and when the first core and the second core finish signal setting, adding the value of a counter of the first core and the offset value configured by the CPU, and stamping the time synchronization protocol message by using the calculated time.
In one embodiment, the CPU configures the offset values in the first core and the second core simultaneously.
In one embodiment, the number of bits of the synchronizable message, the synchronization request message and the synchronization end message is 2 bits.
In an embodiment, the time synchronization protocol packet is a PTP packet.
The invention has the following beneficial effects: a set of self-synchronization mechanism is added on a free counter of the two cores to finish the calibration between the two cores, so that the problem of interoperation of the two cores on one package is solved, and the behavior of the switching chip designed by the scheme is not different from that of a single-core chip when a time synchronization protocol is supported.
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In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a schematic flow chart of the present invention.
Detailed Description
In order to make those skilled in the art better understand the technical solution of the present invention, the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the drawings in the embodiment of the present invention, and it is obvious that the described embodiment is only a part of the embodiment of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention discloses a method for synchronizing the time of a multi-core Ethernet switching chip, which realizes the synchronization between two cores by adding a set of self-synchronizing mechanism on free counters of the two cores.
As shown in fig. 1, a method for time synchronization of a multi-core ethernet switch chip disclosed in the present invention includes:
in a first step, a first core and a second core are configured to a master mode of operation and a slave mode of operation, respectively.
Specifically, for convenience of description, the first core is defined as core 0, and the second core is defined as core 1, that is, in this embodiment, core 0 is configured as the master operation mode, and core 1 is configured as the slave operation mode, but in other embodiments, core 1 may be configured as the master operation mode and core 0 may be configured as the slave operation mode instead.
In the second step, when the first core releases the reset signal, the counter of the first core is self-increased under the driving of the reference clock, and simultaneously the first core sends a synchronizable message to the second core in each period.
Specifically, in the present embodiment, when core 0 releases the reset signal, the counter of core 0 starts to self-increment under the drive of the reference clock. Meanwhile, the core 0 sends a synchronizable (SyncEligible) message to the core 1 through the inter-core communication interface every period under the drive of the reference clock, in this embodiment, the synchronizable message only needs 2 bits, and the set value is 0x 1.
And thirdly, when the second core releases the reset signal, the counter of the second core is kept unchanged until the synchronizable message sent by the first core is received for the first time, the counter starts to increase automatically, and a synchronization request message is replied to the first core in each period.
Specifically, in this embodiment, when core 1 releases the reset signal, the counter of core 1 remains unchanged until it starts to self-increment when it first receives a synchronizable message sent by core 0. And replies a synchronization request (SyncAck) message to the core 0 in each period, in this embodiment, the SyncAck message also only needs 2 bits and is set to 0x 2.
And fourthly, after the first core receives the first synchronization request message, stopping sending the synchronizable message and recording the current first counter value, and simultaneously sending a synchronization end message to the second core.
Specifically, in this embodiment, after receiving the first SyncAck message, the core 0 stops sending the synchronizable message and records the value of the current counter, and sends a synchronization end (SyncFin) message to the core 1. In this embodiment, the SyncFin message also only needs 2 bits, and the setting value is 0x 3.
And fifthly, after receiving the synchronization end message, the second core replies the synchronization end message to the first core, and the positioning is finished.
Specifically, in this embodiment, after receiving the SyncFin message, the core 1 directly replies the SyncFin message to the core 0, and sets itself as DONE (DONE).
And sixthly, when the first core receives the synchronization end message, recording the current value of a second counter, calculating and adjusting the value of the second counter, and setting the second counter to be finished after adjustment.
Specifically, in this embodiment, when the core 0 receives the SyncFin message, the current counter value is recorded. And subtracting the first time T1 of receiving the SyncFin message from the second time T2 of receiving the first SyncAck message to obtain deltaT, recording the deltaT, subtracting the value of the counter (T2+ deltaT/2), and setting the counter to be finished after adjustment. At this point the two cores are finished synchronously.
Preferably, the two cores (i.e., the first core and the second core) are driven using the same reference clock, so that the free time values (i.e., the counter values) on both sides do not deviate again.
Further, when each core completes signal setting, adding the free counter value of the core to the Offset value configured by the CPU to obtain a value, which is the current Time after calibration, and using the Time to perform a stamping process on a Time synchronization Protocol message (such as a PTP message, where PTP english is fully called Precision Time Protocol and chinese is interpreted as Precision Time Protocol message). Since the CPU will configure the Offset in both cores simultaneously, the time values at both locations remain consistent although the two cores are no longer interacting. The two cores act externally at the same time in a consistent and undifferentiated single system time.
According to the technical scheme, the invention has the following advantages: the method solves the problem of interoperation of two cores on one package, so that the switching chip designed by the method has no difference with the single-core chip in behavior when supporting the time synchronization protocol.
The systems, devices, modules or units illustrated in the above embodiments may be implemented by a computer chip or an entity, or by a product with certain functions.
For convenience of description, the above devices are described as being divided into various modules by functions, and are described separately. Of course, the functionality of the modules may be implemented in the same one or more software and/or hardware implementations in implementing one or more embodiments of the present description.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
As will be appreciated by one skilled in the art, embodiments of one or more embodiments of the present description may be provided as a method, system, or computer program product. Accordingly, one or more embodiments of the present description may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, one or more embodiments of the present description may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
One or more embodiments of the present description may be described in the general context of computer-executable instructions, such as program modules, being executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types. One or more embodiments of the specification may also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules may be located in both local and remote computer storage media including memory storage devices.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.
Claims (9)
1. A method for time synchronization of a multi-core Ethernet switch chip, the method comprising:
s1, when the first core releases the reset signal, the counter of the first core self-increases under the drive of the reference clock, and simultaneously the first core sends a synchronizable message to the second core in each period;
s2, when the second core releases the reset signal, the counter of the second core keeps unchanged until it receives the synchronizable message sent by the first core for the first time, it starts to increase itself, and replies the synchronization request message to the first core in each period;
s3, when the first core receives the first synchronization request message, it stops sending the synchronizable message and records the current first counter value, and sends a synchronization end message to the second core;
s4, after receiving the synchronization end message, the second core replies the synchronization end message to the first core and positions itself as completion;
and S5, when the first core receives the synchronization end message, recording the current value of the second counter, calculating and adjusting the value of the second counter, and setting the second counter to be finished after adjustment.
2. The method for time synchronization of multi-core ethernet switching chips of claim 1, wherein prior to S1, the first core and the second core are configured to a master mode of operation and a slave mode of operation, respectively.
3. The method for time synchronization of multi-core Ethernet switching chips of claim 1, wherein in S1, the first core sends a synchronizable message to the second core through a communication interface between the two cores.
4. The method for time synchronization of multicore ethernet switching chips of claim 1, wherein in S5, the performing, by the first core, a calculation adjustment on the second counter value comprises:
s51, the first core subtracts the first time when the synchronization end message is received in S5 from the second time when the first synchronization request message is received in S3, and records the calculated time difference;
s52, subtracting the sum of the second time and the time difference/2 from the second counter value.
5. The method of multi-core ethernet switching chip time synchronization of claim 1, wherein the first core and the second core are driven using the same reference clock.
6. The method of multi-core ethernet switching chip time synchronization according to claim 1, further comprising: and when the first core and the second core finish signal setting, adding the value of a counter of the first core and the offset value configured by the CPU, and stamping the time synchronization protocol message by using the calculated time.
7. The method of multi-core Ethernet switch chip time synchronization of claim 6, wherein the CPU configures the offset values in the first core and the second core simultaneously.
8. The method of multi-core ethernet switching chip time synchronization of claim 1, wherein the bit number of said synchronizable message, synchronization request message and synchronization end message is 2 bits.
9. The method according to claim 6, wherein the time synchronization protocol packet is a PTP packet.
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