CN111028133B - Graphic command pre-decoding device based on SystemVerilog - Google Patents
Graphic command pre-decoding device based on SystemVerilog Download PDFInfo
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- CN111028133B CN111028133B CN201911147511.5A CN201911147511A CN111028133B CN 111028133 B CN111028133 B CN 111028133B CN 201911147511 A CN201911147511 A CN 201911147511A CN 111028133 B CN111028133 B CN 111028133B
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Abstract
The invention belongs to the field of computer graphics, and particularly relates to a graphic command pre-decoding device based on a SystemVerilog dynamic array and task, which comprises the following components: the system comprises a preparation task block, a command analysis task block, a drawing class command processing task block, a parameter configuration class command processing task block, a display list writing task block and a display list reading task block. In the working process of the device, the data and the output result of the operation are dynamic arrays of SystemVerilog, and the task preparation and the task reading and writing of the display list also realize the interaction with the file, so that the data comparison and inspection in the verification process are facilitated. The processing process does not contain time sequence, the processing task of various commands stores the results into the corresponding dynamic array, the process is clear, the maintenance is convenient, and the simulation speed is greatly improved.
Description
Technical Field
The invention belongs to the field of computer graphics, and particularly relates to a graphic command pre-decoding device based on a SystemVerilog dynamic array and task.
Background
In the field of computer graphics, openGL graphics commands are various, and OpenGL programs written by software personnel need to be preprocessed according to a defined command format before entering a processing flow of a GPU, and a preprocessing unit is a key circuit for preprocessing operations. Because the pre-decoding unit at least comprises two data sources and a plurality of processing issuing paths, when the pre-decoding unit is verified, the problem of verification correctness is firstly encountered, and a model for comparing design output is required, and a specific construction scheme for the model is not available in the prior art.
Disclosure of Invention
Aiming at the problems in the background technology, the invention provides a graphic command pre-decoding device based on a SystemVerilog dynamic array and task, which realizes a model of graphic command pre-decoding and simplifies the establishment of a pre-decoding circuit verification platform.
The technical proposal of the invention is as follows:
a graphics command pre-decoding device based on a SystemVerilog dynamic array and task, the device comprising: the system comprises a preparation task block, a command analysis task block, a drawing class command processing task block, a parameter configuration class command processing task block, a display list writing task block and a display list reading task block.
Further, the command analysis task block is used for analyzing the data in the command array in the preparation task block, distinguishing the processing path of the command data, and calling the corresponding processing task block for processing.
Further, the preparation task block is configured to create a command array according to the length of the command file, and read the command in the file and store the command in the command array.
Further, the drawing class command processing task block is used for assembling corresponding data of the command array in the preparation task block according to a specified format when the drawing class command processing task block is called by the command analysis task block, and storing the data into the drawing command array.
Further, the parameter configuration class command processing task block is configured to intercept a required portion of corresponding data of the command array in the preparation task block according to a specified format and store the required portion in the parameter configuration array when the parameter configuration class command processing task block is called by the command analysis task block.
Further, the display list command processing task block is configured to store corresponding data of the command array in the preparation task block into the display list array when the display list command processing task block is called by the command parsing task block.
Further, the display list writing task block is configured to write corresponding data of the command array in the preparation task block to a corresponding position of the display list file when the display list writing task block is called by the display list command processing task block, where the position is determined by the writing list address parsed by the command parsing task block.
Further, the display list reading task is configured to read, when the display list reading task is called by the display list command processing task block, data stored in a corresponding position of the display list file according to the resolved address into a list data array, and call the command resolving task block.
The invention has the advantages that: the invention provides a graphic command pre-decoding device based on SystemVerilog, which greatly facilitates the construction of a pre-decoding unit verification platform; the invention adopts the SystemVerilog dynamic array as a data source and processed output, designs a plurality of parallel task processing paths to simulate the working process of the pre-decoding unit circuit, and performs acquisition optimization on data input, so that each piece of command data input into the device can be checked in a method, the processing results can be checked and compared one by one, and the verification work is convenient to perform.
Drawings
FIG. 1 is a block diagram of the method of the present invention.
Wherein: 1. preparing a task block; 2. a command parsing task block; 3. a drawing class command processing task block; 4. the parameter configuration class command processes the task block; 5. displaying list command processing task blocks; 6. displaying a list writing task block; 7. displaying a list reading task block; 8. the list file is displayed.
Detailed Description
The present invention will be further described in detail with reference to the following examples in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific examples described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
The technical scheme of the invention is further described in detail below with reference to the attached drawings and specific embodiments.
In one embodiment of the present invention, a graphics command pre-decoding device based on a SystemVerilog dynamic array and task is provided, wherein the device comprises: a preparation task block 1, a command analysis task block 2, a drawing class command processing task block 3, a parameter configuration class command processing task block 4, a display list command processing task block 5, a display list writing task block 6, and a display list reading task block 7.
In one embodiment, the command parsing task block 2 is configured to parse the data in the command array in the preparation task block 1, distinguish the processing paths of the command data, and call the corresponding processing task blocks for processing.
In one embodiment, the preparation task block 1 is configured to create a command array according to the length of the command file, and read the command in the file and store the command in the command array.
In one embodiment, the drawing class command processing task block 3 is configured to assemble corresponding data of the command array in the preparation task block 1 according to a specified format and store the data in the drawing command array when the drawing class command processing task block is called by the command parsing task block 2.
In one embodiment, the parameter configuration class command processing task block 4 is configured to intercept the corresponding data of the command array in the preparation task block 1 according to a specified format and store the intercepted data in the parameter configuration array when the intercepted data is called by the command parsing task block 2.
In one embodiment, the display list command processing task block 5 is configured to store corresponding data of the command array in the preparation task block 1 into the display list array when the display list command processing task block is called by the command parsing task block 2.
In one embodiment, the display list writing task block 6 is configured to write, when called by the display list command processing task block 5, corresponding data of the command array in the preparing task block 1 to a corresponding location of the display list file 8, where the location is determined by the write list address parsed by the command parsing task block 2.
In one embodiment, the display list reading task is configured to read, when the display list reading task is called by the display list command processing task block 5, data stored in a corresponding location of the display list file 8 into the list data array according to the parsed address, and call the command parsing task block 2.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (1)
1. A graphics command pre-decoding device based on a SystemVerilog dynamic array and task, the device comprising: a preparation task block (1), a command analysis task block (2), a drawing type command processing task block (3), a parameter configuration type command processing task block (4), a display list command processing task block (5), a display list writing task block (6) and a display list reading task block (7);
the command analysis task block (2) is used for analyzing the data in the command array in the preparation task block (1), distinguishing a processing path of the command data, and calling a corresponding processing task block for processing;
the preparation task block (1) is used for creating a command array according to the length of the graphic command file, and reading the graphic command in the file and storing the graphic command into the command array;
the drawing type command processing task block (3) is used for assembling corresponding data of the command array in the preparation task block (1) according to a specified format and storing the corresponding data into the drawing command array when the drawing type command processing task block is called by the command analysis task block (2);
the parameter configuration class command processing task block (4) is used for intercepting a required part of corresponding data of a command array in the preparation task block (1) according to a specified format and storing the required part into the parameter configuration array when the parameter configuration class command processing task block is called by the command analysis task block (2);
the display list command processing task block (5) is used for storing corresponding data of a command array in the preparation task block (1) into a display list array when the display list command processing task block is called by the command analysis task block (2);
the display list writing task block (6) is used for writing corresponding data of a command array in the preparation task block (1) into a corresponding position of a display list file (8) when the display list writing task block is called by the display list command processing task block (5), and the position is determined by a writing list address analyzed by the command analysis task block (2);
and the display list reading task is used for reading the data stored in the corresponding position of the display list file (8) into a list data array according to the analyzed address when the display list reading task is called by the display list command processing task block (5), and calling the command analysis task block (2).
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101068364A (en) * | 2006-06-16 | 2007-11-07 | 威盛电子股份有限公司 | Video encoder and graph processing unit |
| CN103971391A (en) * | 2013-02-01 | 2014-08-06 | 腾讯科技（深圳）有限公司 | Animation method and device |
| CN105260223A (en) * | 2015-10-27 | 2016-01-20 | 中国电子科技集团公司第四十一研究所 | Method for defining, analyzing, executing and testing SCPI (standard commands for programmable instruments) |
| CN105843590A (en) * | 2016-04-08 | 2016-08-10 | 深圳航天科技创新研究院 | Parallel pre-decoding method and system for instruction sets |
| CN106708472A (en) * | 2016-12-12 | 2017-05-24 | 中国航空工业集团公司西安航空计算技术研究所 | Non-blocking graph command processing method |
| CN107958438A (en) * | 2017-12-06 | 2018-04-24 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of OpenGL creates display listing circuitry |
| CN108230222A (en) * | 2017-12-06 | 2018-06-29 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of OpenGL shows list call circuit |
| CN108520489A (en) * | 2018-04-12 | 2018-09-11 | 长沙景美集成电路设计有限公司 | It is a kind of in GPU to realize that command analysis and vertex obtain parallel device and method |
-
2019
- 2019-11-21 CN CN201911147511.5A patent/CN111028133B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101068364A (en) * | 2006-06-16 | 2007-11-07 | 威盛电子股份有限公司 | Video encoder and graph processing unit |
| CN103971391A (en) * | 2013-02-01 | 2014-08-06 | 腾讯科技（深圳）有限公司 | Animation method and device |
| CN105260223A (en) * | 2015-10-27 | 2016-01-20 | 中国电子科技集团公司第四十一研究所 | Method for defining, analyzing, executing and testing SCPI (standard commands for programmable instruments) |
| CN105843590A (en) * | 2016-04-08 | 2016-08-10 | 深圳航天科技创新研究院 | Parallel pre-decoding method and system for instruction sets |
| CN106708472A (en) * | 2016-12-12 | 2017-05-24 | 中国航空工业集团公司西安航空计算技术研究所 | Non-blocking graph command processing method |
| CN107958438A (en) * | 2017-12-06 | 2018-04-24 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of OpenGL creates display listing circuitry |
| CN108230222A (en) * | 2017-12-06 | 2018-06-29 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of OpenGL shows list call circuit |
| CN108520489A (en) * | 2018-04-12 | 2018-09-11 | 长沙景美集成电路设计有限公司 | It is a kind of in GPU to realize that command analysis and vertex obtain parallel device and method |
Non-Patent Citations (3)
| Title |
|---|
| 田泽;张淑;张骏;许宏杰;黎小玉;郭蒙.图形处理器片段处理单元的设计与实现.计算机应用.2014,(S2),全文. * |
| 陈质冉;张晓林.高速SRAM编译器的设计.电子测量技术.2007,(01),全文. * |
| 韩可;邓中亮;施乐宁.(2,1,7)卷积码Viterbi译码器FPGA实现方案.现代电子技术.2007,(15),全文. * |
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