CN110800113A - Embedded electric power rail - Google Patents

Embedded electric power rail Download PDF

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Publication number
CN110800113A
CN110800113A CN201880041590.9A CN201880041590A CN110800113A CN 110800113 A CN110800113 A CN 110800113A CN 201880041590 A CN201880041590 A CN 201880041590A CN 110800113 A CN110800113 A CN 110800113A
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China
Prior art keywords
power rail
semiconductor device
isolation trench
power
forming
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CN201880041590.9A
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Chinese (zh)
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CN110800113B (en
Inventor
杰弗里·史密斯
安东·J·德维利耶
坎达巴拉·N·塔皮利
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Tokyo Electron Ltd
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Tokyo Electron Ltd
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Abstract

Aspects of the present disclosure provide a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a power rail formed in an isolation trench. The power rail is covered by a dielectric capping layer that isolates the power rail from conductive pattern structures on the dielectric capping layer. Further, openings are selectively formed in the dielectric capping layer and filled with a conductive material to selectively connect conductive pattern structures with the power rail.

Description

Embedded electric power rail
Priority claims and cross-referencing
The present disclosure claims the benefit of U.S. provisional application No.62/523,704, filed on 22.6.2017, which is incorporated herein by reference in its entirety, for a Method for self-aligned Buried Power rail and device under-Wiring (Method to self-aligned Buried Power Rails and Below-device Wiring for Random and Non-Random Logic Applications and Designs).
Technical Field
The present disclosure describes embodiments generally relating to semiconductor devices and manufacturing processes.
Background
The present disclosure relates to methods of manufacturing semiconductor devices, such as integrated circuits and transistors and transistor components for integrated circuits. In the manufacture of semiconductor devices, particularly on a microscopic scale, various manufacturing processes are performed, such as film formation deposition, etching mask formation, patterning, material etching and removal, and doping processes are repeatedly performed to form desired semiconductor device elements on a substrate. Historically, with microfabrication, transistors with wiring/metallization formed above have been formed in one plane and characterized as two-dimensional (2D) circuits or 2D fabrication. Scaling efforts have greatly increased the number of transistors per unit area in 2D circuits, but scaling efforts are caught in greater challenges because of scaling into single-digit nano-semiconductor device fabrication nodes.
Disclosure of Invention
The invention relates to device fabrication incorporating both random and non-random logic of fin field effect transistors (FINFETs), nanowires, nanoplates, or complementary stacked nanowires and/or nanoplates. Within a standard logic cell, power to a device (e.g., a transistor) is supplied to source/drain contacts through power rails in a back-end of line (BEOL) metal layer. The power track typically extends across adjacent units in an orientation commonly referred to as an east-west orientation. Because the power rails must supply power to many cells, the power rails are often implemented to have much larger sizes (e.g., larger widths) than the standard routing rails/signal lines used within the cells. Typically, the size difference of the power rails compared to typical wiring lines can be up to 3 to 4 times, so the power rails utilize a considerable area within the cell design. A large critical dimension of the power rail is required in order to maintain sufficient resistance in the rail in order to maintain sufficient power distribution targets, including the IR drop and frequency of the power rail that needs to be supplied within the device.
A method has been devised to reduce the lateral (width) size of the power rail by making it deeper in size (e.g., higher aspect ratio) in order to allow for a smaller top-down cross section (e.g., smaller width metal lines) while effectively keeping the total metal volume in the power rail the same or increasing. The increase in aspect ratio provides lower resistance on the power rails, thus providing the ability to maintain improved IR drop and frequency of the power rails that need to be supplied. It is often difficult to increase only the aspect ratio of the power rails in the BEOL because this would create larger aspect ratio vias to connect signal lines to devices (e.g., higher via resistance), or would require signal lines to also have similar aspect ratios, which would result in increased capacitance between the rails in the BEOL. One approach includes "burying" or positioning the power rails under physical devices (e.g., transistors), where the aspect ratio of the power rails can be increased independently of the signal lines in the BEOL, which provides a way to significantly reduce the resistance in the power rails without any negative impact on the via resistance or capacitance in the BEOL. In this method, power is supplied to the metal contacts by a bottom-up method as opposed to by a conventional pull-down method.
Embedding power rails under physical devices allows for a reduction in cell footprint. For example, cells are typically implemented as fixed height, variable width cells in a standard cell layout library. The fixed height enables the cells to be placed in rows and facilitates the process of automated layout design. The row direction is an orientation referred to as an east-west orientation, and a direction perpendicular to the east-west orientation is referred to as a north-south orientation. According to this naming convention, M0 will typically contain liners extending in an east-west orientation, while M1 will have liners extending in a north-south orientation. Subsequent metal layers may extend perpendicularly with respect to the previous metal layer.
Embedding the power rails under the physical device allows the cell height of a standard cell to be defined only by the number of wiring rails or signal lines, as opposed to a combination of power and wiring rails. This provides the ability to easily scale the 6.0 to 6.5 routing track (6.5T) cell height (assuming the power track width is equal to 2 or 3 times the width of the routing track line) to 5.0 routing track cell height by incorporating this concept, even if the number of actual routing tracks is the same.
The connection of adjacent cells to Vss or Vdd (in the north-south direction) can be made along a common power rail. In an example, a power rail (e.g., Vdd) is positioned below between an upper row of standard cells and a lower row of standard cells. The power rails extend in an east-west orientation. The cells in the upper row face towards the quilt and the cells in the lower row face towards the south, and the power rail can typically be used as, for example, a Vdd power supply. The power rails can be tapped by north facing cells in the upper row and can similarly be tapped by south facing cells in the lower row. For the case of large non-buried tracks, this can be taken into account because there is enough room on the track for making both connections, and those connections are made according to a top-down integration approach in which vias are transferred through the track to the underlying metal drain (e.g., a channel or tunnel for metallization). Accordingly, any alignment by lithography or patterning will be directly transferred by the etching process. However, with respect to the buried rail implementation, the power rail is either encapsulated within Shallow Trench Isolation (STI) or encapsulated within bulk silicon along with STI, depending on how large an aspect ratio is needed to meet the resistance specification. It is difficult to perform oxide fill down through the replacement metal drain to form connections and land on the metal track rather than on the STI physically adjacent to the track. Any placement error will result in additional metal filling of the tracks, since the next step of the process may be to metalize the metal drain after making the connection to the buried tracks. Conversely, any placement error with insufficient connection to the power rail provides significant resistance penalty, especially in designs where the connection between the rail and the metal drain is less than 12nm in size.
For the case where the two source/drain contacts from two adjacent cells in a north-south orientation are pulled down from a common power rail, the source/drain contacts or electrodes between the two standard cells can be shared in effect, which enables the placement of the via connections to be (a) increased in diameter in order to improve via resistance, and (b) placed anywhere within the width of the power rail, thus providing some edge-placement error (EPE) mitigation.
Several additional challenges arise from the integration of buried power rails under active devices. These issues are also affected by several factors, including the size of the tracks to be used, the location of the buried tracks to be implemented in the integration process sequence, the placement of the buried power tracks close to the silicon or SiGe fin structures (or Si/SiGe fin superlattices used in a nanosheet-all-around-Gate (GAA) process), the density and location of these track taps (within a single standard cell, and between two adjacent cells in a north-south orientation), the metal used for the buried tracks and any associated liners required for metallization of the tracks and subsequent connection of the tracks to the metal drain, and the size and location of thermal resistance in the integration when forming the buried power tracks.
Example embodiments herein are primarily directed to applications describing buried power rails. This application is not intended to be limiting. Embodiments herein can be extended to cover any backside wiring, such as wiring lines or local interconnects or cell-to-cell interconnects that exist below the physical device, as well as buried power distribution networks that supply power rails directly from the backside of the wafer.
Currently, there is no need to perform the method for self-aligning any wires on the bottom end of the physical device. Regardless of the wiring, such methods include buried power rails, buried word lines of the memory, buried interconnect lines, buried wiring lines, buried inter-cell wiring lines, etc.
In combination with other scaling concept implementations, such as complementary FET stacked nanosheet architectures, practicing multiple self-aligned methods as disclosed herein provides for a significant reduction in the cell height of a logic design from the current 6.5T to 5T or even lower, where a cell height of 4T or even 3T can be implemented with buried power rails. This also ultimately provides a mechanism to be able to stack the cells themselves on top of each other. In some examples, complementary stacked nanoplatelets (PMOS over NMOS) are disclosed. These stacked devices can be used with embodiments of buried backside wiring extending to multiple cell stacks in which placement or wiring and/or other wiring can be done under, between, and over physical devices, as is currently used for metallization.
Of course, for clarity, the order of discussion of the different steps as described herein has been provided. In general, the steps can be performed in any suitable order. Additionally, although each of the different features, techniques, configurations, etc. may be discussed in different places of this disclosure, it is intended that each of the concepts can be performed independently of each other or in combination with each other. Accordingly, the present invention may be embodied and inspected in a number of different ways.
Aspects of the present disclosure provide a semiconductor device. The semiconductor device includes a power rail formed in an isolation trench and optionally extending down into bulk silicon. The power rail is covered by a dielectric capping layer or a second deposition with STI oxide to isolate the power rail from high-k metal gates (HKMG), gate electrodes, and even source/drain electrodes. In addition, openings can be formed in the dielectric cap layer and filled with a conductive material to selectively connect the source/drain electrodes with the power rails.
Aspects of the present disclosure provide a method of manufacturing a semiconductor device. The method includes forming a power rail in the isolation trench and optionally extending down into the bulk silicon. Further, the method includes capping the power rail with a dielectric capping layer to isolate the power rail from a conductive pattern structure on the dielectric capping layer. Next, the method includes selectively forming openings in the dielectric capping layer, and filling the openings with a conductive material to selectively connect conductive pattern structures with the power rails via the filled openings. The dielectric capping material can be different from the surrounding STI oxide to provide some self-aligned method by selective deposition when forming via structures that connect the power rails to the source/drain electrodes. The deposition of this capping material can be performed by (a) a conventional filling, CMP and recessing process, or, more preferably, by (b) a selective deposition process in which the capping material is selectively deposited on the upper surface of the buried metal track.
Drawings
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawing figures. Note that the various features are not drawn to scale according to industry standard particles. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
Fig. 1 through 20 show various schematic views of intermediate stages during a semiconductor fabrication process, in accordance with some embodiments disclosed;
fig. 21-30 show various schematic views of intermediate stages for forming a buried power rail, in accordance with some embodiments disclosed; and
fig. 31-39 show various schematic views of intermediate stages for forming a buried power rail, according to some embodiments disclosed.
Detailed Description
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these specific examples are merely examples and are not intended to be limiting. For example, forming a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Furthermore, spatially relative terms, such as "below," "lower," "above," "upper," and the like, may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (selected 90 degrees or at other orientations) and the spatially relative descriptors described herein interpreted accordingly.
The disclosure herein provides a method of self-aligning buried power rails to be used for both random and non-random logic cells. The buried power rail has a plurality of locations for insertion into a given logic integration stream: (a) directly on bulk silicon for standard fin field effect transistor (FINFET) processes; (b) a SiGe epitaxial film directly over bulk silicon for a SiGe P-type metal oxide semiconductor (PMOS) channel process; (c) directly on the Si/SiGe multilayer stack for nanowire and/or nanosheet processing; or (d) after the FINFET or Si/SiGe fin stack has been patterned and filled with STI oxide.
Typically, dummy fin patterns are added to a uniform pattern density in the layout in order to create a uniform processing environment. During processing, for example, the dummy fin pattern is removed at a particular time to create a room or define a space for the space in which an isolation region will eventually be formed to separate the individual FinFET devices from one another. The dummy FIN pattern removal is referred to as FIN cut (FIN cut). Dummy fin pattern removal can occur prior to the fin etch process, for example by removing dummy patterns in a hard mask layer used to mask the fin etch, which is referred to as a CUT-first (CUT-first) method. Dummy fin pattern removal can occur in the middle of the fin etch process, which is referred to as the CUT-middle method. Dummy fin pattern removal can occur after fin formation, which is referred to as the CUT-last method. The final cutting method can improve process uniformity.
For the case of forming buried tracks for applications (a), (b), and (c), the tracks can be patterned and etched to a fixed distance prior to any patterning of Si, SiGe, or stacked Si/SiGe FIN. Thus, the full track depth will be transferred during the fin etch process, for example, in a manner similar to the dual damascene approach for back end of line (BEOL). This approach enables the fin etch process to be performed with either an intermediate cut or a first cut, and the last cut is not favored by semiconductor manufacturers as is currently the case due to advanced technology.
The fin final cutting method can distort the depth and shape of the buried track. Likewise, for the case of forming deep and narrow tracks important for maintaining resistance control, this approach can leave deep trenches adjacent to the patterned fins, with very limited space between the deep trenches, which can lead to some distortion in the size and/or shape of the physical power tracks, which can be equally problematic for electrical parameters. In addition, for the case of FINFET applications, after the power rail and adjacent FIN are formed, the bulk silicon can undergo many implantation steps and it will be difficult to control the implant properties in the regions that are the boundaries of the etched rails within the bulk silicon. These integration schemes are possible and have just been described, but there may be some limitations on implementation. For option (d) of patterning the buried tracks after fin etch and STI fill/CMP, this is a preferred implementation for incorporating buried power tracks.
In this embodiment, the buried tracks are patterned on top of the STI oxide and transferred through the STI oxide, stopping just within the depth of the STI oxide, or passing completely through the depth of the STI oxide and extending into the bulk silicon. The final depth of the power rails in the bulk silicon will depend on the desired aspect ratio of the buried rails and is typically defined by the choice of metal used and the required resistance of the buried power rails in order to meet power distribution network specifications such as IR drop, frequency of contacting the rails and supplying power to the rails, and design rule compliance for the frequency of supplying power to the rails, the effect of routing the upper metal layer based on this frequency, and its effect on area scaling in routing. For wide (1.5T to 4T wide tracks compared to the routing lines) power tracks, the aspect ratio of such trenches is about 2.5 to 5.0. Deep and narrow tracks, which may have additional benefits, will have an aspect ratio of at most 3 times, or 7.5 to 15.0. This etching process will produce very thin (<12nm) STI oxide that can reach as deep as the desired depth of the buried power rail within the STI. Challenges in transferring these narrow trenches within the oxide fill between fins include collapse margins and distortion of the spacing between buried power rails, which is of paramount importance for parasitics.
In some implementations, narrow buried tracks can be formed by a self-alignment process. For example, an initial trench sized 1.5T to 4T power rail is etched through the STI. After reaching the desired depth of the buried power rail, an etch selective film can be conformally deposited within the trench to form "spacers" on both sides of the trench. Such etch selective material can then be subjected to a general "spacer opening" etch to remove the conformal deposition at the bottom of the trench, leaving only the etch selective material along the sidewalls of the wide trench. An oxide or other dielectric liner and/or fill material may then be selected to fill the remaining portion of the trench, and then the oxide or other dielectric liner and/or fill material is planarized (e.g., by CMP) or subjected to a downward dry or wet recess to expose the "a/B" matrix, where a is the STI oxide or fill oxide and B is the etch selective material within the trench. A non-aggressive etch process can then be used to dig out the etch selective material "B" which will result in the formation of two identical trenches. The two trenches will be identical because they were initially formed by a single conformal deposition process. There are a number of low aggressive etch processes that place an oxide collapse between two adjacent narrow trenches. One such process is Chemical Oxide Removal (COR) vapor etching, which can achieve selectivity of up to one percent, as well as other quasi-Atomic Layer Etching (ALE) and wet and or dry etching.
After forming the self-aligned trenches to create the adjacent buried tracks, the power tracks may then be metallized.
The choice of metallization for the buried power rail affects where in the integration flow the rail is formed and metallized. For the case where the buried tracks are formed and metallized just before the tip anneal of the S/D epitaxy is performed, the metal must have excellent thermal properties on the oxide. For example, the metal should be able to be stable at tip anneal temperatures between 700C and 1100C and any deposition temperatures for thin films in metal gates. For embodiments where the buried track is placed before metal gate deposition and S/D tip anneal, this would preclude the use of metals such as copper (<450C thermal stability), cobalt or aluminum. In some embodiments, ruthenium can be selected for metallization of buried power rails at this point in the integration, provided that ruthenium has excellent thermal stability compared to oxide, and ruthenium can also be deposited into deep trenches using a bottom-up deposition process.
According to disclosed aspects, techniques herein include self-aligning a power rail bottom up to a metal drain by using an etch selective capping layer over recessed ruthenium (or any other metal). In some implementations, a capping layer is formed using a selective deposition process to deposit a dielectric on metal (DoM). For the case of ruthenium, the capping layer may be (a) dielectric and of sufficient size to be a true dielectric between the power rail and the metal drain located above the rail, or (b) or etch selective to the boundary STI oxide or dielectric liner, (c) dielectric between the power rail and any upper hanging gate electrode, and (d) the height of the dielectric capping layer will actually define the final placement of the HKMG and gate electrode relative to the top of the buried power rail, and this amount of deposition can be controlled in order to control the capacitance between the power rail and gate electrode. The etch selectivity property incorporated into the cap layer ensures that when the metal drain is opened, a self-aligned etch process can be used, wherein the cap layer can be opened without otherwise opening the STI oxide along the axis of the buried rail, since the physical separation between the buried power rail and any silicon or Si/SiGe fin structure must also be controlled. This also enables the entire metal drain to open the cap layer to the buried power rail, and the control tap has the same size as the size of the initial buried power rail trench, which is also equal to the size of the buried power rail itself minus the size of the additionally deposited liner within the trench. This allows full freedom in the use of the size of the metal drain, which is beneficial for devices with limited area-scale pin access.
For a detailed description of some embodiments herein, it is believed that metal filling will be performed after fin etching, followed by final STI filling, and then polishing down to the top of the fin structure. Although example embodiments focus on buried power rails, enabling the techniques herein to be extended to cover any backside wiring, such as wiring lines or local interconnects or cell-to-cell interconnect lines that exist underneath physical devices.
The example embodiments below illustrate a process flow for a complementary stacked nanoplatelet device (CFET). Note that the integration process flow is similar for use in fabricating FINFET, laterally stacked nanowire and/or nanosheet, and SiGe channel FINFET devices.
A semiconductor process using bottom-up self-alignment of power rails to metal drains by using an etch selective capping layer over recessed ruthenium is described with reference to fig. 1-14.
Fig. 1 illustrates a schematic view of a portion of a semiconductor device 100 during a semiconductor fabrication process, according to some embodiment schemes. In the fig. 1 example, the Si/SiGe fin etch has been completed and a liner oxide/SiN cap layer is left on top of the fin. In this particular case, the fin etch has been performed prior to the fin etch process. This means that the silicon under the STI is considered "flat" in the area between the fins. With the fin last cut method, the dummy fins are etched prior to this step, thus providing deep recesses in the silicon between the fins, which makes it more difficult to form buried power rails. Therefore, for incorporating buried power rails into this example integration, it is preferable to incorporate a fin-first cut or a fin-middle cut method for fin pattern definition. The following figures show example results.
Fig. 2 shows a schematic view of semiconductor device 100 after Shallow Trench Isolation (STI) by depositing oxide and CMP back to the top of the Si/SiGe fin structures.
Fig. 3 shows a schematic view of the semiconductor device 100 after a pattern for track trenches has been created in the photoresist layer. In the fig. 3 example, a multi-layer lithographic stack is used for pattern transfer. The multilayer lithographic stack includes a bottom layer of spin-on-carbon (SOC), an intermediate layer of silicon-containing anti-reflective coating (SiARC), and a top layer of photoresist. In one example, the pattern in the photoresist is first transferred to the middle layer SiARC and the bottom layer SOC. The pattern in the middle layer SiARC and bottom layer SOC is then transferred down to the STI oxide, for example by an orbital trench etch.
Fig. 4 shows a schematic view of the semiconductor device 100 after buried track trench etching. Note that the buried track trenches are patterned on top of the STI oxide and transferred through the STI oxide, for example, by etching. In one example, the pattern transfer stops completely within the depth of the STI oxide. In another example, the pattern transfer is etched completely through the depth of the STI oxide and extending into the bulk silicon. For the case of wide (1.5T to 4T wide tracks compared to routing lines) power tracks, the aspect ratio of this trench is about 2.5 to 5.0. The deep and narrow tracks can have an aspect ratio of at most 3 times, or 7.5 to 15.0. This etching process will produce very thin (<12nm) STI oxide that can reach as deep as the desired depth of the buried power rail within the STI. Challenges to transferring these narrow trenches within the oxide fill between fins include collapse redundancy and distortion of the spacing between the buried power rails. The following figures show example results.
In FINFET applications, the bulk silicon can be heavily doped and it is preferable to keep the rails completely within the STI. However, maintaining deep rails within the STI makes the initial height of the fin much larger than conventionally fabricated fins. Typically, for a FINFET, the fin dimensions extend around 75A, so in this example embodiment, the aspect ratio of the fin can be expanded beyond 15-1 and even close to 20-1. Since this is extremely aggressive and tends to result in distortion of the fin shape, it is preferable for some implementations to drive the buried tracks into the silicon. In one implementation, a narrow buried rail can be formed by a self-aligned process, where the initial trench is the size of the more general 1.5T to 4T power rail, although the initial trench is etched through the STI.
In implementations where the buried rail trenches extend down to the bulk silicon, the buried rails benefit from being physically isolated from the bulk silicon by conformal deposition of dielectric into the trenches after pattern transfer into the bulk silicon.
Fig. 5 shows a schematic view of the semiconductor device 100 after deposition of a linear, e.g. Atomic Layer Deposition (ALD) SiO liner.
After reaching the desired depth of the buried power rail, an etch selective film can be conformally deposited within the trench to form "spacers" on both sides of the trench. Such etch selective material can then be subjected to a general "spacer open" etch to remove the conformal deposition at the bottom of the trench, leaving only the etch selective material along the sidewalls of the wide trench.
In one implementation herein, narrow buried rails can also be formed by a self-aligned process, where the initial trench has the size of the more general 1.5T to 4T power rail, although the initial trench is etched through the STI. After reaching the desired depth of the buried power rail, an etch selective film can be conformally deposited within the trench to form "spacers" on both sides of the trench.
Fig. 6 shows a schematic view of the semiconductor device 100 after deposition of an etch selective thin film (e.g., an ALD sacrificial film).
Such etch selective material can then be subjected to a general "spacer opening" etch to remove the conformal deposition at the bottom of the trench, leaving only the etch selective material along the sidewalls of the wide trench. An oxide or other dielectric liner and/or fill material is then used to fill the remaining portion of the trench, and then the oxide or other dielectric liner and/or fill material is planarized (e.g., CMP) or subjected to a downward dry or wet recess to expose the "a/B" matrix, where a is the STI oxide or fill oxide and B is the etch selective material within the trench.
Fig. 7 shows a schematic view of the semiconductor device 100 after oxide fill.
Furthermore, a non-aggressive etching process can then be used to dig out the etch selective material "B", which will result in the formation of two identical trenches.
Fig. 8 shows a schematic view of the semiconductor device 100 after forming two identical trenches.
In one embodiment, the two trenches can be identical because the two trenches are initially formed by a single conformal deposition process. There are a number of low aggressive etch processes that place an oxide collapse between two adjacent narrow trenches. One such process is Chemical Oxide Removal (COR) vapor etching, which can achieve selectivity of up to one percent, as well as other quasi-Atomic Layer Etching (ALE) and wet and or dry etching. The following figures show example results.
Next, in an example, the bottom of the trench is filled with a metal and/or liner to be used for the buried power rail. The choice of metallization for buried power rails is based on where in the integration flow the rails are formed and metallized. For the case where the buried tracks are formed and metallized just prior to tip annealing for S/D epitaxy, the metal must have excellent thermal properties on oxide-specifically, the metal can be stable at tip anneal temperatures between 700C and 1100C and deposition temperatures for thin films in metal gates. For embodiments where the buried track is placed before metal gate deposition and S/D tip anneal, this would preclude the use of metals such as copper (<450C thermal stability), cobalt or aluminum. Ruthenium, however, can be chosen for metallization of the buried power rail at this point in the integration, provided that ruthenium has excellent thermal stability compared to oxide, and ruthenium can also be deposited into deep trenches using a bottom-up deposition process. However, if a metal such as ruthenium is used; this will turn the buried power rail into a narrow rail rather than a 1.5T to 4T sized rail due to the resistivity of ruthenium and its subsequent resistance. Since it may be more difficult to form connections to narrow power rails from the bottom up, in some implementations, the connections to the metal drains can be self-aligned. The following figures show example results.
Fig. 9 shows a schematic view of the semiconductor device 100 after filling the bottom of the trench with ruthenium. In one example, the trench and surface are filled with ruthenium and the ruthenium is etched back (recessed) to the bottom of the trench.
Techniques herein include self-aligning the power rail bottom up to the metal drain by using an etch selective capping layer over the recessed ruthenium (or any other metal). Note that when the power rails are formed by alternative methods, the metallization can be performed after the S/D tip anneal or during the actual metal drain metallization. For the case of ruthenium, the capping layer may be (a) dielectric and of sufficient size to be the actual dielectric between the power rail and the metal drain located above the rail, or (b) or etch selective to the boundary STI oxide or dielectric liner.
Fig. 10 shows a schematic view of the semiconductor device 100 after forming an etch selective capping layer over the recessed ruthenium.
The remaining portion of the buried rail trench is then filled with STI oxide or other dielectric, and then polished down to the top of the fin structure.
Fig. 11 shows a schematic view of the semiconductor device 100 after filling the STI oxide and performing a down-polish.
Next, an STI recess etch process can be performed to drop the STI to the top of the active fin or to the SiGe of this example for the complementary stacked nanosheets. The STI etch can stop at the top of the etch-selective dielectric cap layer above the buried power rail.
Fig. 12 shows a schematic view of semiconductor device 100 after an STI recess etch process.
Note that other optional embodiments can be used to metalize the buried power rail to achieve metal selection other than ruthenium or other selectively depositable metals. Another option to enable other metals to be incorporated into the buried power rail is to form a complete replacement metal rail, wherein instead of filling the rail with metal and capping with an etch selective dielectric, the trench is completely filled with dielectric and then recessed down to the desired height of the metalized buried rail during the buried rail trench definition process. During subsequent connection to the metal drain, the entire replacement track can be isotropically removed and then refilled with metal. It is beneficial for the buried power rail to extend non-discretely over and reach adjacent given cells. Having such continuous power track metal can be challenging. In such an embodiment, the entire replacement track is removed from the effective contact to the metal drain and points where no connection is required. When filling with metal, the filling in this case will be performed as a "subsurface" filling (rather than a simple top-down or bottom-up filling), where the metal extends along the length of the buried track extending under the metal drain, without requiring a connection to the track.
Continuing with the integration embodiment herein, where the rails are just metallized and capped with an etch selective dielectric cap, process flow continues after the S/D has been formed by tip anneal and subsequent replacement metal gate metallization. At this point in the integration flow, contact between the desired metal drain and the selected contact point to the power rail is achieved.
The exemplary implementation uses complementary FET stacked nanoplates as an example, the description focuses primarily on the tap from the metal drain to Vss, which is connected to most of the bottom of the two stacked electrodes (bottom NMOS and top PMOS).
At this point, the metal drain has not yet been metallized, and the metal drain is filled with oxide during metallization of the metal gate. At this point, the oxide within the metal drain is recessed down to the top of the etch-selective dielectric cap layer above the buried power rail (or the oxide can be removed entirely if there is an etch stop between the STI and the metal drain fill oxide). The etch selectivity properties incorporated into the capping layer ensure that when the metal drain is opened, a self-aligned etch process can be used, wherein the capping layer can be opened without otherwise opening the STI oxide along the axis of the buried rail. This also enables the entire metal drain to open the cap layer to the buried power rail, and always controls the tap to have the same size as the size of the initial buried power rail trench, which is also equal to the size of the buried power rail itself minus the size of the additionally deposited liner within the trench. This allows full freedom in the use of the size of the metal drain, which is beneficial for devices with limited area-scale pin access.
Fig. 13 shows a schematic view of the semiconductor device 100 after recessing the oxide within the metal drain down to the top of the etch selective dielectric cap.
The metal drain can be filled with oxide (if there is a stop layer between the oxide and the STI) or with some other material commonly referred to as a replacement contact. Replacement contacts generally have excellent selectivity for multiple films: (a) oxide in STI; (b) a dielectric cap layer protecting the buried rail; (c) a capping layer, which is typically some type of nitride, that protects the metal gate; and (d) a low-k gate spacer. The following figures show example results.
Fig. 14 shows a schematic view of the semiconductor device 100 after filling with replacement contacts.
The power tap to the power rail is imaged (patterned) and transferred down through the replacement contact. Since buried power rails can make the BEOL metal lines a series of dense wiring lines, the spacing between cells in the north-south orientation would only be 1/2 critical metal spacing, or approximately 12nm for cast N5 technology considerations. For a power tap formed by two adjacent cells to the same position along the power rail longitudinal axis, this means that it will be difficult to image discrete vias even with EUV multi-patterning. Self-alignment is beneficial to ensure that this condition does not cause shorting between adjacent cells. This is the case because the initial wide trenches are self-aligned patterned to form two identical narrow tracks. Thus, each "pair" of rails would correspond to Vdd or Vss, since the cells in the north-south orientation share the Vss or Vdd rail, this self-alignment approach not only provides resistance improvement, but also determines that two adjacent cells are not shorted.
Fig. 15 shows a schematic view of the semiconductor device 100 after imaging the power taps in, for example, the SiARC layer and the SOC layer from the photoresist layer.
In case a tap to the power rail is required, the etch selective cap layer above the power rail can be removed to achieve a metal drain contact.
Fig. 16 shows a schematic view of the semiconductor device 100 after removal of the etch selective cap layer.
The replacement contact material in the metal drain can then be removed.
Fig. 17 shows a schematic view of the semiconductor device 100 after removal of the replacement contact.
The metal drain can then be metallized, with connections to the desired tracks filled equally, while the unwanted connections are still blocked by the etch selective capping layer, which does not open during transfer of the tap through the metal drain.
Fig. 18 shows a schematic view of the semiconductor device 100 after drain metallization of the bottom electrode.
For the case of complementary stacked nanosheet FETs, metallization is required separately from the bottom electrode (NMOS) and the upper electrode (PMOS). Likewise, power taps to the Vss and Vdd rails occur for both sets of electrodes. In embodiments herein, separate metallizations may be performed using multiple metallization and etching steps or via selective deposition.
Fig. 19 shows a schematic view of the semiconductor device 100 after patterning the metallization of the bottom electrode and depositing an oxide layer.
Fig. 20 shows a schematic view of the semiconductor device 100 after drain metallization of the top electrode and deposition of an oxide layer.
Note that in the semiconductor device 100, each power rail includes two rail lines formed using an open spacer technique. The process can be modified to form a wide power track such as shown in fig. 21-30.
Fig. 21 illustrates a schematic view of a portion of a semiconductor device 200 during a semiconductor fabrication process, according to some embodiments. Fig. 21 is similar to fig. 1. In the fig. 21 example, the Si/SiGe fin etch has been completed and a liner oxide/SiN cap layer is left on top of the fin.
Fig. 22 shows a schematic view of the semiconductor device 200 after Shallow Trench Isolation (STI) by depositing oxide and CMP back to the top of the Si/SiGe fin structures. Fig. 22 is similar to fig. 2.
Fig. 23 shows a schematic view of the semiconductor device 200 after a pattern for the track trenches has been created in the photoresist layer. Fig. 23 is similar to fig. 3.
Fig. 24 shows a schematic view of the semiconductor device 200 when the pattern is transferred through the STI oxide, for example by etching.
Fig. 25 shows a schematic view of the semiconductor device 200 when the pattern is additionally transferred into the bulk silicon. In an example, a spacer layer is deposited prior to pattern transfer into silicon to aid in pattern transfer into silicon.
Fig. 26 shows a schematic view of the semiconductor device 200 after deposition of an etch selective film, such as a SiO/TaN liner.
Fig. 27 shows a schematic view of the semiconductor device 200 after ruthenium underfill.
Fig. 28 shows a schematic view of the semiconductor device 200 after ruthenium is etched back. The ruthenium is etched recessed in the track trenches to a specified depth. In addition, the TaN in the liner is removed.
Fig. 29 shows a schematic view of the semiconductor device 200 after forming an etch selective capping layer over the recessed ruthenium.
Fig. 30 shows a schematic view of the semiconductor device 200 after the STI oxide is filled and polished down.
Furthermore, similar processes described with reference to fig. 12-20 can be used to continue the manufacturing process with respect to the semiconductor device 200.
Note that the semiconductor devices 100 and 200 are 3D devices having stacked devices. The operations for fabricating the buried power rail can be integrated to achieve regular FINFETs that are not stacked. Fig. 31-39 show various schematic views of intermediate stages for forming buried power rails for FINFET devices, according to some embodiments disclosed.
Fig. 31 illustrates a schematic view of a portion of a semiconductor device 300 during a semiconductor fabrication process, according to some embodiments. In the fig. 31 example, the Si fin etch has been completed and a liner oxide/SiN cap layer is left on top of the fin.
Fig. 32 shows a schematic view of the semiconductor device 300 after Shallow Trench Isolation (STI) by depositing oxide and CMP back to the top of the Si/SiGe fin structures.
Fig. 33 shows a schematic view of the semiconductor device 300 when the pattern is transferred through the STI oxide, for example by etching.
Fig. 34 shows a schematic view of the semiconductor 300 after deposition of the spacer layer. The spacer layer can facilitate pattern transfer into the silicon by: (a) ensuring that any open silicon or SiGe fin structures are not etched during the transfer of the buried track trench pattern into the bulk silicon; and (b) ensuring a fixed and controllable distance between the last buried power rail and the silicon, SiGe or silicon/SiGe fin structure via atomic layer deposition.
Fig. 35 shows a schematic view of the semiconductor device 300 when the pattern is additionally transferred into bulk silicon.
Fig. 36 shows a schematic view of the semiconductor device 300 when an etch selective film such as a SiO/TaN liner is deposited and then ruthenium is filled from the bottom of the trench.
Fig. 37 shows a schematic view of the semiconductor device 300 after etching back ruthenium. The ruthenium is etched recessed in the track trenches to a specified depth. In addition, the TaN in the liner is removed.
Fig. 38 shows a schematic view of the semiconductor device 300 after forming an etch selective capping layer over the recessed ruthenium.
Fig. 39 shows a schematic view of the semiconductor device 300 after the wafer fabrication process.
As noted above, example embodiments herein are directed to the application of buried power rails. This is but one example embodiment, and the techniques herein can be extended to cover any backside wiring, such as wiring lines or local interconnects or cell-to-cell interconnect lines, that exist underneath physical devices or transistor devices.
In the previous description, specific details have been described, such as specific geometries of the processing systems and descriptions of various components and processes used herein. It should be understood, however, that the technology herein may be practiced in other embodiments that depart from these specific details, and that these details are for purposes of explanation rather than limitation. The embodiments disclosed herein have been described with reference to the accompanying drawings. Similarly, for purposes of explanation, specific numbers, materials, and configurations have been set forth in order to provide a thorough understanding. However, embodiments may be practiced without these specific details. Components having substantially the same functional configuration are denoted by like reference characters, and thus any redundant description may be omitted.
Various techniques have been described as multiple discrete operations to aid in understanding various embodiments. The order of description should not be construed as to imply that these operations are necessarily order dependent. Indeed, these operations need not be performed in the order of presentation. The operations described may be performed in an order different than the described embodiments. In additional embodiments, various additional operations may be performed and/or the described operations may be omitted.
As used herein, "substrate" or "target substrate" generally refers to an article that is processed in accordance with the invention. The substrate may comprise any material part or structure of a device, in particular a semiconductor device or other electronic device, and may be, for example, a base substrate structure, such as a semiconductor wafer, a reticle or a layer on or overlying a base substrate structure, such as a thin film. Thus, the substrate is not limited to any particular base structure, underlying layer, or overlying layer, patterned or unpatterned, but is intended to include any such layer or base structure, and any combination of layers and/or base structures. The description may refer to a particular type of substrate, but this is for illustration purposes only.
Those skilled in the art will also appreciate that many changes can be made in the operation of the above-explained techniques, while still accomplishing the same objects of the present invention. Such variations are intended to be covered by the scope of this disclosure. Thus, the foregoing description of embodiments of the invention is not intended to be limiting. Indeed, any limitations to embodiments of the invention are set forth in the claims.

Claims (22)

1. A semiconductor device, comprising:
a power rail formed in an isolation trench;
a dielectric cap layer on the power rail, the dielectric cap layer isolating the power rail from a conductive pattern structure on the dielectric cap layer; and
an opening selectively formed in the dielectric capping layer, the opening filled with a conductive material to selectively connect a conductive pattern structure with the power rail.
2. The semiconductor device of claim 1, wherein the power rail is formed within the isolation trench.
3. The semiconductor device of claim 1, wherein the power rail is formed through the isolation trench and into a bulk silicon substrate.
4. The semiconductor device of claim 1, wherein said dielectric cap layer is etch selective to a material forming said isolation trench to achieve self-alignment to create said opening in said dielectric cap layer.
5. The semiconductor device of claim 4, wherein the dielectric cap layer is a material having etch selectivity to the SiO liner between the power rail and the isolation trench and to the oxide in the isolation trench.
6. The semiconductor device of claim 4, wherein the dielectric cap layer is selectively deposited on the power rail.
7. The semiconductor device of claim 1, wherein the power rail is formed of a metallic material having a thermal stability in excess of 700.
8. The semiconductor device of claim 7, wherein the metal material is a refractive metal.
9. The semiconductor device according to claim 7, wherein the metal material comprises ruthenium.
10. The semiconductor device of claim 1, wherein an aspect ratio of the power rail is predetermined to meet a resistivity requirement of the power rail.
11. The semiconductor device of claim 10, wherein a critical dimension width of the power rail is predetermined in conjunction with the aspect ratio.
12. The semiconductor device of claim 8, wherein the power rail is formed by filling a rail opening with the refractive metal and etching back the refractive metal to a specific depth.
13. A method of manufacturing a semiconductor device, the method comprising:
forming a power track in the isolation trench;
capping the power rail with a dielectric capping layer that isolates the power rail from conductive pattern structures on the dielectric capping layer; and
selectively forming an opening in the dielectric cap layer;
filling the openings with a conductive material to selectively connect conductive pattern structures with the power rails via the filled openings.
14. The method of claim 13, wherein forming the power rail in the isolation trench further comprises:
etching a power rail trench within the isolation trench;
forming the power rail within the isolation trench.
15. The method of claim 13, wherein forming the power rail in the isolation trench further comprises:
etching a power rail trench through the isolation trench and into a bulk silicon substrate; and
forming the power rail in the isolation trench and the bulk silicon substrate.
16. The method of claim 13, wherein capping the power rail with the dielectric cap layer to isolate the power rail from the conductive pattern structure on the dielectric cap layer further comprises:
capping the power rail with the dielectric cap layer, the dielectric cap layer having an etch selectivity to a material forming the isolation trench to achieve self-alignment to create the opening in the dielectric cap layer.
17. The method of claim 16, wherein top capping the power rail with the dielectric cap layer having etch selectivity to a material forming the isolation trench further comprises:
selectively depositing a dielectric material as the dielectric capping layer, the dielectric material having an etch selectivity to the SiO liner between the power rail and the isolation trench.
18. The method of claim 13, wherein forming the power rail in the isolation trench further comprises:
the power rail is formed using a metallic material having a thermal stability exceeding 700 a.
19. The method of claim 17, wherein forming the power rail using the metallic material having the thermal stability in excess of 700 further comprises:
the power rail is formed using ruthenium.
20. The method of claim 17, wherein forming the power rail using ruthenium further comprises:
filling a track opening in the isolation trench with the ruthenium; and
the ruthenium is etched back to a specific depth.
21. The method device of claim 13, wherein forming the power rail in the isolation trench further comprises:
forming the power track comprising two track lines.
22. The method of claim 21, wherein forming the power track comprising the two track lines further comprises:
conformally depositing a spacer layer on sidewalls and a bottom of a track opening in the isolation trench;
filling the rail openings with a dielectric material;
removing the spacer layer formed on sidewalls of the rail opening to form two spacer trenches;
filling the two spacer trenches with ruthenium; and
the ruthenium is etched back to a specific depth.
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