CN110333616B - Display panel and display device - Google Patents
Display panel and display device Download PDFInfo
- Publication number
- CN110333616B CN110333616B CN201910359365.6A CN201910359365A CN110333616B CN 110333616 B CN110333616 B CN 110333616B CN 201910359365 A CN201910359365 A CN 201910359365A CN 110333616 B CN110333616 B CN 110333616B
- Authority
- CN
- China
- Prior art keywords
- potential line
- substrate
- display panel
- display
- electrode layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/133345—Insulating layers
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1339—Gaskets; Spacers; Sealing of cells
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Liquid Crystal (AREA)
Abstract
The invention discloses a display panel and a display device, which relate to the technical field of display and comprise a first substrate and a second substrate which are opposite; the first substrate comprises a first substrate, a first potential line, a second potential line and at least one third potential line, wherein the at least one third potential line is positioned on one side, facing the second substrate, of the first potential line and the second potential line, and the third potential line is isolated from the first potential line and the second potential line through a first insulating layer; in the non-display area on the same side of the display area, the first insulating layer comprises a first groove and a second groove; the first potential line receives a positive voltage, the second potential line receives a negative voltage, and the third potential line receives a reference voltage; the first electric field is formed by the first potential line and the third potential line in the first groove, and the second electric field is formed by the second potential line and the third potential line in the second groove; and the frame glue, wherein a first interval is formed between the edge of one side of the frame glue close to the display area and the display area. Therefore, the amount of impurity ions diffused from the frame glue to the display area is reduced.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a display panel and a display device.
Background
Liquid crystal displays, which are flat, ultra-thin display devices, consist of a certain number of color or black and white pixels placed in front of a light source or a reflective surface. Liquid crystal displays are very low power consuming and are therefore favored by engineers for use in battery-operated electronic devices.
The working principle of the liquid crystal display is as follows: the liquid crystal is a special substance between solid and liquid, which is an organic compound, normally in a liquid state, but its molecular arrangement is very regular as that of a solid crystal, and therefore, it is called a liquid crystal, and another special property thereof is that if an electric field is applied to the liquid crystal, its molecular arrangement is changed, and at this time if a polarizing plate is fitted thereto, it has a function of preventing light from passing therethrough (light can pass smoothly without applying an electric field), and if a color filter is fitted thereto, the magnitude of voltage applied to the liquid crystal is changed, so that the amount of light transmission of a certain color can be changed, and also it can be said that the transmittance thereof can be changed by changing the voltage applied to both ends of the liquid crystal.
Generally, a liquid crystal display includes two substrates disposed opposite to each other, and the two substrates are fixed by a sealant at a frame position, so that a sealed space for filling liquid crystal is formed between the two substrates. The narrow frame design is a development trend of the liquid crystal display, when the frame of the display is narrowed, the distance between the frame glue and the display area is reduced, the probability that impurity ions in the frame glue are diffused into the display area is higher, the impurity ions may affect the deflection of the liquid crystal, and thus the normal display of the display is affected.
Disclosure of Invention
In view of this, the present invention provides a display panel and a display device, in which a first electric field is formed in a first trench and a second electric field is formed in a second trench, so that impurity ions in a sealant are collected in the first trench and the second trench, thereby reducing the possibility that the impurity ions in the sealant are diffused into a display region, and facilitating to improve the display effect of the display panel and the display device.
In a first aspect, the present application provides a display panel comprising a display area and a non-display area surrounding the display area; the display panel further includes:
the first substrate and the second substrate are oppositely arranged;
the first substrate comprises a first substrate, a first potential line and a second potential line which are positioned on one side of the first substrate facing the second substrate, and at least one third potential line which is positioned on one side of the first potential line and the second potential line facing the second substrate, wherein the third potential line is isolated from the first potential line and the second potential line by a first insulating layer; in the non-display region on the same side of the display region, the first insulating layer includes a first cutout and a second cutout;
the first potential line receives a positive voltage, the second potential line receives a negative voltage, and the third potential line receives a reference voltage, the reference voltage being between the positive voltage and the negative voltage; the first potential line and the third potential line form a first electric field in the first groove, and the second potential line and the third potential line form a second electric field in the second groove;
and the frame glue is positioned in the non-display area and on one side of the third potential line facing the second substrate, and a first interval is formed between the edge of one side of the frame glue close to the display area and the display area.
In a second aspect, the present application provides a display device, including a display panel, where the display panel is any one of the display panels provided in the present application.
Compared with the prior art, the display panel and the display device provided by the invention at least realize the following beneficial effects:
in the display panel and the display device provided by the embodiment of the application, the non-display area includes a first potential line, a second potential line, and a third potential line located on one side, facing the second substrate, of the first potential line and the second potential line, the third potential line is isolated from the first potential line and the second potential line by a first insulating layer, particularly, the first insulating layer includes a first trench and a second trench, the first potential line and the third potential line form a first electric field in the first trench, the second potential line and the third potential line form a second electric field in the second trench, and under the action of the first electric field, impurity ions with negative charges in the sealant are gathered towards the first trench; under the effect of the second electric field, impurity ions with positive charges in the frame glue are gathered towards the second digging groove, so that the possibility of diffusion of the impurity ions in the frame glue to the display area is greatly reduced, the influence of the impurity ions on liquid crystal deflection in the display area is favorably reduced, and the display effect of the display panel and the display device is favorably improved.
Of course, it is not necessary for any product in which the present invention is practiced to achieve all of the above-described technical effects simultaneously.
Other features of the present invention and advantages thereof will become apparent from the following detailed description of exemplary embodiments thereof, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.
Fig. 1 is a top view of a display panel according to an embodiment of the present disclosure;
FIG. 2 is an AA cross-sectional view of the display panel provided in the embodiment of FIG. 1;
FIG. 3 is a BB cross-sectional view of the display panel provided in the embodiment of FIG. 1;
FIG. 4 is a schematic view showing an electric field direction of an electric field formed in a first trench and a second trench;
FIG. 5 is a cross-sectional view of another BB of the display panel of the embodiment of FIG. 1;
FIG. 6 is a cross-sectional view of another BB of the display panel of the embodiment of FIG. 1;
FIG. 7 is a cross-sectional view of another BB of the display panel of the embodiment of FIG. 1;
FIG. 8 is a cross-sectional view of another BB of the display panel of the embodiment of FIG. 1;
fig. 9 is a schematic diagram of a gate driving circuit according to an embodiment of the present disclosure;
FIG. 10 is a cross-sectional view of a first substrate of the display panel of FIG. 1, showing a cross-section CC;
FIG. 11 is a cross-sectional view of a first substrate of the display panel of FIG. 1, showing a cross-section CC;
FIG. 12 is a cross-sectional view of another BB of the display panel of the embodiment of FIG. 1;
FIG. 13 is a cross-sectional view of another BB of the display panel of the embodiment of FIG. 1;
fig. 14 is a schematic structural diagram of a display device according to an embodiment of the present disclosure.
Detailed Description
Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.
The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.
Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.
In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.
Generally, a liquid crystal display includes two substrates disposed opposite to each other, and the two substrates are fixed by a sealant at a frame position, so that a sealed space for filling liquid crystal is formed between the two substrates. The narrow frame design is a development trend of the liquid crystal display, when the frame of the display is narrowed, the distance between the frame glue and the display area is reduced, the probability that impurity ions in the frame glue are diffused into the display area is higher, the impurity ions may affect the deflection of the liquid crystal, and thus the normal display of the display is affected.
In view of this, the present invention provides a display panel and a display device, in which a first electric field is formed in a first trench and a second electric field is formed in a second trench, so that impurity ions in a sealant are collected in the first trench and the second trench, thereby reducing the possibility that the impurity ions in the sealant are diffused into a display region, and facilitating to improve the display effect of the display panel and the display device.
The following detailed description is to be read in connection with the drawings and the detailed description.
Fig. 1 is a top view of a display panel provided in an embodiment of the present invention, fig. 2 is an AA cross-sectional view of the display panel provided in the embodiment of fig. 1, fig. 3 is a BB cross-sectional view of the display panel provided in the embodiment of fig. 1, and with reference to fig. 1 to fig. 3, a display panel 100 provided in an embodiment of the present invention includes a display area 101 and a non-display area 102 surrounding the display area 101; the display panel 100 further includes:
a first substrate 10 and a second substrate 20 disposed opposite to each other;
the first substrate 10 includes a first substrate 11, a first potential line 31 and a second potential line 32 on a side of the first substrate 11 facing the second substrate 20, at least one third potential line 33 on a side of the first potential line 31 and the second potential line 32 facing the second substrate 20, the third potential line 33 being separated from the first potential line 31 and the second potential line 32 by a first insulating layer 40; in the non-display region 102 on the same side of the display region 101, the first insulating layer 40 includes a first cutout 41 and a second cutout 42;
the first potential line 31 receives a positive voltage, the second potential line 32 receives a negative voltage, and the third potential line 33 receives a reference voltage, which is between the positive voltage and the negative voltage; the first potential line 31 and the third potential line 33 form a first electric field in the first groove 41, and the second potential line 32 and the third potential line 33 form a second electric field in the second groove 42;
the sealant 30 is located in the non-display region 102 and on a side of the third potential line 33 facing the second substrate 20, and a first gap 111 is formed between an edge of the sealant 30 close to the display region 101 and the display region 101.
It should be noted that the first interval 11 refers to a shortest distance between an edge of the sealant 30 close to the display region 101 and an edge 19 of the display region; fig. 2 only schematically shows a relative position relationship between the first substrate 10, the second substrate 20 and the sealant 30, and does not represent actual dimensions; fig. 3 only schematically shows a relative positional relationship among the first potential line 31, the second potential line 32, the third potential line 33, and the sealant 30, and does not represent an actual size.
Specifically, referring to fig. 1 to 3, in the display panel 100 provided in the embodiment of the present application, the non-display area 102 includes the first potential line 31 and the second potential line 32, and the third potential line 33 located on the side of the first potential line 31 and the second potential line 32 facing the second substrate 20, the third potential line 33 is isolated from the first potential line 31 and the second potential line 32 by the first insulating layer 40, and particularly, the first insulating layer 40 includes the first trench 41 and the second trench 42, since the first potential line 31 receives a positive voltage and the third potential line 33 receives a reference voltage, the first potential line 31 and the third potential line 33 form a first electric field in the first trench 41, and the direction of the first electric field is directed from the first potential line 31 to the third potential line 33; since the second potential line 32 receives the negative voltage and the third potential line receives the reference voltage, the second potential line 32 and the third potential line 33 form a second electric field in the second slot 42, and the direction of the second electric field is directed from the third potential line 33 to the second potential line 32, as shown in fig. 4, fig. 4 is a schematic view of the direction of the electric field formed in the first slot 41 and the second slot 42, under the action of the first electric field, the negatively charged impurity ions in the sealant 30 will move toward the positively charged first potential line 31 and gather in the first slot 41; under the action of the second electric field, the positively charged impurity ions in the sealant 30 will move toward the negatively charged second potential line 32 and gather in the second trench 42, so that most of the impurity ions in the sealant 30 will gather in the first trench 41 and the second trench 42, thereby greatly reducing the possibility of diffusion of the impurity ions in the sealant 30 into the display region 101, and being beneficial to reducing the influence of the impurity ions on the liquid crystal deflection in the display region 101, and thus being beneficial to improving the display effect of the display panel 100.
Alternatively, please refer to fig. 1 and fig. 5, fig. 5 is another BB cross-sectional view of the display panel 100 provided in the embodiment of fig. 1, in the display panel 100 provided in the embodiment of the present application, the second slot 42 is located between the first slot 41 and the display area 101; the orthographic projection of the frame glue 30 on the plane of the first substrate 11 at least overlaps with a part of the first grooves 41. It should be noted that, besides the structures shown in fig. 3 and fig. 5, in some other embodiments of the present application, the first trench 41 may also be located between the second trench 42 and the display area 101, for example, please refer to fig. 6, which is not particularly limited in this application, wherein fig. 6 is another BB cross-sectional view of the display panel provided in the embodiment of fig. 1. In addition, the orthographic projection of the sealant 30 on the plane of the first substrate 11 in fig. 6 overlaps with the first recessed groove 41 and the second recessed groove 42, respectively, in some other embodiments of the present application, the orthographic projection of the sealant 30 on the plane of the first substrate 101 may also overlap with only at least a part of the first recessed groove 41 and the second recessed groove 42, or overlap with neither the first recessed groove 41 nor the second recessed groove 42, which is not specifically limited in the present application.
The positional relationship between the sealant 30 and the second groove 42 and the first groove 41 will be described below by taking a structure in which the second groove 42 is located between the first groove 41 and the display region 101 as an example.
Specifically, in the embodiment shown in fig. 5, the orthographic projection of the sealant 30 on the plane of the first substrate 11 overlaps with the first cutout 41, and does not overlap with the second cutout 42, and the second cutout 42 is located in the first space 111 formed by the sealant 30 and the display region 101, so that the distance between the negatively charged impurity ions in the sealant 30 and the first cutout 41 is favorably reduced, so that the negatively charged impurity ions in the sealant 30 can be rapidly collected in the first cutout 41. In addition, the positively charged impurity ions in the sealant 30 will be collected in the second trench 42 due to the action of the second electric field in the second trench 42, and since the second trench 42 is located in the first space 111 and the first trench 41 is located on the side of the second trench 42 away from the display region 101, most of the impurity ions in the sealant 30 will be collected in the first trench 41 and the second trench 42 due to the action of the electric field before being diffused to the display region 101, so that the possibility of the impurity ions in the sealant 30 diffusing to the display region 101 is greatly reduced, and the display effect of the display panel 100 is improved. In addition, as shown in fig. 5, since the second trench 42 is closer to the display region than the first trench 41, when the orthographic projection of the sealant 30 on the plane of the first substrate 11 is not overlapped with the second trench 42, the distance between the sealant 30 and the display region is increased, which is equivalent to increasing the diffusion distance of the impurity ions to the display region, and also is beneficial to reducing the possibility that the impurity ions in the sealant 30 diffuse into the display region, and further is beneficial to reducing the influence of the impurity ions on the liquid crystal deflection in the display region 101, thereby being beneficial to improving the display effect of the display panel 100.
Optionally, with continued reference to fig. 3, the orthographic projection of the sealant 30 on the plane of the first substrate 11 is overlapped with the first trench 41 and the second trench 42, which is favorable for reducing the distance between the sealant 30 and the display region 101, that is, the width of the first interval 111, so as to realize the narrow frame design of the display panel 100, and meanwhile, because the sealant 30 is overlapped with the first trench 41 and the second trench 42, under the action of the first electric field and the second electric field, the impurity ions in the sealant 30 will be rapidly collected into the first trench 41 and the second trench 42, so that the design structure is favorable for reducing the possibility that the impurity ions in the sealant 30 are diffused into the display region 101 while realizing the narrow frame of the display panel 100.
Alternatively, fig. 7 shows another BB cross-sectional view of the display panel 100 provided in the embodiment of fig. 1, wherein an orthographic projection of the first trench 41 and the second trench 42 on the plane of the first substrate 11 is located in the first space 111.
Specifically, with reference to fig. 7, in the display panel 100 provided in the embodiment of the present disclosure, the orthographic projection of the sealant 30 on the plane of the first substrate 11 is not overlapped with the first trench 41 and the second trench 42, so that the orthographic projection of the first trench 41 and the second trench 42 on the plane of the first substrate 11 is located in the first interval 111, and thus, the design is equivalent to introducing the first electric field and the second electric field in the first interval 111 between the sealant 30 and the display region 101, and the adsorption effect of the first electric field and the second electric field on the impurity ions in the sealant 30 is equivalent to blocking the diffusion path of the impurity ions into the display region 101, so that the possibility of the impurity ions in the sealant 30 diffusing into the display region 101 is greatly reduced, thereby reducing the influence of the impurity ions on the liquid crystal deflection, and thus being also beneficial to improving the display effect of the display panel 100.
Optionally, fig. 8 is another BB cross-sectional view of the display panel 100 provided in the embodiment of fig. 1, in which a front projection of the sealant 30 on the plane of the first substrate 11 overlaps at least a portion of the third potential line 33.
Specifically, in some other embodiments of the present application, for example, in fig. 8, a front projection of the sealant 30 on the plane of the first substrate 11 overlaps at least a portion of the third potential line 33, and since the third potential line 33 forms an electric field with the first potential line 31 and the second potential line 32, when the sealant 30 directly contacts the third potential line 33, the impurity ions in the sealant 30 can sensitively sense the acting force of the electric field, so that the diffusion speed of the impurity ions in the sealant 30 to the first trench 41 and the second trench 42 is advantageously increased, and the impurity ions in the sealant 30 can be gathered in the first trench 41 and the second trench 42, which is also advantageous for reducing the possibility of the impurity ions in the sealant 30 diffusing into the display region 101. Of course, the orthographic projection of the sealant 30 on the plane of the first substrate 11 can also overlap all the third potential lines 33, for example, as shown in fig. 3, which is more favorable for increasing the diffusion speed of the impurity ions in the sealant 30 to the first trenches 41 and the second trenches 42. In addition, referring to fig. 8, when the orthographic projection of the sealant 30 on the plane of the first substrate 11 is not overlapped with the first trench 41 and the second trench 42, the design is favorable for further increasing the distance between the sealant 30 and the display region, which is equivalent to further increasing the diffusion distance of the impurity ions to the display region, so as to further reduce the possibility that the impurity ions in the sealant 30 diffuse into the display region, and further reduce the influence of the impurity ions on the liquid crystal deflection in the display region 101, thereby being favorable for improving the display effect of the display panel 100.
Optionally, referring to fig. 1, fig. 8 and fig. 9, fig. 9 is a schematic diagram of a gate driving circuit provided in an embodiment of the present disclosure, in a display panel 100 provided in an embodiment of the present disclosure, the first substrate 10 further includes a gate driving circuit located in the non-display region 102, the gate driving circuit includes a high-level signal line 51 and a low-level signal line 52, the first potential line 31 is electrically connected to the high-level signal line 51, and the second potential line 32 is electrically connected to the low-level signal line 52.
Specifically, referring to fig. 9, the gate driving circuit generally includes a plurality of cascaded gate driving units 71, and further includes a high-level signal line 51 and a low-level signal line 52 led out from a driving chip 103, fig. 9 only schematically shows a connection relationship between the gate driving unit 71 and one of the high-level signal line 51 or the low-level signal line 52, and does not represent an actual size or number, a signal input end In of each gate driving unit 71 is electrically connected to the high-level signal line 51 or the low-level signal line 52, the driving chip 103 provides the high-level signal or the low-level signal to the gate driving unit 71 through the high-level signal line 51 and the low-level signal line 52, the high-level signal line 51 receives a fixed high-level signal, and the low-level signal line 52 receives a fixed low-level signal; the first signal output terminal OUT1 of each gate driving unit 71 is electrically connected to a pixel unit row in the display region 101, and the second signal output terminal OUT2 of the gate driving unit 71 is connected to the next stage of the gate driving unit 71 as a shift signal output terminal.
With reference to fig. 1, 8 and 9, when the first potential line 31 is electrically connected to the high-level signal line 51, the first potential line 31 and the high-level signal line 51 are at the same potential, that is, the first potential line 31 obtains the high-level signal, so that the first potential line 31 and the third potential line 33 form a first electric field in the first trench 41. Similarly, in the present embodiment, when the second potential line 32 is electrically connected to the low-level signal line 52, the second potential line 32 receives a low-level signal, so that the second potential line 32 and the third potential line 33 form a second electric field in the second trench 42. Alternatively, the first potential line 31 and the third potential line 33, and the second potential line 32 and the third potential line 33 are electrically connected by punching, respectively, so that it is not necessary to provide a special lead wire for the first potential line 31 and the second potential line 32 to connect to a control chip to obtain a corresponding level signal, and it is sufficient to obtain the high level signal and the low level signal on the high level signal line 51 and the low level signal line 52 by punching directly, which is also beneficial to simplifying the wiring process of the display panel 100 and improving the production efficiency of the display panel 100.
Optionally, fig. 10 is a CC cross-sectional view of the first substrate 10 in the display panel 100 provided in the embodiment of fig. 1, please refer to fig. 10, where the first substrate 10 further includes a gate metal layer 12, a source/drain metal layer 13, a touch metal layer 14 and an electrode layer 70, which are sequentially disposed on one side of the first substrate 11 facing the second substrate 20;
the high-level signal line 51 and the low-level signal line 52 are provided in the same layer as at least one of the gate metal layer 12 and the source-drain metal layer 13;
the first potential line 31 and the second potential line 32 are disposed on the same layer as the touch metal layer 14.
Specifically, referring to fig. 10, in the display panel 100 provided in the embodiment of the present application, when the high-level signal line 51 and the low-level signal line 52 are disposed on the same layer as at least one of the gate metal layer 12 and the source drain metal layer 13, there is no need to separately dispose a special film structure for the high-level signal line 51 and the low-level signal line 52, and when the first potential line 31 and the second potential line 32 are disposed on the same layer as the touch metal layer 14, there is no need to separately dispose a special film structure for the first potential line 31 and the second potential line 32, which is favorable for simplifying the film structure of the display panel 100 and improving the production efficiency of the display panel 100.
Alternatively, with reference to fig. 10, the electrode layer 70 includes a common electrode layer 71 and a pixel electrode layer 72, the pixel electrode layer 72 is located on a side of the common electrode layer 71 facing the second substrate 20, and the third potential line 33 and the pixel electrode layer 72 are disposed in the same layer.
Specifically, in the embodiment shown in fig. 10, the pixel electrode layer 72 is disposed on a side of the common electrode layer 71 facing the second substrate 20, and in the non-display region 102, when the third potential line 33 and the pixel electrode layer 72 are disposed on the same layer, the third potential line 33 can directly contact the sealant 30, so that the impurity ions in the sealant 30 can be more sensitively influenced by the electric field formed by the third potential line 33 and the first potential line 31 or the second potential line 32, which is more beneficial to the accumulation of the impurity ions in the sealant 30 in the first trench 41 and the second trench 42, and is more beneficial to reducing the possibility of the impurity ions in the sealant 30 diffusing into the display region 101. Note that, in general, the drain electrode 28 on the source/drain metal layer 13 is generally electrically connected to the pixel electrode layer 72, and supplies a pixel voltage to the pixel electrode layer 72; since the common electrode layer 71 receives the common voltage, the pixel voltage and the common voltage cooperate to form a deflection voltage for driving the liquid crystal to deflect, so that the liquid crystal is deflected, and the display panel 100 can realize a display function.
Alternatively, in the display panel 100 provided in this embodiment of the application, in the non-display region 102, the third potential line 33 is electrically connected to the common electrode layer 71 through a via hole. Since the third potential line 33 receives the reference voltage, when the third potential line 33 is electrically connected to the common electrode layer 71, the third potential line 33 is equipotential to the common electrode layer 71, and the common voltage is used as the reference voltage of the third potential line 33, so that it is not necessary to provide a dedicated lead for the third potential line 33 to be connected to a control chip to obtain a corresponding reference voltage signal, and the third potential line is connected to the common electrode layer 71 through a via hole, which is beneficial to simplifying the wiring process of the display panel 100 and improving the production efficiency of the display panel 100.
Alternatively, fig. 11 is a cross-sectional view of a CC' of the first substrate 10 in the display panel 100 provided in the embodiment of fig. 1, please refer to fig. 11, in which the electrode layer 70 includes a common electrode layer 71 and a pixel electrode layer 72, the common electrode layer 71 is located on a side of the pixel electrode layer 72 facing the second substrate 20, and the third potential line 33 is disposed in the same layer as the common electrode layer 71 and receives a common voltage.
Specifically, referring to fig. 11, the pixel electrode layer 72 is located on a side of the common electrode layer 71 close to the first substrate 11, and the common electrode layer 71 is closer to the second substrate 20, in the non-display region 102, when the third potential line 33 and the common electrode layer 71 are disposed on the same layer, the third potential line 33 can directly contact the sealant 30, so that the impurity ions in the sealant 30 can be more sensitively influenced by the electric field formed by the third potential line 33 and the first potential line 31 or the second potential line 32, which is more beneficial to the accumulation of the impurity ions in the sealant 30 in the first trench 41 and the second trench 42, and is more beneficial to reducing the possibility that the impurity ions in the sealant 30 diffuse into the display region 101.
When the third potential line 33 is provided on the same layer as the common electrode layer 71, the common voltage can be directly used as the reference voltage required for the third potential line 33 because the third potential line 33 is equal to the common electrode layer 71.
Alternatively, with continued reference to fig. 3, in the non-display area 102 on the same side of the display area 101, the first substrate 10 includes three third potential lines 33, which are a third potential line 331, a third potential line 332 and a third potential line 333, respectively; the orthographic projection of the first groove 41 on the plane of the first substrate 11 is positioned between the third potential line 331 and the third potential line 332, and the orthographic projection of the second groove 42 on the plane of the first substrate 11 is positioned between the third potential line 332 and the third tripropyl potential line 333.
Specifically, referring to fig. 3, when three third potential lines 33 are disposed in the non-display area 102 on the same side of the display area 101, the first potential line 31 can form a first electric field in the first trench 41 with the third and the third potential lines 331 and 332, respectively, and when two third potential lines 33 form a first electric field with the first potential line 31 at the same time, the electric field strength of the first electric field is increased, so that the first electric field can apply a stronger acting force to the negatively charged impurity ions in the sealant 30, which is beneficial to increasing the number of the negatively charged impurity ions collected in the first trench 41, further reducing the number of the negatively charged impurity ions diffused from the sealant 30 to the display area 101, and further improving the display effect of the display panel 100. Similarly, the second potential line 32 can form a second electric field in the second trench 42 with the third potential line 332 and the third tripropyl potential line 333, and when the two third potential lines 33 form a second electric field with the second potential line 32 at the same time, the electric field strength of the second electric field is increased, so that the second electric field can apply a stronger acting force to the positively charged impurity ions in the sealant 30, thereby increasing the number of the positively charged impurity ions collected in the second trench 42, further reducing the number of the positively charged impurity ions diffused from the sealant 30 to the display area 101, and also facilitating further improving the display effect of the display panel 100.
Alternatively, with continued reference to fig. 3, an orthogonal projection of the third potential line 331 on the plane of the first substrate 11 overlaps the first potential line 31, an orthogonal projection of the third potential line 332 on the plane of the first substrate 11 overlaps at least one of the first potential line 31 and the second potential line 32, and an orthogonal projection of the third potential line 333 on the plane of the first substrate 11 overlaps the second potential line 32.
Specifically, with continued reference to fig. 3, when the orthographic projections of the third potential line 331 and the first potential line 31 on the plane of the first substrate 11 are designed to overlap, the intensity of the first electric field formed by the third potential line 331 and the first potential line 31 in the first trench 41 can be made larger, so that the acting force of the first electric field on the negatively charged impurity ions in the sealant 30 is made stronger; when the orthographic projection of the third tripropyl potential line 333 on the plane of the first substrate 11 overlaps with the second potential line 32, the intensity of a second electric field formed by the third tripropyl potential line 333 and the second potential line 32 in the second groove 42 can be made larger, so that the acting force of the second electric field on the positively charged impurity ions in the sealant 30 is made stronger. In addition, if the third potential line 332 and the first potential line 31 are overlapped in the orthographic projection design of the plane where the first substrate 11 is located, the electric field intensity of the first electric field can be further enhanced; if the third potential line 332 and the second potential line 32 are overlapped in the orthographic projection design of the plane where the first substrate 11 is located, the electric field intensity of the second electric field can be further enhanced; when the electric field intensity of the first electric field and the second electric field is increased, more impurity ions can be gathered in the first trench 41 and the second trench 42, and the amount of the impurity ions in the sealant 30 diffusing into the display region 101 is further reduced, thereby being more beneficial to improving the display effect of the display panel 100.
It should be noted that, in the above embodiments, only the case where the non-display area 102 on the same side of the display area 101 includes three third potential lines 33 is shown, in some other embodiments of the present application, the number of the third potential lines 33 may also be other numbers, for example, only one third potential line 33 is provided in fig. 12, fig. 12 is another BB' sectional view of the display panel 100 provided in the embodiment of fig. 1, and the front projection of the third potential line 33 on the plane of the first substrate 11 is located between the first trench 41 and the second trench 42, and optionally, the front projection of the third potential line 33 on the plane of the first substrate 11 overlaps with the first potential line 31 and the second potential line 32 at the same time, so that a first electric field with higher intensity may be formed in the first trench 41, and a second electric field with higher intensity may be formed in the second trench 42. In addition, the number of the third potential lines 33 can be two, for example, referring to fig. 13, fig. 13 shows another BB' cross-sectional view of the display panel 100 provided in the embodiment of fig. 1, the orthographic projection of the first trench 41 and the second trench 42 on the plane of the first substrate 11 is located between the two third potential lines 33, the first potential line 31 and the third potential line 33 located on the left side form an electric field in the first trench 41, and the second potential line 32 and the third potential line 33 located on the right side form an electric field in the second trench 42 in the view shown in fig. 13.
It should be noted that, in the cross-sectional views provided in the embodiments of the present application, only the relative position relationship between the film layers is shown, and does not represent an actual size.
Based on the same inventive concept, the present application further provides a display device 200, please refer to fig. 14, and fig. 14 is a schematic structural diagram of the display device provided in the embodiment of the present application, in which the display device 200 includes a display panel 100, and the display panel 100 is any one of the display panels provided in the present application. It should be noted that, for the embodiments of the display device 200 provided in the embodiments of the present application, reference may be made to the embodiments of the display panel 100, and repeated descriptions are omitted. The display device provided by the application can be: any product and component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a navigator and the like.
As can be seen from the above embodiments, the display panel and the display device provided by the present invention at least achieve the following advantages:
in the display panel and the display device provided by the embodiment of the application, the non-display area includes a first potential line, a second potential line, and a third potential line located on one side, facing the second substrate, of the first potential line and the second potential line, the third potential line is isolated from the first potential line and the second potential line by a first insulating layer, particularly, the first insulating layer includes a first trench and a second trench, the first potential line and the third potential line form a first electric field in the first trench, the second potential line and the third potential line form a second electric field in the second trench, and under the action of the first electric field, impurity ions with negative charges in the sealant are gathered towards the first trench; under the effect of the second electric field, impurity ions with positive charges in the frame glue are gathered towards the second digging groove, so that the possibility of diffusion of the impurity ions in the frame glue to the display area is greatly reduced, the influence of the impurity ions on liquid crystal deflection in the display area is favorably reduced, and the display effect of the display panel and the display device is favorably improved.
Although some specific embodiments of the present invention have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustrative purposes only and are not intended to limit the scope of the present invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.
Claims (12)
1. A display panel characterized by comprising a display area and a non-display area surrounding the display area; the display panel further includes:
the first substrate and the second substrate are oppositely arranged;
the first substrate comprises a first substrate, a first potential line and a second potential line which are arranged on the same layer on one side of the first substrate facing the second substrate, and at least one third potential line which is arranged on one side of the first potential line and the second potential line facing the second substrate, wherein the third potential line is isolated from the first potential line and the second potential line by a first insulating layer; in the non-display region on the same side of the display region, the first insulating layer includes a first cutout and a second cutout;
the first potential line receives a positive voltage, the second potential line receives a negative voltage, and the third potential line receives a reference voltage, the reference voltage being between the positive voltage and the negative voltage; the first potential line and the third potential line form a first electric field in the first groove, and the second potential line and the third potential line form a second electric field in the second groove;
and the frame glue is positioned in the non-display area and on one side of the third potential line facing the second substrate, and a first interval is formed between the edge of one side of the frame glue close to the display area and the display area.
2. The display panel of claim 1, wherein the second cutout is located between the first cutout and the display area; the orthographic projection of the frame glue on the plane of the first substrate is at least overlapped with part of the first grooves.
3. The display panel of claim 1, wherein an orthographic projection of the first and second pockets on a plane of the first substrate is in the first space.
4. The display panel according to claim 1, wherein an orthographic projection of the sealant on the plane of the first substrate overlaps at least a part of the third potential lines.
5. The display panel according to claim 1, wherein the first substrate further comprises a gate driver circuit in the non-display region, the gate driver circuit comprising a high-level signal line and a low-level signal line, the first potential line being electrically connected to the high-level signal line, and the second potential line being electrically connected to the low-level signal line.
6. The display panel according to claim 5, wherein the first substrate further comprises a gate metal layer, a source drain metal layer, a touch metal layer and an electrode layer which are sequentially arranged on one side of the first substrate facing the second substrate;
the high-level signal line and the low-level signal line are arranged on the same layer as at least one of the grid metal layer and the source drain metal layer;
the first potential line, the second potential line and the touch metal layer are arranged on the same layer.
7. The display panel according to claim 6, wherein the electrode layer comprises a common electrode layer and a pixel electrode layer, wherein the pixel electrode layer is located on a side of the common electrode layer facing the second substrate, and wherein the third potential line is provided in the same layer as the pixel electrode layer.
8. The display panel according to claim 7, wherein the third potential line is electrically connected to the common electrode layer through a via hole.
9. The display panel according to claim 6, wherein the electrode layer comprises a common electrode layer and a pixel electrode layer, wherein the common electrode layer is located on a side of the pixel electrode layer facing the second substrate, and wherein the third potential line is provided in the same layer as the common electrode layer and receives a common voltage.
10. The display panel according to claim 1, wherein the first substrate includes three of the third potential lines, a third potential line, a third switch potential line, and a third switch potential line, in the non-display area on the same side as the display area; the orthographic projection of the first digging groove on the plane of the first substrate is located between the third potential line and the tenth potential line, and the orthographic projection of the second digging groove on the plane of the first substrate is located between the thirteenth potential line and the tripropyl potential line.
11. The display panel according to claim 10, wherein an orthogonal projection of the third potential line on the plane of the first substrate overlaps with the first potential line, an orthogonal projection of the third potential line on the plane of the first substrate overlaps with at least one of the first potential line and the second potential line, and an orthogonal projection of the third potential line on the plane of the first substrate overlaps with the second potential line.
12. A display device characterized by comprising the display panel according to any one of claims 1 to 11.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910359365.6A CN110333616B (en) | 2019-04-30 | 2019-04-30 | Display panel and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910359365.6A CN110333616B (en) | 2019-04-30 | 2019-04-30 | Display panel and display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110333616A CN110333616A (en) | 2019-10-15 |
| CN110333616B true CN110333616B (en) | 2022-02-25 |
Family
ID=68139892
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910359365.6A Active CN110333616B (en) | 2019-04-30 | 2019-04-30 | Display panel and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110333616B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112017541A (en) * | 2020-08-25 | 2020-12-01 | 昆山国显光电有限公司 | Display panel and display device |
| CN113589600B (en) * | 2021-06-24 | 2023-03-28 | 上海中航光电子有限公司 | Display panel and display device |
| CN113625494B (en) * | 2021-08-06 | 2023-04-07 | 厦门天马微电子有限公司 | Display panel and display device |
| CN114779539B (en) * | 2022-03-30 | 2023-03-10 | 绵阳惠科光电科技有限公司 | Display panel and adjusting method of display panel |
| CN114740663A (en) * | 2022-05-05 | 2022-07-12 | 广州华星光电半导体显示技术有限公司 | Liquid crystal display panel and liquid crystal display device |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI368094B (en) * | 2008-01-18 | 2012-07-11 | Chimei Innolux Corp | Liquid crystal display panel and liquid crystal display device using the same |
| CN101825817B (en) * | 2009-03-06 | 2011-12-14 | 北京京东方光电科技有限公司 | Liquid crystal display |
| KR101097333B1 (en) * | 2010-02-11 | 2011-12-23 | 삼성모바일디스플레이주식회사 | Liquid Crystal Display Panel |
| JP2012083513A (en) * | 2010-10-12 | 2012-04-26 | Seiko Epson Corp | Liquid crystal device, and electronic device |
| JP6063706B2 (en) * | 2012-10-19 | 2017-01-18 | 株式会社ジャパンディスプレイ | Liquid crystal display |
| JP6102543B2 (en) * | 2013-06-17 | 2017-03-29 | セイコーエプソン株式会社 | Liquid crystal device driving method, liquid crystal device, and electronic apparatus |
| JP2017111396A (en) * | 2015-12-18 | 2017-06-22 | 株式会社ジャパンディスプレイ | Display device |
| CN106483729B (en) * | 2017-01-04 | 2019-06-07 | 京东方科技集团股份有限公司 | Display base plate and display equipment |
-
2019
- 2019-04-30 CN CN201910359365.6A patent/CN110333616B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN110333616A (en) | 2019-10-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110333616B (en) | Display panel and display device | |
| CN107479283B (en) | Array substrate, display panel and display device | |
| US10817095B2 (en) | Electronic device, touch display panel and touch display substrate | |
| CN110536542B (en) | Flexible circuit board and manufacturing method thereof, display device and mobile terminal | |
| CN106324924B (en) | A kind of array substrate and preparation method thereof, display panel, display device | |
| CN106950772B (en) | Array substrate, display panel and display device | |
| US10371980B2 (en) | Display substrate, display panel and display device | |
| CN111309177B (en) | Array substrate, display panel and display device | |
| CN105629597A (en) | Array substrate, display and driving method and manufacturing method thereof and display device | |
| CN106200162B (en) | A kind of array substrate, display panel and display device | |
| CN104380367A (en) | Display device | |
| CN111580695B (en) | Display panel, manufacturing method thereof and display device | |
| CN109343285B (en) | Display panel and display device | |
| CN109872636B (en) | Display panel and display device | |
| CN109991788B (en) | Display panel and display device | |
| CN108279798A (en) | Integrated touch display panel and touch display device | |
| CN108169947B (en) | Array substrate, manufacturing method thereof and touch display device | |
| CN105045005A (en) | Liquid crystal display device and method of manufacturing the same | |
| CN106526954A (en) | Display panel and display device | |
| CN109143649B (en) | Display panel and display device | |
| CN108732830B (en) | Display panel and display device | |
| US20180373091A1 (en) | Display panel | |
| US20180329220A1 (en) | 3d display device and method for manufacturing the same | |
| CN114446260B (en) | Array substrate and display device | |
| US10747077B2 (en) | Display substrate and display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |