CN109508205B - NVM chip supporting in-situ operation, operation method thereof and solid-state storage device - Google Patents
NVM chip supporting in-situ operation, operation method thereof and solid-state storage device Download PDFInfo
- Publication number
- CN109508205B CN109508205B CN201710829805.0A CN201710829805A CN109508205B CN 109508205 B CN109508205 B CN 109508205B CN 201710829805 A CN201710829805 A CN 201710829805A CN 109508205 B CN109508205 B CN 109508205B
- Authority
- CN
- China
- Prior art keywords
- physical
- operation command
- command
- address
- situ
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000011065 in-situ storage Methods 0.000 title claims abstract description 121
- 238000003860 storage Methods 0.000 title claims abstract description 76
- 238000000034 method Methods 0.000 title claims abstract description 33
- 239000007787 solid Substances 0.000 claims abstract description 57
- 230000004044 response Effects 0.000 claims description 24
- 238000012545 processing Methods 0.000 claims description 22
- 238000012937 correction Methods 0.000 claims description 4
- 230000000737 periodic effect Effects 0.000 claims description 2
- 230000000694 effects Effects 0.000 description 11
- 230000008569 process Effects 0.000 description 11
- 238000010586 diagram Methods 0.000 description 6
- CXOXHMZGEKVPMT-UHFFFAOYSA-N clobazam Chemical compound O=C1CC(=O)N(C)C2=CC=C(Cl)C=C2N1C1=CC=CC=C1 CXOXHMZGEKVPMT-UHFFFAOYSA-N 0.000 description 3
- 229940044442 onfi Drugs 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 239000000835 fiber Substances 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000013507 mapping Methods 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 239000000872 buffer Substances 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 238000012552 review Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Read Only Memory (AREA)
Abstract
NVM chips, methods of operating NVM chips, and solid state storage devices that provide in-situ operation commands are disclosed. The disclosed method of operating an NVM chip includes: an in-place operation command is issued to one or more physical blocks of the NVM chip, the in-place operation command indicating a command code and a physical block address. By the method for operating the NVM chip, the data error rate of the NVM chip can be reduced.
Description
Technical Field
The present application relates to memory technology, and more particularly, to reducing data error rates of NV M chips by in-situ operation in solid state memory devices.
Background
Referring to FIG. 1, a block diagram of a storage device is shown. The storage device 102 is coupled to a host for providing storage capability for the host. The host and storage device 102 may be coupled by a variety of means including, but not limited to, connecting the host to storage device 10 via, for example, SATA, IDE, USB, PCIE, NVMe (NVM express), SAS, ethernet, fibre channel, wireless communication network, etc. The host may be an information processing device capable of communicating with the storage device in the manner described above, such as a personal computer, tablet, server, portable computer, network switch, router, cellular telephone, personal digital assistant, or the like. The Memory device 102 includes an interface 103, a control unit 104, one or more NVM (Non-Volatile Memory) chips 105, and optionally a firmware Memory 110. The interface 103 may be adapted to exchange data with a host by way of, for example, SATA, IDE, USB, PCIE, NVMe, SAS, ethernet, fibre channel, etc. The control unit 104 is used to control data transfer among the interface 103, NVM chip 105, and firmware memory 110, and also for storage management, host logical address to flash physical address mapping, erase balancing, bad block management, etc. The control component 104 can be implemented in a variety of ways, either in software, hardware, firmware, or a combination thereof. The control unit 104 may be in the form of an FPGA (Field-programmable gate array, field programmable gate array), an ASIC (Application Specific Integrated Circuit ) or a combination thereof. The control component 104 can also include a processor or controller. The control component 104 loads firmware from the firmware memory 110 at runtime. Firmware memory 110 may be NOR flash memory, RO M, EEPROM, or may be part of NVM chip 105.
The control section 104 includes a flash interface controller (or referred to as a media interface controller, a flash channel controller) that is coupled to the NVM chip 105 and issues commands to the NVM chip 105 in a manner conforming to an interface protocol of the NVM chip 105 to operate the NVM chip 105 and receive a command execution result output from the NVM chip 105. Known NVM chip interface protocols include "T oggle", "ONFI", and the like.
The memory Target (Target) is one or more Logic Units (LUNs) of a shared Chip Enable (CE) signal within the NAND flash package. One or more dies (Die) may be included within the NAND flash package. Typically, the logic unit corresponds to a single die. The logic cell may include multiple planes (planes). Multiple planes within a logic unit may be accessed in parallel, while multiple logic units within a NAND flash memory chip may execute commands and report status independently of each other. In "Open NAND Flash Interface Specifica tion (review 3.0)" available from https:// www.micron.com/-/media/Documents/Products/Other% 20Documents/ONFI3_0gold. Ashx, the meaning of target, logical unit, LUN, plane is provided as part of the prior art.
Some NVM chips support multi-plane operations (Multiplane Operation), allowing multiple planes on a LUN to perform the same type of operation at the same time, improving throughput or bandwidth by increasing parallelism of operations. For example, a LUN includes 4 planes, to which a read command or a program command is issued simultaneously to access a physical page of each of the 4 planes, or to which an erase operation is issued simultaneously to erase a physical block of each of the 4 planes.
Data is typically stored and read on a storage medium on a page basis. While data is erased in blocks. A block (also called a physical block) contains a plurality of pages. A block contains a plurality of pages. Pages on a storage medium (referred to as physical pages) have a fixed size, e.g., 17664 bytes. The physical pages may also have other sizes. After a page of the storage medium is programmed (data written), it is subjected to an erase process before it can be reprogrammed.
In chinese patent application publication No. CN1414468A, a scheme is provided for processing CPU (Central Processing Unit ) instructions by executing a micro instruction sequence. When the CPU is to process the specific instruction, the conversion logic circuit converts the specific instruction into a micro instruction sequence corresponding to the specific instruction, and the function of the specific instruction is realized by executing the micro instruction sequence. The micro instruction sequence or a template of the micro instruction sequence is stored in a ROM (Read Only Memory). In the process of converting a specific instruction into a micro instruction sequence, the micro instruction sequence template can be filled so as to correspond to the specific instruction.
The micro instruction execution method and apparatus for flash memory interface controllers are provided in chinese patent applications CN201610009789.6 and CN201510253428.1, chinese patent application CN 201661086 1793.5 provides a micro instruction sequence scheduling method and apparatus, chinese patent application CN 20161213 754.0 provides an IO command processing method and solid state storage device, chinese patent application CN 201611213755.5 provides a high capacity NVM interface controller, and the entire contents thereof are incorporated herein. The flash interface controller is typically coupled to multiple NVM chips, which include multiple LUNs (Logic units) or dies that can respond to and access NVM commands in parallel. Also, since there may be multiple NVM commands to be processed on each LUN or die, the NVM controller needs to schedule the processing of multiple NVM commands to maintain multiple in-process or pending NVM commands, or to maintain execution of multiple micro instruction sequences for generating and processing NVM commands.
The fast initial charge loss (Fast Initial Charge Loss) is an inherent property of NAND flash memory using charge Trapping (Char ge transfer) technology (see Study of Fast Initial Charge Loss and It's Impact on the Programmed States Vt Distributio n of Charge-Trapping NAND Flash, https:// ieeeexplore. Ieeee. Org/document/5703304 /). In the NAND flash memory of the 3D structure, the rapid initial charge loss phenomenon is more remarkable. In some documents, this is also called fast escape (fast escape). A fast initial charge loss will result in an increased error rate of the stored data.
Disclosure of Invention
To compensate for the effects of the rapid initial charge loss phenomenon, the solid state storage device of embodiments of the present application applies subsequent operations to the programmed memory cells and reduces the effects of the compensation process on the performance of the solid state storage device.
According to a first aspect of the present application, there is provided a first nonvolatile memory chip according to the first aspect of the present application, including an IO interface, a control logic circuit, and a memory cell array; the IO interface receives an in-situ operation command and stores a command code into a command register, wherein the in-situ operation command indicates a physical block address; the control logic circuit is based on the contents of the command register and the physical block address, instructing a high voltage generator to apply weak programming pulses to one or more physical pages of the physical block, wherein the one or more physical pages have been programmed; the control logic circuit writes the execution result of the in-situ operation command into the state register; and the IO interface outputs the contents of the status register.
According to a first non-volatile memory chip of the first aspect of the present application, a second non-volatile memory chip according to the first aspect of the present application is provided, wherein the amplitude of the weak programming pulse is smaller than the amplitude of the programming pulse and/or the duration of the weak programming pulse is smaller than the duration of the programming pulse.
According to the first or second nonvolatile memory chip of the first aspect of the present application, there is provided a third nonvolatile memory chip according to the first aspect of the present application, wherein the in-situ operation command further indicates target data; the IO interface writes target data into a data register; the control circuit writes the target data to the physical page indicated by the physical page address with one or more weak programming pulses according to the physical page address indicated by the address register.
According to a third nonvolatile memory chip of the first aspect of the present application, there is provided a fourth nonvolatile memory chip according to the first aspect of the present application, wherein the control circuit reads out data from a physical page indicated by the physical page address according to the physical page address indicated by the address register, comparing the read data with the target data stored in the data register, and continuing to program the memory cell whose state indicated by the read data does not reach the state corresponding to the target data to the state corresponding to the target data.
According to the first or second nonvolatile memory chip of the first aspect of the present application, there is provided the fifth nonvolatile memory chip according to the first aspect of the present application, wherein the control circuit reads out data from a physical page indicated by the physical address according to the physical page address indicated by the address register, stores the read data into the data register, and programs the physical page with the read data as target data.
According to a fifth nonvolatile memory chip of the first aspect of the present application, there is provided the sixth nonvolatile memory chip according to the first aspect of the present application, wherein the control circuit further performs error correction on the read data to obtain error corrected read data, and programs the physical page with the error corrected read data as target data.
According to the first or second nonvolatile memory chip of the first aspect of the present application, there is provided a seventh nonvolatile memory chip according to the first aspect of the present application, wherein the in-situ operation command does not indicate target data; the control circuit instructs the high voltage generator to apply a single weak programming pulse to the physical page indicated by the physical page address according to the physical page address indicated by the address register.
According to one of the first to seventh nonvolatile memory chips of the first aspect of the present application, there is provided an eighth nonvolatile memory chip according to the first aspect of the present application, wherein the in-situ operation command indicates a parameter for a weak programming pulse; the control circuit obtains the amplitude and/or duration of the weak programming pulse according to the parameters for the if programming pulse.
According to a first or second nonvolatile memory chip of a first aspect of the present application, there is provided a ninth nonvolatile memory chip according to the first aspect of the present application, wherein the control circuit instructs the high voltage generator to apply one or more weak programming pulses to all other physical pages of the physical block corresponding to the physical block address than the physical page corresponding to the physical page address, in accordance with the physical block address and the physical page address indicated by the address register.
According to a first or second nonvolatile memory chip of a first aspect of the present application, there is provided a tenth nonvolatile memory chip according to the first aspect of the present application, wherein the control circuit instructs the high voltage generator to apply one or more read pulses to all other physical pages of the physical block corresponding to the physical block address than the physical page corresponding to the physical page address, in accordance with the physical block address and the physical page address indicated by the address register.
According to the first or second nonvolatile memory chip of the first aspect of the present application, there is provided the eleventh nonvolatile memory chip according to the first aspect of the present application, wherein the control circuit instructs the high voltage generator to apply one or more weak programming pulses to all physical pages of a physical block corresponding to the physical block address according to the physical block address indicated by the address register.
According to an eleventh non-volatile memory chip of the first aspect of the present application, there is provided a twelfth non-volatile memory chip according to the first aspect of the present application, wherein the in-place operation command further indicates a physical page address.
According to a second aspect of the present application, there is provided a first solid state storage device according to the second aspect of the present application, comprising a control unit and one or more NVM chips coupled to the control unit, the control unit acquiring one or more physical blocks of the one or more NVM chips, issuing an in-place operation command to the one or more physical blocks, the in-place operation command indicating a command code and a physical block address.
According to a first solid state storage device of a second aspect of the present application, there is provided a second solid state storage device of the second aspect of the present application, wherein the control means acquires one or more physical blocks in response to expiration of a timer; and wherein a specified time interval has elapsed, the timer expiring.
According to a second solid state storage device of a second aspect of the present application, there is provided a third solid state storage device according to the second aspect of the present application, further comprising: the control unit acquires another one or more physical blocks in response to expiration of the timer again.
According to one of the first to third solid-state storage devices of the second aspect of the present application, there is provided a fourth solid-state storage device according to the second aspect of the present application, wherein the control section identifies whether or not the in-place operation command has been transmitted to the acquired one or more physical blocks within a specified time interval, and transmits the in-place operation command only to physical blocks to which the in-place operation command has not been transmitted.
According to one of the first to fourth solid state storage devices of the second aspect of the present application, there is provided a fifth solid state storage device according to the second aspect of the present application, wherein the control means sets parameters for weak programming pulses in an in-situ operation command, which parameters are indicative of the amplitude and/or duration of one or more weak programming pulses, in dependence of the lifetime of the one or more physical blocks.
According to one of the first to fifth solid state storage devices of the second aspect of the present application, there is provided a sixth solid state storage device according to the second aspect of the present application, wherein the control section sets a physical page address for the in-place operation in the in-place operation command.
According to a fourth solid state storage device of the second aspect of the present application, there is provided a seventh solid state storage device according to the second aspect of the present application, wherein the control section recognizes that an in-place operation command has been sent to the acquired first physical block within a specified time interval, depending on that data is currently being written to the first physical block.
According to one of the first to seventh solid state storage devices of the second aspect of the present application, there is provided an eighth solid state storage device according to the second aspect of the present application, wherein the control unit further receives an execution result of the in-situ operation command from the one or more NVM chips.
According to one of the first to seventh solid state storage devices of the second aspect of the present application, there is provided a ninth solid state storage device according to the second aspect of the present application, wherein the control means comprises a media interface controller and a flash memory management unit; the flash memory management unit instructs the media interface controller to issue a read command, a program command erase command or an in-situ operation command to one or more physical blocks; the media interface controller issues a read command, a program command erase command, or an in-situ operation command to one or more physical blocks in response to an indication of the flash memory management unit.
According to a ninth solid state storage device of the second aspect of the present application, there is provided the tenth solid state storage device of the second aspect of the present application, wherein the media interface controller issues the first in-place operation command to the first physical block after the first physical page of the first physical block completes processing the first programming command in response to receiving the indication of the first programming command.
According to a tenth solid state storage device of the second aspect of the present application, there is provided an eleventh solid state storage device according to the second aspect of the present application, wherein the first in-place operation command indicates the same or different physical address as the first program command, or the first in-place operation command indicates a specified physical page address on the first physical block.
According to a tenth or eleventh solid state storage device of the second aspect of the present application, there is provided a twelfth solid state storage device according to the second aspect of the present application, wherein the media interface controller indicates to the flash memory management unit that the first programming command processing is complete, and also indicates to the flash memory management unit that an in-place operation command has been sent to the first physical block.
According to one of the ninth to twelfth solid state storage devices of the second aspect of the present application, there is provided the thirteenth solid state storage device of the second aspect of the present application, wherein the flash memory management unit acquires one or more physical blocks in response to expiration of a timer and sends an indication of an in-situ operation command to the media interface controller.
According to a thirteenth solid state storage device of the second aspect of the present application, there is provided the fourteenth solid state storage device according to the second aspect of the present application, wherein for the acquired one or more physical blocks, the flash memory management unit identifies whether a program command has been issued to the one or more physical blocks at a current time interval, and for the second physical block to which a program command has been issued, no indication of an in-place operation command corresponding to the second physical block is issued to the media interface controller.
According to one of the first through fourteenth solid-state storage devices of the second aspect of the present application, there is provided a fifteenth solid-state storage device according to the second aspect of the present application, wherein the one or more NVM chips are non-volatile memory chips according to the first aspect of the present application.
According to a third aspect of the present application, there is provided a first method of operating an NVM chip according to the third aspect of the present application, comprising: an in-place operation command is issued to one or more physical blocks of the NVM chip, the in-place operation command indicating a command code and a physical block address.
According to a first method of operating an NVM chip of the third aspect of the present application, there is provided a method of operating an NVM chip according to the third aspect of the present application, further comprising: issuing a program command to a first physical page of a first physical block; in response, an in-situ operation command is issued to the first physical block after the programming command is completed by the NVM chip.
According to a third aspect of the present application, there is provided a method of operating an NVM chip according to the third aspect of the present application, wherein issuing an in-situ operation command to one or more physical blocks of the NVM chip is periodic.
According to one of the first to third methods of operating an NVM chip of the third aspect of the present application, there is provided a method of operating an NVM chip according to the fourth aspect of the present application, wherein one or more physical blocks are acquired and an in-situ operation command is issued to each of the one or more physical blocks in response to expiration of a timer.
According to one of the first to fourth methods of operating an NVM chip of the third aspect of the present application, there is provided a fifth method of operating an NVM chip according to the third aspect of the present application, wherein it is identified whether an in-place operation command has been sent to the one or more physical blocks within a specified time interval, and the in-place operation command is sent only to physical blocks not sent the in-place operation command.
According to a fourth aspect of the present application there is provided a first solid state storage device according to the fourth aspect of the present application comprising a memory and a processor, the memory storing a program which, when executed by the processor, causes the processor to perform one of the methods of operating an NVM chip according to the first to fifth aspects of the present application.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments will be briefly introduced below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 illustrates a block diagram of a prior art memory device;
FIG. 2 is a schematic diagram of control components of a solid state storage device of an embodiment of the present application;
FIG. 3 is a block diagram of an NVM chip;
FIG. 4A is a flow chart of a control component issuing an in-situ operation command to an NVM chip according to an embodiment of the present application;
FIG. 4B is a flow chart of a control component issuing an in-situ operation command to an NVM chip according to yet another embodiment of the present application; and
FIG. 4C is a flow chart of a control component issuing an in-situ operation command to an NVM chip according to another embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
FIG. 2 is a block diagram of control components of a solid state storage device according to an embodiment of the present application. The control section 104 of the solid state storage device includes therein a host interface 210, a front end processing module 220, a flash memory management module 230, and one or more media interface controllers 240. The host interface 210 is used to exchange commands and data with a host. Flash management module 230 provides logical address to physical address mapping, wear leveling, garbage collection, etc. functions and generates IO commands to media interface controller 240. The media interface controller is coupled to the NVM chip 105. The media interface controllers have one or more, each coupled to a respective NVM chip 105. The media interface controller receives the IO command and issues IO commands (commands such as read, program, erase, pause, read feature, set feature, and/or in-situ operation) to the NVM chip according to the IO command.
In one example, the media interface controller provides multiple queues with different priorities (e.g., queue 242 and queue 244, where queue 242 is a high priority queue and queue 244 is a low priority queue) to receive IO commands. The flash management module 230 fills the read command into the high priority queue of the interface controller, causing the media interface controller to process the read command preferentially. While program commands, erase commands, in-situ operation commands, and/or read commands that do not require processing delays are filled into the low priority queue of the media interface controller. The media interface controller will prioritize commands in the high priority queue 242 and process commands in the low priority queue 244. It will be appreciated that other types of IO commands may be filled into the high priority queue by the flash management module. In accordance with embodiments of the present application, the media interface controller typically prioritizes IO commands in the high priority queues and I O commands in the low priority queues with low priority.
The media interface controller includes a plurality of processing units, each of which is responsible for accessing one of the Logical Units (LUNs) of, for example, the NVM chip. And the medium interface controller processes the IO command by the corresponding processing unit according to the LUN accessed by the IO command. Each processing unit is configured to issue a command to the NVM chip and receive a response from the NVM chip to the command.
According to embodiments of the present application, the NVM chip provides in-situ operation commands. And the medium interface controller coupled with the NVM chip sends out an in-situ operation command to the LUN of the NVM chip, and the LU N of the NVM chip receives the in-situ operation command and processes according to the indication of the in-situ operation command. And optionally, giving a response to the media interface controller in terms of completion of the in-situ operation command execution. Typically, the memory cells of the NVM chip are no longer subject to programming operations after they are programmed and before they are erased, while the in-situ operation command produces a programming effect on the memory cells that have been programmed. Since the in-situ operation command acts on the memory cells that have been programmed, it is referred to as an "in-situ operation" for this reason.
As one example, the in-place operation command includes a command code and a physical address. The command code identifies the in-place operation command, and the physical address indicates the accessed plane number, physical block number, and physical page address. The NV M chip accesses the physical page in response to receiving the in-situ operation command, reads data from the physical page, and programs the physical page in-situ with the read data. In-situ programming is different from a normal programming operation. A typical programming operation writes data to memory cells of the NVM chip in an erased state in a series of programming pulses along with a verify operation. In-situ programming is applied to memory cells in a programmed state by applying relatively weak programming pulses (e.g., programming pulses having smaller voltage amplitude, duration, number, etc. parameters than in a typical programming operation) such that the state of the in-situ programmed memory cells corresponds to the data written to the memory cells. For example, a relatively weak programming pulse is applied to the memory cell indicated by the in-situ operation command, and then it is verified whether the state of the memory cell corresponds to the target data. Alternatively, the state of the memory cell is made to correspond to the target data by a plurality of relatively weak programming pulses. Since the change of the programming pulse to the state of the memory cell is unidirectional, if the state of the memory cell has not reached a state corresponding to the target data, a relatively weak programming pulse may continue to be applied; if the state of the memory cell has reached or exceeded the state corresponding to the target data, no programming pulse is applied. In any event, in the in-situ programming, at least one relatively weak programming pulse is applied to the memory cell. In one example, the original data read out using the physical page is used as target data for performing the in-situ programming operation such that the state of the memory cell being in-situ programmed corresponds to the target data. As another example, error correction is performed on the data read out of the physical page, and the corrected data is used as target data for the in-situ program operation. Optionally, the NVM chip also responds to the original program command with respect to completion of the in-situ program operation.
Optionally, parameters of the relatively weak programming pulses used (e.g., the voltage amplitude, duration, etc. of the programming pulses) are also indicated in the in-situ operation command. The NVM chip generates programming pulses according to parameters indicated by the in-situ operation command. The control component indicates the corresponding programming pulse parameters according to the lifecycle and/or operating environment in which the NVM chip is located.
As yet another example, the in-place operation command includes a command code, a physical address, and target data. The NVM chip is configured to perform in-situ programming operations based on target data provided by the in-situ operation command.
As another example, the in-place operation command includes a command code and a physical address, and the physical address indicates a plane number and a physical block number of access without identifying a physical page address. The NVM chip generates a random or specified physical page address based on the in-place operation command. The specified physical page address is, for example, the address of the first physical page, the last physical page, or the centered physical page within the physical block. And performing a home program operation on the generated physical page address within the physical block indicated by the home operation command. Since the individual memory cells within a physical block are coupled to each other directly or indirectly, an in-situ programming operation on a random or designated physical page within the physical block will produce a weak programming effect on other physical pages within the physical block and compensate for the effects of rapid initial charge loss. Alternatively, in an in-situ programming operation, a relatively weak programming pulse is applied without performing a subsequent verify operation.
As yet another example, the in-place operation command includes a command code and a physical address, and the physical address indicates a plane number and a physical block number of access without identifying a physical page address. The NVM chip applies in-situ program operations to all physical pages of the designated physical block according to the in-situ operation command. For example, all physical pages within a physical block are selected and weaker programming pulses are applied to the word lines of all selected physical pages. Alternatively, in an in-situ programming operation, a relatively weak programming pulse is applied without performing a subsequent verify operation.
As yet another example, the in-place operation command includes a command code and a physical address, and the physical address indicates a plane number and a physical block number of access without identifying a physical page address. The NVM chip applies a read operation to a specified or random physical page of a specified physical block according to an in-place operation command. For a normal read operation, the word lines of the unselected physical pages within the physical block are applied with a gating voltage that is generally lower than the programming voltage applied to the word lines, such that the gating voltage produces an effect on the physical page similar to a weaker programming pulse. And compensates for the effects of rapid initial charge loss. By way of example, the physical block includes, for example, a dummy physical page. To perform a read operation on the dummy physical page, other physical pages of the physical block except for the dummy physical page are applied with a gate voltage, thereby generating an effect similar to a weaker program pulse on all other physical pages of the physical block except for the dummy physical page. And applying a read operation to the pseudo physical page by the NVM chip according to the in-situ operation command. The NVM chip applies a read operation to a specified physical block to apply a strobe voltage without acquiring read data, e.g., without amplifying, comparing, and/or decoding the output of the bit lines.
As yet another example, the in-situ operation command is a read command that does not require data output. The NVM chip applies a read operation to a specified physical page of a specified physical block according to the in-place operation command. Thus, the gate voltage is applied to the word lines of all physical pages of the specified physical block except the instruction physical page. The NVM chip can obtain stored data from the bit line output of the physical page being read. Thus, the NVM chip can support in-situ operation commands without modification. Alternatively, the NVM chip does not transmit the read data to the media interface controller because the in-situ operation command does not require a data output. Thereby reducing processing delay of in-situ operation commands.
According to embodiments of the present application, the control component 104 of the solid state storage device compensates for the effects of the rapid initial charge loss phenomenon of the NVM chip by issuing an in-situ operation command to the NVM chip 1 05. Control component 104 repeatedly issues in-situ operation commands to each physical block of the NVM chip. For example, the control section 104 sets a timer, and when the timer expires, the control section 104 acquires one or more physical blocks and issues an in-situ operation command to the physical blocks in response. And when the timer expires next time, the control unit 104 acquires another physical block or blocks and issues an in-situ operation command to the physical blocks. So that for each physical block, in-situ operation commands are received within a certain time interval. Optionally, the control component 104 sets parameters for the in-situ operation command according to the use of the solid state storage device. For example, parameters for the in-situ operation command are adjusted according to the lifetime (number of times erased) of the accessed physical block.
FIG. 3 illustrates a block diagram of an NVM chip according to an embodiment of the present application. NAND flash memory is taken as an example of an NVM chip. The NVM chip provides services by receiving, processing, and responding to memory commands, such as IO commands. The NVM chip includes an IO interface, a control logic unit, and a memory cell array.
The IO interface is used for receiving and sending addresses and/or data in the IO command. Optionally, the data and/or address further comprises a command code of the memory command. The IO interface stores the command code in the IO command to the command register, the address in the IO command to the address register, and the data in the IO command to the data register, or for the read command, the data of the data register is transferred through the IO interface to, for example, the control unit 104 (see also fig. 1 and 2). The IO reception is also coupled to a status register that stores the execution results of the IO command, which the IO interface provides to, such as control component 104. The IO interface receives and transmits addresses and/or data in IO commands through external signal pins, e.g., DQ, DQS signal pins defined in the ONFI protocol.
The control logic unit is used for controlling the processing process of the NVM chip to the IO command according to the instruction of the IO command. The control part receives the IO command through the external signal pin and sends the execution result of the IO command. For example, CE, CLE, ALE and/or WE signal pins are defined in the ONFI protocol. The control logic unit identifies the IO command according to the external signal pin, acquires the address, data and/or command code of the IO command, controls the read, program or erase operation process of the memory cell array according to the command code and/or the external signal, operates the high voltage generator to provide the required read pulse, program pulse and/or erase pulse to the memory cell array, fills the IO command processing result into the status register, and indicates the progress and result of the IO command execution to the control unit 104 through the external signal pin.
The memory cell array includes a plurality of memory cells for storing data. Memory cells can be programmed, read, and erased. The memory cell array is also coupled to the column decoder, the row decoder, and the data register. The column decoder is used for decoding column addresses in the addresses to select accessed columns. The row decoder is used for decoding row addresses in the addresses to select the accessed row. An address decoder is also provided to identify the LUN, plane, and/or physical block accessed by the I O command. The data register buffers data to be written to the memory cells and/or data read from the memory cells.
According to an embodiment of the present application, in response to receiving a home operation command, the control logic unit identifies the home operation command from the command register. The address accessed by the in-place operation command is stored in an address register. Optionally, the control logic unit also generates a random or specified physical page address for an in-place operation command that does not carry a physical page address. And performing address decoding on the physical page address, and selecting the corresponding physical page. The control logic unit instructs the high voltage generator to generate a weaker programming pulse read pulse to apply to the selected physical page, the physical block in which the selected physical page is located, or all physical pages in the physical block in which the selected physical page is located except the selected physical page. The control logic unit controls parameters of the weaker programming pulse read pulse generated by the high voltage generator, and generates information indicating the execution result of the in-situ operation command, which is stored in the status register. And the control logic unit also gives the execution result of the in-situ operation command to the control part 104 through the external signal pin.
As one example, the in-place operation command includes a command code and a physical address. The physical address indicates a physical block. The control logic unit instructs the row decoder to select all word lines of the physical block according to the physical address. The control logic unit thus applies a weaker programming pulse to all word lines of the physical block through the high voltage generator and controls the time at which the programming pulse is applied to the word lines. And generating information indicating a result of execution of the in-situ operation command.
As one example, the in-place operation command includes a command code and a physical address. The physical address indicates a physical block. The control logic unit generates a page address of the dummy physical page according to the physical address and supplies the page address to the row decoder to select the dummy physical page through the row decoder. The control logic unit thus applies weaker programming pulses to all word lines of the physical block except the dummy physical page through the high voltage generator.
As one example, the in-place operation command includes a command code and a physical address. The physical address indicates a physical page. The row decoder selects a word line corresponding to the physical page according to the physical page address, and the control logic unit applies a read signal to the physical page. Data read from the physical page is stored in a data register. The control logic unit then performs an in-situ program operation on the selected physical page with the data in the data register. Optionally, error correction is also performed on the data in the data register, and an in-situ programming operation is performed with the corrected data.
As one example, the in-situ operation command is a read command. The physical page address of the read command causes the row decoder to select a word line in the physical block corresponding to the physical page address and apply a gate voltage to word lines in the physical block corresponding to other physical pages except the physical page being read. Alternatively, the control logic unit has generated information indicating the execution result of the in-situ operation command and supplied to the control section 104 without transferring data from the memory cell array to the data register or before transferring data from the data register to the control section 104 through the IO interface.
Optionally, the control logic unit also obtains parameters indicative of the programming pulses for the weaker programming pulses from the in situ programming operation command and controls the amplitude, shape and/or duration of the programming pulses generated by the high voltage generator in accordance with the parameters.
Fig. 4A is a flow chart of control unit 104 issuing an in-situ operation command to NVM chip 105, implemented by media interface controller 240 (see also fig. 2) of control unit 104, according to an embodiment of the application. The media interface controller 240 recognizes that a program command has been issued to a memory cell of the NVM chip (4), and after the program command, issues an in-situ operation command to the same memory cell (420). This subsequent in-situ operation command is added by the media interface controller, rather than the flash management module 230 (see FIG. 2) being sent to the media interface controller. Under the control of the media interface controller 240, the programming command is issued consecutively with its subsequent in-place operation command without intervening other commands accessing the same LUN. By way of example, for each of the successive programming commands of a physical block, the media interface controller adds thereafter an in-situ operation command to access the physical block. Optionally, the media interface controller 240 also inserts a specified time interval (e.g., several milliseconds to several tens of milliseconds) between the programming command and its subsequent in-situ operation command to maximize the compensation effect for the rapid initial charge loss phenomenon. To enhance the performance of the solid state storage device, the media interface controller 240 is allowed to issue an access command to a LUN accessed by a programming command and its subsequent in-place operation command based on such access requests if such access request occurs within a specified time interval. Further, if the access command is exactly a read command or a normal operation command to the physical block accessed by the program command and its subsequent normal operation command, the subsequent normal operation command may be omitted.
In an alternative embodiment, the processing units of media interface controller 240 implement the process flow illustrated in FIG. 4A. The processing unit is responsible for issuing IO commands to, for example, a LUN, and after issuing the programming commands, issuing in-situ operation commands to the physical blocks accessed by the programming commands. Further, the processing unit also records the location where the physical block was programmed. In response to a portion of the physical pages of the physical block not having been programmed, the processing unit directs, in the in-place operation command, to issue the in-place operation command only to the physical pages of the physical block that have been programmed, or to dummy physical pages of the physical block. For example, the processing unit records the current programmed location of the physical block, and issues the in-situ operation command only to the physical page or the dummy physical page preceding the location when the in-situ operation command is added to the program command. Alternatively or in addition, the media interface controller 240 also obtains data to be written by the programming command and uses the data for the target data of the in-situ operation command.
Fig. 4B is a flow chart of control component 104 issuing in-situ operation commands to NVM chip 105, implemented by, for example, a flash management module (see fig. 2, flash management module 230) of control component 104, according to yet another embodiment of the present application. The operations indicated in fig. 4B are performed sporadically or periodically as background tasks for the solid state storage device and are independent of access to the solid state storage device by a host or other device. Optionally, the background task has a lower priority than the host's access to the solid state storage device.
In the background task, the flash management module 230 sends in-place operation commands to the individual physical blocks of the solid state storage device. For example, physical blocks of the respective LUNs are acquired in the order of their physical block addresses (440), and an in-place operation command is sent to each physical block of the respective LUNs (450). The in-situ operation command is sent by the media interface controller to the corresponding NVM chip as directed by flash management module 230. Optionally, the flash management module maintains specified time intervals (e.g., several milliseconds to several tens milliseconds), each of which sends an in-situ operation command to the physical block. Within a specified time interval, flash management module 230 selects the appropriate opportunity to send the in-situ operation command. For example, selecting a period of time when the workload of the solid state storage device is light sends an in-place operation command to one or more physical blocks; alternatively, the in-situ operation command is issued at an average time interval as much as possible to reduce the fluctuation of the load of the solid-state storage device.
As yet another example, flash management module 230 maintains flag information for each physical block. The flag information of all physical blocks is set every time a specified time interval starts or ends. When the in-situ operation command is to be sent, checking the mark information of the corresponding physical block, and if the mark information is not cleared, sending the in-situ operation command to the physical block; if the flag information is clear, then no in-situ operation command is issued to the physical block. And correspondingly, each time the media interface controller issues the in-situ operation command according to the flow shown in fig. 4A, the flag information corresponding to the physical block accessed by the remote operation command is also cleared, so as to indicate to the flash memory management module 230 that the in-situ operation command is not required to be sent to the physical block any more in the current time interval.
As yet another example, flash management module 230 assigns a physical address to a write command that accesses a solid state storage device, thereby knowing the one or physical blocks that are currently being programmed. Flash management module 230 sweeps one or more physical blocks currently being programmed while sending in-place operation commands to the respective physical blocks within a specified time interval, without sending in-place operation commands to the physical blocks currently being programmed. In this way, the flash memory management module 230 does not need to maintain the flag information corresponding to the physical block, thereby saving memory occupation and improving efficiency.
Fig. 4C is a flow chart of control component 104 issuing in-situ operation commands to NVM chip 105, implemented by control component 104 in conjunction with, for example, a flash management module (see fig. 2, flash management module 230) and media interface controller 240, according to another embodiment of the present application.
At specified time intervals, for example, in response to expiration of a timer (460), flash management module 230 obtains one or more physical blocks (470). By way of example, physical blocks are acquired sequentially in the order of their addresses. Flash memory management module 230 identifies whether the acquired physical block received the in-place operation command within the current time interval (480) and issues an in-place operation command to the physical block that did not receive the in-place operation command (490). In one example, the flash management module 230 identifies whether the physical block received the in-situ operation command within the current time interval according to the flag information of the physical block; and modifying the flag information of the physical block with issuing an in-situ operation command to the physical block. Both the flash management module 230 and the media interface controller 240 generate in-situ operation commands, which in turn update the flag information of the physical blocks. As yet another example, flash management module 230 is aware of one or physical blocks currently being programmed for which it will receive in-place operation commands generated by media interface controller 240 so that flash management module 230 does not send in-place operation commands to it during the current time interval.
The media interface controller 240, in response to receiving the indication of the in-situ operation command from the flash memory management module 230, issues the in-situ operation command to the corresponding physical block; in response to receiving the instruction for the program command issued by the flash memory management module 2, the program command is issued to the corresponding physical block, and the in-situ operation command is generated, and after the program command is processed, the in-situ operation command is issued to the corresponding physical block. The media interface controller 240, in response to sending the in-situ operation command to the physical block, also updates the flag information corresponding to the physical block to indicate to the flash memory management module 230 that the in-situ operation command is no longer required to be issued to the physical block during the current time interval.
Optionally, the media interface controller 240, in response to receiving an instruction for a read command from the flash memory management module 230, issues the read command to the corresponding physical block and also updates the flag information corresponding to the physical block. In this example, the read command produces an effect similar to the in-situ operation command.
Optionally, the media interface controller also generates a random or specified page address when generating the in-place operation command.
The foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes and substitutions are intended to be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (32)
1. A nonvolatile memory chip comprises an IO interface, a control logic circuit and a memory cell array;
the IO interface receives an in-situ operation command and stores a command code into a command register, wherein the in-situ operation command indicates a physical block address;
control logic circuitry directs a high voltage generator to apply weak programming pulses to one or more physical pages of the physical block, wherein the one or more physical pages have been programmed, based on the contents of a command register and the physical block address;
the control logic circuit writes the execution result of the in-situ operation command into the state register; and
the IO interface outputs the content of the status register;
wherein the in-place operation command comprises a command code and a physical address, and the executing of the in-place operation command comprises: one or more physical pages are accessed according to the physical address of the in-situ operation command, data is read from the physical pages, and the physical pages are programmed in-situ with the read data.
2. The nonvolatile memory chip of claim 1 wherein
The amplitude of the weak programming pulse is smaller than the amplitude of the programming pulse and/or the duration of the weak programming pulse is smaller than the duration of the programming pulse.
3. The nonvolatile memory chip of claim 1 wherein
The in-situ operation command indicates parameters for the weak programming pulse; the control circuit obtains the amplitude and/or duration of the weak programming pulse according to the parameters for the weak programming pulse.
4. The nonvolatile memory chip of claim 1 wherein the in-situ operation command further indicates target data; the IO interface writes target data into a data register;
the control circuit is responsive to the physical page address indicated by the address register, target data is written to the physical page indicated by the physical page address with one or more weak programming pulses.
5. The nonvolatile memory chip as in claim 4, wherein
The control circuit reads data from the physical page indicated by the physical page address according to the physical page address indicated by the address register, compares the read data with target data stored in the data register, and continues programming the memory cell whose state indicated by the read data has not reached the state corresponding to the target data to the state corresponding to the target data.
6. The nonvolatile memory chip of claim 1 wherein
The control circuit reads data from the physical page indicated by the physical page address according to the physical page address indicated by the address register, stores the read data in the data register, and programs the physical page with the read data as target data.
7. The nonvolatile memory chip of claim 6 wherein
The control circuit also performs error correction on the read data to obtain error-corrected read data, and programs the physical page with the error-corrected read data as target data.
8. The nonvolatile memory chip of claim 1 wherein the in-place operation command does not indicate target data;
the control circuit instructs the high voltage generator to apply a single weak programming pulse to the physical page indicated by the physical page address according to the physical page address indicated by the address register.
9. The nonvolatile memory chip of claim 1 wherein
The control circuit instructs the high voltage generator to apply one or more weak programming pulses to all other physical pages of the physical block corresponding to the physical block address except the physical page corresponding to the physical page address according to the physical block address and the physical page address indicated by the address register.
10. The nonvolatile memory chip of claim 1 wherein
The control circuit instructs the high voltage generator to apply one or more read pulses to all other physical pages of the physical block corresponding to the physical block address except the physical page corresponding to the physical page address according to the physical block address and the physical page address indicated by the address register.
11. The nonvolatile memory chip of claim 1 wherein
The control circuit instructs the high voltage generator to apply one or more weak programming pulses to all physical pages of the physical block corresponding to the physical block address according to the physical block address indicated by the address register.
12. The nonvolatile memory chip of claim 11, wherein the method comprises the steps of
The in-place operation command also indicates a physical page address.
13. A solid state storage device comprising a control component and one or more NVM chips coupled to the control component, the control component acquiring one or more physical blocks of the one or more NVM chips, issuing an in-place operation command to the one or more physical blocks, the in-place operation command indicating a command code and a physical address; wherein the executing of the in-situ operation command includes: accessing one or more physical pages according to the physical address of the in-situ operation command, reading data from the physical pages, and in-situ programming the physical pages with the read data; wherein the control logic circuit directs the high voltage generator to apply weak programming pulses to one or more physical pages of the physical block, wherein the one or more physical pages have been programmed.
14. The solid state storage device of claim 13, wherein
The control part obtains one or more physical blocks in response to expiration of a timer; and pass through therein the time interval is specified to be a time interval, the timer expires.
15. The solid state storage device of claim 14, wherein
Further comprises: the control unit acquires another one or more physical blocks in response to expiration of the timer again.
16. The solid state storage device of claim 13, wherein
The control section identifies whether or not a home operation command has been transmitted to the acquired one or more physical blocks within a specified time interval, and transmits a home operation command only to physical blocks to which no home operation command has been transmitted.
17. The solid state storage device of claim 13, wherein
The control means sets parameters for the weak programming pulses in the in-situ operation command, which parameters are indicative of the amplitude and/or duration of the weak programming pulse or pulses, in dependence of the lifetime of the physical block or blocks.
18. The solid-state storage device of any of claims 13-17, wherein
The control section sets a physical page address for the in-place operation in the in-place operation command.
19. The solid state storage device of claim 16, wherein
The control section recognizes that an in-situ operation command has been transmitted to the acquired first physical block within a specified time interval, based on data being currently written to the first physical block.
20. The solid-state storage device of any of claims 13-17, wherein
The control component also receives results of execution of the in-situ operation command from the one or more NVM chips.
21. The solid state storage device of claim 13, wherein
The control part comprises a medium interface controller and a flash memory management unit;
the flash memory management unit instructs the media interface controller to issue a read command, a program command erase command or an in-situ operation command to one or more physical blocks;
the media interface controller issues a read command, a program command erase command, or an in-situ operation command to one or more physical blocks in response to an indication of the flash memory management unit.
22. The solid state storage device of claim 13, wherein
The media interface controller, in response to receiving an indication of the first programming command, issues a first in-situ operation command to the first physical block after the first physical page of the first physical block completes processing the first programming command.
23. The solid state storage device of claim 22, wherein
The first in-place operation command indicates the same or a different physical address as the first program command, or the first in-place operation command indicates a specified physical page address on the first physical block.
24. The solid state storage device of claim 23, wherein
The media interface controller indicates to the flash memory management unit that the first programming command processing is complete and also indicates to the flash memory management unit that an in-place operation command has been sent to the first physical block.
25. The solid state storage device of claim 23, wherein
The flash memory management unit obtains one or more physical blocks in response to expiration of a timer and sends an indication of an in-situ operation command to the media interface controller.
26. The solid state storage device of claim 25, wherein
For the acquired one or more physical blocks, the flash memory management unit identifies whether a program command was issued to the one or more physical blocks at a current time interval, and for a second physical block to which a program command has been issued, does not issue an indication of an in-place operation command corresponding to the second physical block to the media interface controller.
27. The solid state storage device of claim 26, wherein
Further comprises:
an in-place operation command is issued to one or more physical blocks of the NVM chip, the in-place operation command indicating a command code and a physical block address.
28. The solid-state storage device of any of claims 13-17, 21-27, wherein
Selecting a period of time when the workload of the solid state storage device is light, and sending an in-situ operation command to one or more physical blocks; alternatively, the in-situ operation command is issued at an average time interval.
29. A method of operating an NVM chip, comprising:
issuing a home operation command to one or more physical blocks of the NVM chip, the home operation command indicating a command code and a physical address; wherein the executing of the in-situ operation command includes: accessing one or more physical pages according to a physical address of an in-situ operation command, reading data from the physical pages, and in-situ programming the physical pages with the read data, wherein control logic circuitry directs a high voltage generator to apply weak programming pulses to one or more physical pages of the physical block, wherein the one or more physical pages have been programmed.
30. The method of operating an NVM chip of claim 29, wherein
Issuing an in-situ operation command to one or more physical blocks of the NVM chip is periodic.
31. The method of operating an NVM chip of claim 29, wherein
One or more physical blocks are acquired and an in-situ operation command is issued to each of the one or more physical blocks in response to expiration of the timer.
32. The method of operating an NVM chip of claim 29, wherein
Identifying whether a in-place operation command has been sent to the one or more physical blocks within a specified time interval, and sending only in-place operation commands to physical blocks that have not been sent in-place operation commands.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710829805.0A CN109508205B (en) | 2017-09-15 | 2017-09-15 | NVM chip supporting in-situ operation, operation method thereof and solid-state storage device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710829805.0A CN109508205B (en) | 2017-09-15 | 2017-09-15 | NVM chip supporting in-situ operation, operation method thereof and solid-state storage device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109508205A CN109508205A (en) | 2019-03-22 |
| CN109508205B true CN109508205B (en) | 2024-04-05 |
Family
ID=65744580
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710829805.0A Active CN109508205B (en) | 2017-09-15 | 2017-09-15 | NVM chip supporting in-situ operation, operation method thereof and solid-state storage device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109508205B (en) |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1667753A (en) * | 2004-03-09 | 2005-09-14 | 基洛帕斯技术公司 | Methods and circuits for programming of a semiconductor memory cell and memory array |
| CN1777959A (en) * | 2003-04-24 | 2006-05-24 | 先进微装置公司 | Method of dual cell memory device operation for improved end-of-life read margin |
| CN101351847A (en) * | 2005-12-28 | 2009-01-21 | 桑迪士克股份有限公司 | Alternate sensing techniques for non-volatile memory |
| CN101405813A (en) * | 2006-06-22 | 2009-04-08 | 桑迪士克股份有限公司 | Method for non-real time reprogramming of non-volatile memory to achieve tighter distribution of threshold voltages |
| CN101625899A (en) * | 2008-07-10 | 2010-01-13 | 海力士半导体有限公司 | Method for programming of non volatile memory device |
| CN102027455A (en) * | 2008-05-13 | 2011-04-20 | 拉姆伯斯公司 | Fractional program commands for memory devices |
| CN102077298A (en) * | 2008-06-30 | 2011-05-25 | 桑迪士克公司 | Read disturb mitigation in non-volatile memory |
| US8942028B1 (en) * | 2014-06-16 | 2015-01-27 | Sandisk Technologies Inc. | Data reprogramming for a data storage device |
| US9620226B1 (en) * | 2015-10-30 | 2017-04-11 | Western Digital Technologies, Inc. | Data retention charge loss and read disturb compensation in solid-state data storage systems |
| CN106951374A (en) * | 2016-01-06 | 2017-07-14 | 北京忆芯科技有限公司 | Method and its device for checking block page address |
-
2017
- 2017-09-15 CN CN201710829805.0A patent/CN109508205B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1777959A (en) * | 2003-04-24 | 2006-05-24 | 先进微装置公司 | Method of dual cell memory device operation for improved end-of-life read margin |
| CN1667753A (en) * | 2004-03-09 | 2005-09-14 | 基洛帕斯技术公司 | Methods and circuits for programming of a semiconductor memory cell and memory array |
| CN101351847A (en) * | 2005-12-28 | 2009-01-21 | 桑迪士克股份有限公司 | Alternate sensing techniques for non-volatile memory |
| CN101405813A (en) * | 2006-06-22 | 2009-04-08 | 桑迪士克股份有限公司 | Method for non-real time reprogramming of non-volatile memory to achieve tighter distribution of threshold voltages |
| CN102027455A (en) * | 2008-05-13 | 2011-04-20 | 拉姆伯斯公司 | Fractional program commands for memory devices |
| CN102077298A (en) * | 2008-06-30 | 2011-05-25 | 桑迪士克公司 | Read disturb mitigation in non-volatile memory |
| CN101625899A (en) * | 2008-07-10 | 2010-01-13 | 海力士半导体有限公司 | Method for programming of non volatile memory device |
| US8942028B1 (en) * | 2014-06-16 | 2015-01-27 | Sandisk Technologies Inc. | Data reprogramming for a data storage device |
| US9620226B1 (en) * | 2015-10-30 | 2017-04-11 | Western Digital Technologies, Inc. | Data retention charge loss and read disturb compensation in solid-state data storage systems |
| CN106951374A (en) * | 2016-01-06 | 2017-07-14 | 北京忆芯科技有限公司 | Method and its device for checking block page address |
Non-Patent Citations (2)
| Title |
|---|
| High dynamic performance programmed PWM control of a multilevel inverter with capacitor DC sources;John N. Chiasson;《Proceedings of the 48h IEEE Conference on Decision and Control (CDC) held jointly with 2009 28th Chinese Control Conference》;全文 * |
| 可在系统内重新编程的非易失存储器――闪烁EPROM;车明康;微电子学与计算机(09);全文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109508205A (en) | 2019-03-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10466903B2 (en) | System and method for dynamic and adaptive interrupt coalescing | |
| US11237765B2 (en) | Data writing method and storage device | |
| JP6805205B2 (en) | Devices and methods for managing data in memory | |
| US20190324647A1 (en) | Memory system and operating method thereof | |
| US20180150242A1 (en) | Controller and storage device for efficient buffer allocation, and operating method of the storage device | |
| US10846017B2 (en) | Secure digital (SD) to NVMe buffer manager | |
| CN111045593B (en) | Method for reading acceleration, data storage device and controller thereof | |
| US10503438B1 (en) | Memory sub-system supporting non-deterministic commands | |
| US20160027518A1 (en) | Memory device and method for controlling the same | |
| US11307768B2 (en) | Namespace auto-routing data storage system | |
| CN112534391A (en) | Limiting response signals from a memory system | |
| US11861207B2 (en) | Management of erase suspend and resume operations in memory devices | |
| US11119693B2 (en) | Method of operating storage device for improving QOS latency and storage device performing the same | |
| KR20200129943A (en) | Storage device and operating method thereof | |
| US11687363B2 (en) | Internal management traffic regulation for memory sub-systems | |
| US20180299935A1 (en) | Memory device and data storage device including the same | |
| US20200409846A1 (en) | Dual controller cache optimization in a deterministic data storage system | |
| KR20200129700A (en) | Controller and memory system having the same | |
| CN109508205B (en) | NVM chip supporting in-situ operation, operation method thereof and solid-state storage device | |
| US20210124497A1 (en) | Quality of service for memory devices using weighted memory access operation types | |
| TWI631565B (en) | Methods for garbage collection in a flash memory and apparatuses using the same | |
| TWI602186B (en) | Methods for garbage collection in a flash memory and apparatuses using the same | |
| US20240071513A1 (en) | Erase suspend with configurable forward progress | |
| CN114328304B (en) | Method and device for operating storage medium | |
| CN112231252B (en) | Internal management traffic throttling for memory subsystem |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information |
Address after: 100192 room A302, building B-2, Dongsheng Science Park, Zhongguancun, 66 xixiaokou Road, Haidian District, Beijing Applicant after: Beijing yihengchuangyuan Technology Co.,Ltd. Address before: 100192 room A302, building B-2, Dongsheng Science Park, Zhongguancun, 66 xixiaokou Road, Haidian District, Beijing Applicant before: BEIJING MEMBLAZE TECHNOLOGY Co.,Ltd. |
|
| CB02 | Change of applicant information | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |