CN109477241B - Evaluation method and production method for silicon wafer - Google Patents

Evaluation method and production method for silicon wafer Download PDF

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CN109477241B
CN109477241B CN201780043227.6A CN201780043227A CN109477241B CN 109477241 B CN109477241 B CN 109477241B CN 201780043227 A CN201780043227 A CN 201780043227A CN 109477241 B CN109477241 B CN 109477241B
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silicon wafer
thermal donor
generation rate
silicon
region
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CN109477241A (en
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鸟越和尚
小野敏昭
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Sumco Corp
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    • H—ELECTRICITY
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    • C—CHEMISTRY; METALLURGY
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    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B15/00—Single-crystal growth by pulling from a melt, e.g. Czochralski method
    • C30B15/20—Controlling or regulating
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B15/00—Single-crystal growth by pulling from a melt, e.g. Czochralski method
    • C30B15/20—Controlling or regulating
    • C30B15/203—Controlling or regulating the relationship of pull rate (v) to axial thermal gradient (G)
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/02—Elements
    • C30B29/06—Silicon
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
    • C30B33/02—Heat treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H01L21/3225—Thermally inducing defects using oxygen present in the silicon body for intrinsic gettering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

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Abstract

The invention aims to evaluate the existence and the type of a defect area of a silicon wafer by a simple method by reducing time and cost. A method for evaluating a silicon wafer cut out from a silicon single crystal ingot grown by the Czochralski method, wherein the generation rate of a thermal donor generated when a thermal donor is applied to the silicon wafer to generate a heat treatment is measured (S14), and the presence or absence of a crystal defect region or the type of a crystal defect is discriminated on the basis of the generation rate of the thermal donor (S15).

Description

Evaluation method and production method for silicon wafer
Technical Field
The present invention relates to a method for evaluating a silicon wafer and a method for manufacturing the same, and more particularly to a method for evaluating a crystal defect region of a silicon wafer manufactured by the czochralski method (hereinafter referred to as the CZ method).
Background
Various methods are used for producing single crystal silicon used as a semiconductor material, and a CZ (Czochralski) method or an FZ (Floating Zone) method is generally used. The CZ method is a method in which a polycrystalline raw material filled in a quartz crucible is heated and melted by a heater, a seed crystal is immersed in the melt, and the seed crystal is pulled upward while being rotated, thereby growing a single crystal. The FZ method is a method of melting a part of a polycrystalline raw material rod by high-frequency heating to produce a molten region and growing a single crystal while moving the molten region. Since the CZ method is easy to form a large-diameter crystal, a wafer cut out from a single-crystal silicon produced by the CZ method is used as a highly integrated semiconductor device substrate.
When a silicon wafer produced by the CZ method is subjected to thermal oxidation treatment at 1000 to 1200 ℃ for 1 to 10 hours in an acidic atmosphere, oxidation induced Stacking faults (hereinafter referred to as osf (oxidation induced Stacking fault) rings) in a ring shape may occur. In addition, several micro defects (hereinafter, referred to as Grown-in defects) are formed.
The generation site of OSF ring in the crystal is determined by the ratio V/G of the growth rate (pulling rate) V of single-crystal silicon to the temperature gradient G in the pulling axis direction in the temperature region from the melting point of the grown single-crystal silicon to 1300 ℃. When the V/G is larger than the critical value at which the OSF ring disappears in the center of the crystal, the voids aggregate to form octahedral void (void) defects of about 0.1 μm, and the breakdown voltage of the gate oxide film is deteriorated or poor isolation of the element isolation region is caused in the production of MOS LSI. In addition, when a Trench Capacitor (Trench Capacitor) is used, characteristics such as punch-through between capacitors are poor. On the other hand, when V/G is less than the critical value, silicon between lattices is aggregated to form dislocation clusters (dislocation clusters), which causes poor characteristics such as PN junction leakage.
To cope with such a problem, many methods have been proposed in the past. For example, patent document 1 proposes the following method: a region where no grown-in defect or OSF ring is generated (hereinafter referred to as a defect-free region) is grown by controlling the ratio V/G of the pulling rate V to the temperature gradient G in the crystal during the single crystal growth.
As a method for evaluating grown-in defects, OSF rings, and the like, for example, a method of detecting void defects by an infrared scattering tomography, a method of observing an OSF ring developed by etching after the thermal oxidation treatment at 1000 to 1200 ℃.
Patent documents 2 and 3 describe a method for analyzing and evaluating crystal defects of a silicon wafer by a so-called copper decoration (copper decoration) method. For example, an analysis method described in patent document 2 includes: a step of forming a thermal oxide film of a prescribed thickness on the surface of the bare wafer; etching the back side of the bare wafer; a stage of executing copper decoration on the defect part of the bare chip; and analyzing the defect part of the wafer decorated with copper after the copper decoration execution stage. In the analysis stage, in addition to the distribution and density of the defect sites of the wafer decorated with copper by means of the flesh eye analysis, the morphology (morphology) of the defect sites of the wafer decorated with copper is analyzed by means of a Transmission Electron Microscope (TEM) or a Scanning Electron Microscope (SEM).
Patent document 3 describes a method for evaluating crystal defects in a silicon single crystal produced by the CZ method by a copper decorating method in which a sample contaminated with copper is heat-treated and then rapidly cooled. In this evaluation method, the interstitial oxygen concentration in the crystal is 10X 1017atoms/cm3(ASTM' 79) or less, and a region in which OSF exists or which serves as a nucleus of OSF is detected with high sensitivity by applying a copper decoration method to a low-oxygen-concentration single crystal silicon.
Patent document 4 describes a method for evaluating a wafer structure relating to oxygen concentration distribution such as measurement of the thickness of an epitaxial layer and a DZ layer in an epitaxial wafer by measuring the resistivity of the wafer due to a thermal donor generated from oxygen between crystal lattices when a silicon wafer is annealed at a low temperature of about 450 ℃.
Documents of the prior art
Patent document
Patent document 1: japanese laid-open patent publication No. 8-330316
Patent document 2: japanese laid-open patent publication No. 10-227729
Patent document 3: japanese laid-open patent application No. 2001-81000
Patent document 4: japanese laid-open patent publication No. 9-82768
Disclosure of Invention
Technical problem to be solved by the invention
However, conventional methods for evaluating crystal defects of silicon wafers generally require a plurality of heat treatment and etching steps according to the type of crystal defects, and thus have a problem that time and cost are required for evaluation.
Further, the method of evaluating crystal defects of a silicon wafer by the copper decoration method can simultaneously evaluate the presence or absence of a grown-in defect region and an OSF ring region, but has a problem of requiring a heat treatment step of several tens of hours for copper decoration, lacking simplicity, and the like.
Accordingly, an object of the present invention is to provide a method for evaluating a silicon wafer and a method for manufacturing the same, which can evaluate the presence or absence of a crystal defect region of the silicon wafer and the type of the crystal defect region by a simple method with reduced time and cost.
Means for solving the technical problem
In order to solve the above problems, a method for evaluating a silicon wafer according to the present invention is a method for evaluating a silicon wafer sliced from a single crystal silicon ingot grown by the CZ method, characterized in that a generation rate of a thermal donor generated when a thermal donor generating heat treatment is applied to the silicon wafer is measured, and the presence or absence of a crystal defect region or the type of a crystal defect is discriminated on the basis of the generation rate of the thermal donor.
According to the present invention, by applying a heat treatment to a silicon wafer sliced from a single crystal silicon ingot grown by the CZ method while controlling V/G and measuring the rate of generation of a heat donor according to a change in resistivity caused by the application of the heat treatment, the presence or absence of a crystal defect region and the type of crystal defects can be easily evaluated.
The evaluation method of the silicon wafer according to the present invention is preferably: determining a1 st thermal donor generation rate, which is a generation rate of a thermal donor generated at a1 st measurement point on a1 st silicon wafer, when the thermal donor generation heat treatment is applied in a state where the 1 st silicon wafer cut out from the single crystal silicon ingot contains oxygen clusters; determining a2 nd thermal Donor generation rate, which is a generation rate of thermal donors generated at a2 nd measurement point on a2 nd silicon wafer when a Donor elimination (Donor killer) treatment and a thermal Donor generation heat treatment are sequentially performed on a2 nd silicon wafer different from the 1 st silicon wafer; and determining which of the region containing OSF nuclei, the region containing void defects, and the defect-free region corresponds to the 1 st measurement point on the 1 st silicon wafer based on a thermal donor generation rate ratio which is a ratio of the 1 st thermal donor generation rate to the 2 nd thermal donor generation rate. Here, the state of the silicon wafer oxygen-containing cluster refers to a state before the (as-growth) state is generated and the donor elimination treatment is applied to the silicon wafer. The defect-free region refers to a region that does not contain grown-in defects and does not generate an OSF ring after the evaluation heat treatment. As described above, according to the present invention, the presence or absence of the crystal defect region and the type of the crystal defect can be easily evaluated based on the 1 st and 2 nd thermal donor generation rates obtained from the two different wafers having the presence or absence of the donor erase process, respectively.
The evaluation method of the silicon wafer according to the present invention is preferably: determining that the 1 st measurement point on the 1 st silicon wafer is a defect-free region when the thermal donor generation rate ratio is within a1 st rate range; when the thermal donor generation rate ratio is in a2 nd speed range higher than the 1 st speed range, the 1 st measurement point is determined to be a region containing void defects; when the thermal donor generation rate ratio is in a3 rd rate range higher than the 2 nd rate range, the 1 st measurement point is discriminated to be a region containing OSF nuclei. By this discrimination, the OSF ring region, the void defect-containing region, and the defect-free region can be easily determined.
In the present invention, the heat donor generating heat treatment is preferably a heat treatment at 430 ℃ or more, 480 ℃ or less, and 2 hours or more, and 4 hours or less, and more preferably a heat treatment at 450 ℃ for 4 hours. Under these heat treatment conditions, the oxygen clusters are activated, and the presence or absence of a crystal defect region and the type of crystal defects can be evaluated based on the heat donor generation rate.
The evaluation method of the silicon wafer according to the present invention is preferably: judging that the 1 st measurement point on the 1 st silicon wafer is a defect-free region when the thermal donor generation rate ratio is 1.3 or more and less than 1.7 when the thermal donor generation heat treatment is performed at 450 ℃ for 4 hours; when the heat donor generation rate ratio is 1.7 or more and less than 1.9, the 1 st measurement point is determined to be a region containing a void defect; when the heat donor generation rate ratio is 1.9 or more and less than 2.3, the 1 st measurement point is determined to be a region containing OSF nuclei. By this discrimination, the OSF ring region, the void defect-containing region, and the defect-free region can be easily determined.
The evaluation method of the silicon wafer according to the present invention is preferably: the generation speed of the thermal donor is measured at each of a plurality of measurement points provided along the radial direction of the silicon wafer, thereby creating a crystal defect map in the radial direction of the silicon wafer.
The evaluation method of the silicon wafer according to the present invention is preferably: the resistivity of the silicon wafer is measured, the carrier concentration is obtained from an Irvin curve (Irvin curve) on the basis of the resistivity, the heat donor generation amount is obtained from the carrier concentration before and after the heat donor heat treatment, and the heat donor generation rate is obtained from the relationship between the heat donor generation amount and the time of the heat donor heat treatment. In this case, the resistivity of the silicon wafer is preferably measured by a 4-probe method.
Further, the method for manufacturing a silicon wafer according to the present invention is characterized in that the 1 st silicon single crystal ingot is grown by the czochralski method; measuring a generation rate of a thermal donor generated when a thermal donor is applied to an evaluation silicon wafer sliced from the 1 st silicon single crystal ingot to generate a thermal treatment, and determining the presence or absence of a crystal defect region or the type of a crystal defect in the evaluation silicon wafer based on a measurement result of the generation rate of the thermal donor; and adjusting growth conditions for a2 nd silicon single crystal ingot based on the growth conditions for the 1 st silicon single crystal ingot and the results of the determination of the presence or absence of a crystal defect region or the type of crystal defect in the silicon wafer for evaluation, and slicing a silicon wafer for product from the 2 nd silicon single crystal ingot.
According to the method for manufacturing a silicon wafer of the present invention, by adjusting the growth conditions of the 2 nd silicon single crystal ingot, the 2 nd silicon single crystal ingot having a defect-free region can be grown, the 2 nd silicon single crystal ingot having a region containing void defects can be grown, and the 2 nd silicon single crystal ingot having a region containing OSF nuclei can be grown. In the present invention, it is preferable that the pulling rate of the 2 nd silicon single crystal ingot is adjusted as the growth condition of the 2 nd silicon single crystal ingot. Thus, various types of silicon wafers can be separately produced using the evaluation result based on the heat donor generation rate.
In the present invention, it is preferable to subject the silicon wafer for the product to donor elimination treatment. Thus, a silicon wafer product free from the influence of a heat donor can be provided.
Effects of the invention
According to the present invention, it is possible to provide a method for evaluating a silicon wafer and a method for manufacturing the same, which can evaluate the presence or absence of a crystal defect region and the type of a crystal defect in the silicon wafer by a simple method with reduced time and cost.
Drawings
Fig. 1 is a flowchart for explaining a method of manufacturing a silicon wafer according to an embodiment of the present invention.
FIG. 2 is a diagram showing a general relationship between V/G and the type and distribution of crystal defects.
FIG. 3 is a flowchart showing a process for measuring the generation rate of the thermal donor.
Fig. 4 is a flowchart showing a process of determining the presence or absence of a crystal defect region and the type of crystal defect in a wafer.
FIG. 5 is a graph showing the relationship between the heat donor generation rate and the heat donor heat treatment time in the wafer samples A1 to A3 and B1 to B3.
FIG. 6 is a graph showing the results of determining the relationship between the oxygen concentration and the thermal donor generation rate in the OSF ring generation region, the void defect-containing region, and the defect-free region when the thermal donor generation heat treatment is performed at 450 ℃ for 4 hours.
Fig. 7 is a graph showing the results of normalizing the thermal donor generation rate at each measurement point of the wafer without donor erase treatment and the thermal donor generation rate at the same measurement point of the wafer with donor erase treatment in fig. 6.
Detailed Description
Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
Fig. 1 is a flowchart for explaining a method of manufacturing a silicon wafer according to an embodiment of the present invention.
As shown in fig. 1, the method for manufacturing single crystal silicon according to the present embodiment includes: a crystal growth step (S11) for growing a silicon single crystal ingot by the CZ method; a slicing step (S12) for slicing a silicon wafer from a single crystal silicon ingot; a thermal donor generation rate measuring step (S13 YES, S14) of measuring a thermal donor generation rate when a crystal defect region of a silicon wafer needs to be evaluated; a determination step (S15) for determining the presence or absence of a crystal defect region and the type of crystal defect from the measurement result of the heat donor generation rate; and an adjusting step (S16, YES, S17) of adjusting the growth conditions of the single crystal silicon ingot to be grown subsequently based on the determination result of the presence or absence of the crystal defect region and the type of the crystal defect.
Further, the method for manufacturing single crystal silicon according to the present embodiment includes: a donor elimination treatment step (S18) performed when evaluation of the silicon wafer is not required; and a product processing step (S19) of mirror polishing or the like of the silicon wafer after the donor elimination treatment.
The type and distribution of crystal defects contained in a silicon single crystal grown by the CZ method depend on the ratio V/G of the pulling rate V of the silicon single crystal to the temperature gradient G in the crystal in the direction of the pulling axis. Therefore, in order to control the crystal quality in single crystal silicon, it is necessary to accurately control V/G. However, whether or not a silicon single crystal ingot (1 st silicon single crystal ingot) grown under a certain condition has a desired crystal quality is not known unless an actual evaluation of the crystal quality is tried.
Therefore, in the present embodiment, the presence or absence of a crystal defect region and the type of crystal defects in a wafer cut from a single crystal silicon ingot are evaluated. When the presence or absence of the crystal defect region and the type of the crystal defect are evaluated and the result does not satisfy the desired crystal quality, the evaluation result is fed back to the subsequent growth step of the single crystal silicon ingot (the 2 nd single crystal silicon ingot), and the crystal growth conditions such as the crystal pulling rate V are adjusted so as to achieve the desired crystal quality.
FIG. 2 is a diagram showing a general relationship between V/G and the type and distribution of crystal defects.
As shown in fig. 2, when V/G is large, voids become excessive, and void defects, which are aggregates of voids, occur. Void defects are Crystal defects generally referred to as COPs (Crystal ordered particles). On the other hand, when V/G is small, silicon atoms between the lattices are excessively left, and dislocation clusters, which are aggregates of silicon between the lattices, are generated. Therefore, in order to produce a single crystal which does not contain COP or dislocation clusters, V/G must be controlled in both the radial direction and the longitudinal direction (crystal growth direction) of the single crystal.
Since the crystal pulling rate V is constant at any position in the radial direction of the single crystal, it is necessary to construct an appropriate high-temperature region (hot zone) in the chamber in order to make the temperature gradient G in the radial direction fall within a predetermined range. The radial intra-crystal temperature gradient G is controlled by a heat shield provided above the silicon melt, whereby an appropriate hot zone can be constructed in the vicinity of the solid-liquid interface. On the other hand, the temperature gradient G in the longitudinal direction in the crystal depends not only on the hot zone structure but also on the crystal pulling rate V, and therefore, it is necessary to adjust the single crystal pulling rate V. Currently, by strictly controlling the crystal pulling rate V, a single crystal silicon having a diameter of 300mm and containing no COP and dislocation clusters can be mass-produced.
However, the silicon wafer pulled by controlling V/G and not containing COP and dislocation clusters is not homogeneous at all but includes a plurality of regions having different behaviors when subjected to heat treatment. For example, three regions, i.e., an OSF region, a Pv region, and a Pi region, exist between a region where COPs occur and a region where dislocation clusters occur in the order of V/G from large to small.
The OSF region is a region containing plate-like oxide precipitates (OSF nuclei) in a grown state (a state in which no heat treatment is performed after the single crystal growth), and generating OSF when the thermal oxidation treatment is performed at a high temperature of 1000 to 1200 ℃. The Pv region is a region which contains oxygen precipitation nuclei in a grown state and in which oxygen precipitates are likely to be generated when heat treatment is performed at two stages of low temperature and high temperature (e.g., 800 ℃ and 1000 ℃). The Pi region means a region in which oxygen precipitation nuclei are hardly contained in the grown state and oxygen precipitates are hardly generated even by heat treatment.
As described above, V/G is controlled mainly by adjusting the pull rate V. For example, although a wafer mainly including a defect-free region is desired, when a wafer including a region including many void defects and an OSF ring region is manufactured, it is determined that V/G is too large, and the crystal pulling rate V is reduced. On the other hand, although a wafer mainly containing an OSF ring region is desired, when a wafer containing a large number of defect-free regions is produced, it is judged that V/G is too small and the crystal pulling rate V is increased. By adjusting the pulling rate V, a single crystal silicon ingot having desired crystal quality can be produced.
In order to determine whether a single crystal silicon ingot satisfies a desired crystal quality, in the present embodiment, the temporal change of the thermal donor in the silicon wafer sliced from the ingot is measured.
In the CZ method, since the silicon single crystal is grown from a melt of a polycrystalline silicon raw material charged in a quartz crucible by dissolving the raw material, the silicon single crystal generally contains 10 × 1017atoms/cm3(ASTM F-121, 1979) oxygen eluted from a quartz crucible. This oxygen causes crystal defects in the wafer to cause device characteristic defects, but on the other hand, it acts in a complicated manner to increase the strength of the wafer in the device manufacturing process to prevent deformation, or to form oxygen precipitates or the like in the wafer, which have a gettering (gettering) action of capturing heavy metals causing device operation defects.
Generally, the oxygen atoms in silicon are electrically neutral and do not affect the electrical resistance. However, since a silicon single crystal produced by the CZ method is grown in a quartz crucible, it is known that the crystal contains supersaturated oxygen, and when heat treatment is performed at a low temperature of about 450 ℃.
The thermal donor formed by the heat treatment before and after 450 ℃ is affected by the point defect, and the thermal donor generation rate is different depending on the point defect concentration in the vacancy dominant region (COP region, OSF ring region) and the defect-free region. Therefore, in the present embodiment, the presence or absence of a crystal defect region and the type of a crystal defect in a silicon wafer are determined based on the generation rate of a thermal donor generated in the silicon wafer.
In the thermal donor generation rate measuring step (S14), two silicon wafers for evaluation were prepared, which were continuously sliced from the ingot in the slicing step (S12). Two wafers for evaluation are preferably wafers cut out of an ingot by a wire saw and subjected to rough polishing. Then, a thermal donor generation heat treatment process was performed on one wafer (1 st wafer) without previously applying donor erasing treatment, and a thermal donor generation heat treatment was performed on the other wafer (2 nd wafer) after previously applying donor erasing treatment, and the thermal donor generation rate was determined from the change in resistivity of each of the 1 st and 2 nd wafers before and after the thermal donor generation heat treatment.
FIG. 3 is a flowchart showing a process for measuring the generation rate of the thermal donor.
As shown in fig. 3, the heat donor generation rate measuring step (S14) includes: a preparation step (S20) for preparing the 1 st and 2 nd wafers in the production state; a resistivity measuring step (S21) for measuring the resistivity of the 1 st wafer; a thermal donor heat treatment step (S22) of subjecting the 1 st wafer after resistivity measurement to a thermal donor heat treatment; a resistivity measuring step (S23) for measuring the resistivity of the 1 st wafer after the heat donor is subjected to the heat treatment; and a step (S24) of calculating the 1 st thermal donor generation rate from the two measured resistivity values before and after the thermal donor generation heat treatment.
The heat donor generation rate measuring step (S14) includes: a step (S25) of performing donor erase processing on the 2 nd wafer; a resistivity measuring step (S26) for measuring the resistivity of the 2 nd wafer after the donor erase treatment; a thermal donor heat treatment step (S27) of subjecting the second wafer after resistivity measurement to the same thermal donor heat treatment as the first wafer; a resistivity measuring step (S28) for measuring the resistivity of the 2 nd wafer after the heat donor is subjected to the heat treatment; and a step (S29) of calculating the generation rate of the 2 nd thermal donor from the two measured resistivity values before and after the thermal donor generation heat treatment.
The temperature of the heat donor for generating heat treatment is preferably 430-480 ℃, and particularly preferably 450 ℃. The time for the heat donor to perform the heat treatment is preferably 1 to 4 hours, and more preferably 2 to 4 hours. The donor-elimination treatment is a heat treatment performed in an inert gas atmosphere at 600 to 700 ℃ for a short time, for example, about 15 minutes.
The resistivity in the silicon wafer plane can be measured by a so-called 4-probe method. The carrier concentration can be obtained from the euclidean curve from the measured resistivity, the thermal donor generation amount can be obtained from the carrier concentrations before and after the thermal donor generation heat treatment, and the thermal donor generation rate can be obtained from the relationship between the thermal donor generation amount and the time of the thermal donor generation heat treatment.
In the present embodiment, it is preferable that a plurality of measurement points are set along the radial direction of the silicon wafer, resistance measurement is performed at each measurement point, and the generation rate of the thermal donor is calculated from the measurement result. By evaluating the presence or absence of the crystal defect region and the type of crystal defect at each measurement point in this manner, a defect map in the radial direction of the silicon wafer can be created.
Fig. 4 is a flowchart showing a process of determining the presence or absence of a crystal defect region and the type of crystal defect in a wafer.
As shown in fig. 4, in the step of determining the presence or absence of a crystal defect region and the type of crystal defect (S15), the ratio of the 1 st thermal donor generation rate to the 2 nd thermal donor generation rate is calculated (S30); when the value is 1.3 or more and less than 1.7, the defect-free region is discriminated (yes at S31, S34); a region determined to contain a void defect when the number is 1.7 or more and less than 1.9 (S31 NO, S32 YES, S35); when the value is 1.9 or more and less than 2.3, the region is discriminated as a region containing an OSF nucleus (NO at S31, NO at S32, YES at S33, S36). If the value does not fall within any numerical range, the determination is impossible (no at S31, no at S32, no at S33, and S37).
As described above, according to the method for evaluating a silicon wafer of the present embodiment, since the silicon wafer is cut out from a single crystal silicon ingot grown by the CZ method, the generation rate of the thermal donor generated when the thermal donor generation heat treatment is applied to the silicon wafer is measured, and the presence or absence of the crystal defect region or the type of the crystal defect is discriminated based on the generation rate of the thermal donor, the region containing OSF nuclei, the region containing void defects, or the defect-free region can be discriminated easily and in a short time. Further, the evaluation can be performed by a low-temperature heat treatment in a short time without applying copper decoration as in the conventional evaluation method, and the presence or absence of the crystal defect region of the silicon wafer and the type of the crystal defect can be evaluated by a simple method with time and cost reduced.
Further, in the method for manufacturing a silicon wafer according to the present embodiment, the thermal donor generation rate for the evaluation silicon wafer sliced from the previous silicon single crystal ingot is measured, the presence or absence of a crystal defect region or the type of a crystal defect in the evaluation silicon wafer is discriminated based on the measurement result of the thermal donor generation rate, and the growth condition of the subsequent silicon single crystal ingot is adjusted based on the discrimination result, so that the crystal growth condition can be optimized easily.
While the preferred embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the present invention, and these modifications are also included in the scope of the present invention.
For example, in the above embodiment, the 1 st and 2 nd silicon wafers cut out from the silicon single crystal ingot were prepared in the thermal donor generation rate measuring step (S14), and the thermal donor generation heat treatment (S27) was performed after the donor elimination treatment (S25) was performed on the 2 nd wafer to calculate the 2 nd thermal donor generation rate, but the 2 nd thermal donor generation rate calculating step can be omitted in the present invention. That is, the following may be used: the donor annihilation treatment and the thermal donor generation heat treatment were performed on another silicon wafer equivalent to the 2 nd silicon wafer to calculate the 2 nd thermal donor generation rate in advance, and the 2 nd thermal donor generation rate was prepared as a database, and the presence or absence of the crystal defect region and the type of the crystal defect were evaluated by measuring only the 1 st thermal donor generation rate using data read from the database for the 2 nd thermal donor generation rate.
Examples
The influence of the kind of crystal defect on the generation speed of the thermal donor was evaluated. In this evaluation test, a P-type single crystal silicon ingot having a diameter of 300mm and a plane orientation of (100) was grown by the CZ method. At this time, a single crystal silicon ingot was grown so as to contain an OSF ring generation region while controlling V/G. The silicon single crystal ingot has an oxygen concentration of 5X 1017～20×1017atoms/cm3(ASTM F-121, 1979). The single crystal silicon ingot was sliced to obtain two silicon wafer samples a1 and B1 containing an OSF ring generation region. Here, OSF is produced in a ringThe green region refers to a region where an OSF ring is generated after the evaluation of the heat treatment, and refers to a region containing OSF nuclei in a grown state.
Except that the V/G was controlled so as to contain a region having void defects, a silicon single crystal ingot was grown under the same conditions as in samples A1 and B1, and the silicon single crystal ingot was sliced to obtain two silicon wafer samples A2 and B2 each containing a region having void defects.
Except that the V/G was controlled so as to be a defect-free region, a single crystal silicon ingot was produced under the same conditions as in samples a1 and B1, and the single crystal silicon ingot was sliced to obtain two silicon wafer samples A3 and B3 containing defect-free regions.
Then, in order to eliminate the heat donor generated in the crystal growth of the silicon wafer samples B1, B2, B3, donor elimination treatment was performed for 15 minutes under a nitrogen atmosphere at 700 ℃.
Samples A1 to A3 (examples 1 to 3) of silicon wafers prepared from processes without donor elimination treatment and samples B1 to B3 (comparative examples 1 to 3) of silicon wafers prepared from processes with donor elimination treatment were subjected to heat donor generation heat treatment under a nitrogen atmosphere at 450 ℃ to generate heat donors.
According to the method described in JIS H0602: in the resistivity measuring method by the 4-probe method established in 1995, the resistivity of samples a1 to A3 and B1 to B3 of each silicon wafer was measured, and the carrier concentration was determined from the euclidean curve based on the resistivity. Then, the thermal donor generation amount is determined from the carrier concentration before and after the thermal donor generation heat treatment, and the thermal donor generation rate is further determined from the relationship between the heat treatment time and the thermal donor generation amount.
FIG. 5 is a graph showing the relationship between the heat donor generation rate and the heat treatment time of the heat donor in the wafer samples A1 to A3 and B1 to B3, in which the horizontal axis shows the heat treatment time (h) and the vertical axis shows the heat donor generation rate (cm)-3H). And, particularly, the graph satisfies 11X 10 only with the oxygen concentration17atoms/cm3A wafer of conditions (c) and a chart of the summary.
As shown in fig. 5, when the heat treatment time was 4 hours or less, the thermal donor generation rate of the samples having no donor elimination treatment (samples a1, a2, and A3) was higher than that of the samples having donor elimination treatment (samples B1, B2, and B3) in all of the OSF ring generation region, the region having void defects, and the defect-free region. In the case of the donor elimination treatment, the thermal donor generation rates in any regions are the same, while in the case of the non-donor elimination treatment, the thermal donor generation rate is increased in the order of the OSF ring generation region, the void defect-containing region, and the defect-free region. If the heat treatment time exceeds 4 hours, the thermal donor generation rate increases first and then decreases without the donor elimination treatment. On the other hand, in the case of the donor eliminating treatment, the thermal donor generation rate decreased, and after 16 hours, the thermal donor generation rate became the same under all conditions.
FIG. 6 is a graph showing the results of determining the relationship between the oxygen concentration and the thermal donor generation rate in the OSF ring generation region, the void defect-containing region and the defect-free region when the thermal donor generation heat treatment was performed at 450 ℃ for 4 hours, and the horizontal axis shows the oxygen concentration (. times.10)17atoms/cm3) The vertical axis represents the heat donor generation rate (cm)-3/h)。
As shown in fig. 6, the thermal donor generation rate of the wafer without donor elimination treatment (samples a1, a2, A3) was higher than that of the wafer with donor elimination treatment (samples B1, B2, B3) at any oxygen concentration as in fig. 5. In the case of the wafer with donor erase processing, the thermal donor generation rate is the same in any region, whereas in the case of the wafer without donor erase processing, the thermal donor generation rate is increased in the order of the OSF ring generation region, the region containing void defects, and the defect-free region.
FIG. 7 is a graph showing the normalization of the thermal donor generation rates at the measurement points of the non-donor-annihilation-treated wafer to the thermal donor generation rates at the same measurement points of the donor-annihilation-treated wafer in FIG. 6, with the horizontal axis representing the oxygen concentration (. times.10)17atoms/cm3) The vertical axis represents the thermal donor generation rate (standard value).
As shown in fig. 7, the thermal donor generation rate in the defect-free region of the wafer without donor erase treatment was 1.3 times or more and less than 1.7 times the thermal donor generation rate of the wafer with donor erase treatment. The thermal donor generation rate in the void defect-containing region of the wafer without donor erase treatment is 1.7 times or more and less than 1.9 times the thermal donor generation rate of the wafer with donor erase treatment. The thermal donor generation rate in the OSF ring generation region of the wafer without donor elimination treatment is 1.9 times or more but less than 2.3 times the thermal donor generation rate of the wafer with donor elimination treatment.
Description of the reference numerals
S11-crystal growth process, S12-slicing process, S13, S14-thermal donor generation rate measuring process, S15-discrimination process, S16, S17-crystal growth condition adjusting process, S20-wafer preparation process, S21-resistivity measuring process of the 1 st wafer, S22-thermal donor generation heat treatment process of the 1 st wafer, S23-resistivity measuring process of the 1 st wafer, S24-1 st thermal donor generation rate calculating process, S25-donor elimination treatment process of the 2 nd wafer, S26-resistivity measuring process of the 2 nd wafer, S27-thermal donor generation heat treatment process of the 2 nd wafer, S28-resistivity measuring process of the 2 nd wafer, S29-2 nd thermal donor generation rate calculating process.

Claims (14)

1. A method for evaluating a silicon wafer cut out from a silicon single crystal ingot grown by the Czochralski method, the method being characterized in that,
measuring a generation rate of a thermal donor generated when the thermal donor is subjected to the thermal treatment to generate heat, and determining the presence or absence of a crystal defect region or the type of the crystal defect based on the generation rate of the thermal donor,
in the measurement of the generation rate of the thermal donor,
determining a1 st thermal donor generation rate, which is a generation rate of a thermal donor generated at a1 st measurement point on a1 st silicon wafer when the thermal donor generation heat treatment is applied in a state where a1 st silicon wafer sliced from the single crystal silicon ingot contains oxygen clusters,
determining a2 nd thermal donor generation rate, the 2 nd thermal donor generation rate being a generation rate of a thermal donor generated at a2 nd measurement point on a2 nd silicon wafer when a2 nd silicon wafer different from the 1 st silicon wafer is subjected to donor elimination treatment and the thermal donor generation heat treatment in this order,
in the judgment of the presence or absence of the crystal defect region or the type of the crystal defect,
determining which of an OSF nucleus-containing region, a void defect-containing region and a defect-free region corresponds to the 1 st measurement point on the 1 st silicon wafer based on a thermal donor generation rate ratio which is a ratio of the 1 st thermal donor generation rate to the 2 nd thermal donor generation rate,
in the measurement of the generation rate of the thermal donor, the resistivity of the silicon wafer is measured, the carrier concentration is obtained from an euclidean curve based on the resistivity, the generation amount of the thermal donor is obtained from the carrier concentrations before and after the thermal donor generation heat treatment, and the generation rate of the thermal donor is obtained from the relationship between the time of the thermal donor generation heat treatment and the generation amount of the thermal donor.
2. The evaluation method of a silicon wafer according to claim 1, wherein,
the method includes measuring the generation speed of the thermal donor at each of a plurality of measurement points provided along the radial direction of the silicon wafer, thereby creating a crystal defect map of the silicon wafer in the radial direction.
3. The evaluation method of a silicon wafer according to claim 1, wherein,
determining that the 1 st measurement point on the 1 st silicon wafer is a defect-free region when the thermal donor generation rate ratio is within a1 st rate range;
when the heat donor generation rate ratio is in a2 nd rate range higher than the 1 st rate range, the 1 st measurement point on the 1 st silicon wafer is determined to be a region containing a void defect;
and when the thermal donor generation rate ratio is in a3 rd rate range higher than the 2 nd rate range, the 1 st measurement point on the 1 st silicon wafer is discriminated as a region containing OSF nuclei.
4. The evaluation method of a silicon wafer according to claim 1, wherein,
the thermal donor generating heat treatment is a heat treatment at 430 ℃ or higher and 480 ℃ or lower and 2 hours or higher and 4 hours or lower.
5. The evaluation method of a silicon wafer according to claim 1, wherein,
when the thermal donor generation rate ratio is 1.3 or more and less than 1.7 when the thermal donor generation heat treatment is performed at 450 ℃ for 4 hours, it is discriminated that the 1 st measurement point on the 1 st silicon wafer is a defect-free region.
6. The evaluation method of a silicon wafer according to claim 1, wherein,
when the thermal donor generation rate ratio is 1.7 or more and less than 1.9 when the thermal donor generation heat treatment is applied at 450 ℃ for 4 hours, the 1 st measurement point is judged to be a region containing a void defect.
7. The evaluation method of a silicon wafer according to claim 1, wherein,
when the thermal donor generation rate ratio is 1.9 or more and less than 2.3 when the thermal donor generation heat treatment is performed at 450 ℃ for 4 hours, it is judged that the 1 st measurement point is a region containing OSF nuclei.
8. The evaluation method for a silicon wafer according to any one of claims 1 to 7, wherein,
the 1 st and 2 nd silicon wafers are silicon wafers that are cut out continuously from the single crystal silicon ingot.
9. A method for manufacturing a silicon wafer is characterized in that,
growing a1 st monocrystalline silicon ingot by the Czochralski method;
measuring a generation rate of a thermal donor generated when a thermal donor generation heat treatment is applied to an evaluation silicon wafer sliced from the 1 st silicon single crystal ingot, and determining the presence or absence of a crystal defect region or the type of a crystal defect in the evaluation silicon wafer based on a measurement result of the generation rate of the thermal donor;
adjusting growth conditions for a2 nd silicon single crystal ingot based on the growth conditions for the 1 st silicon single crystal ingot and the results of the determination of the presence or absence of a crystal defect region or the type of crystal defect in the silicon wafer for evaluation, and slicing a silicon wafer for product from the 2 nd silicon single crystal ingot,
in the measurement of the generation rate of the thermal donor,
determining a1 st thermal donor generation rate, which is a generation rate of a thermal donor generated at a1 st measurement point on a1 st silicon wafer when the thermal donor generation heat treatment is applied in a state where a1 st silicon wafer sliced from the single crystal silicon ingot contains oxygen clusters,
determining a2 nd thermal donor generation rate, the 2 nd thermal donor generation rate being a generation rate of a thermal donor generated at a2 nd measurement point on a2 nd silicon wafer when a2 nd silicon wafer different from the 1 st silicon wafer is subjected to donor elimination treatment and the thermal donor generation heat treatment in this order,
in the judgment of the presence or absence of the crystal defect region or the type of the crystal defect,
and determining which of the region containing OSF nuclei, the region containing void defects, and the defect-free region corresponds to the 1 st measurement point on the 1 st silicon wafer based on a thermal donor generation rate ratio which is a ratio of the 1 st thermal donor generation rate to the 2 nd thermal donor generation rate.
10. The manufacturing method of a silicon wafer according to claim 9, wherein,
growing the 2 nd silicon single crystal ingot having a defect-free region by adjusting growth conditions of the 2 nd silicon single crystal ingot.
11. The manufacturing method of a silicon wafer according to claim 9, wherein,
growing the 2 nd silicon single crystal ingot having a region containing void defects by adjusting growth conditions of the 2 nd silicon single crystal ingot.
12. The manufacturing method of a silicon wafer according to claim 9, wherein,
growing the 2 nd silicon single crystal ingot having a region containing OSF nuclei by adjusting growth conditions of the 2 nd silicon single crystal ingot.
13. The manufacturing method of a silicon wafer according to any one of claims 9 to 12, wherein,
adjusting a pulling rate of the 2 nd silicon single crystal ingot as a growth condition of the 2 nd silicon single crystal ingot.
14. The manufacturing method of a silicon wafer according to any one of claims 9 to 12, wherein,
the product is subjected to a donor elimination treatment with a silicon wafer.
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