CN109446110A - The continuous U-shaped layout tile caching method of data address can be achieved - Google Patents
The continuous U-shaped layout tile caching method of data address can be achieved Download PDFInfo
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- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
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Abstract
The present invention relates to field of data storage, and in particular to a kind of continuous U-shaped layout tile caching method of achievable data address solves the problems, such as that existing on piece register data storage efficiency is low.The technical solution of the invention is as follows, and a kind of continuous U-shaped layout tile caching method of achievable data address is the following steps are included: four cachings 1) chosen in tile are used as cache blocks, four caching rectangular array arrangements；2) with any caching in four cachings for starting point, read-write sequence successively carries out clockwise or counterclockwise along rectangular array.
Description
Technical field
The present invention relates to field of data storage, and in particular to a kind of continuous U-shaped layout tile of achievable data address is slow
Method is deposited, this method is the storage mode and storage address indexing means of a kind of U-shaped layout.
Background technique
With the development of Computer Architecture, computer gradually forms on piece register-on piece caching-chip external memory
Memory hierarchy.On piece register has the characteristics that data exchange is fastest closest to processor, while also having and holding
Measure the smallest defect.Therefore in lifting tab register working efficiency, the waiting time for reducing on piece register, which becomes, promotes number
According to the effective means of storage efficiency.
In data storage, the isolated problem of focused data is generally required.The data such as image, math matrix are handling certain
When one area data, the data of neighbor address are also possible to be used in a short time, lead to the problem of spatial locality.Traditional
Sequence address access often ignores the spatial locality that data have, and causes on piece register to generate data latency, reduces
The reading efficiency of data.
With the raising that people recognize data spatial locality, correlative study person proposes linear Z-type storage, compared to
Every two row is become continuous subaddressing block on piece block of registers by linear memory, linear Z-type storage mode, but in subaddressing
Biggish address span can be still generated between block, therefore can still generate conflict missing when writing back, and reduce the reading efficiency of data.
Summary of the invention
Present invention aim to address the low problems of existing on piece register data storage efficiency, provide a kind of can be achieved
The continuous U-shaped layout tile caching method of data address.
The technical scheme is that
A kind of continuous U-shaped layout tile caching method of achievable data address, comprising the following steps:
1) four cachings in tile are chosen and are used as cache blocks, four caching rectangular array arrangements；
2) with four caching in it is any caching for starting point, read-write sequence along rectangular array clockwise or counterclockwise successively into
Row.
Further, it in step 2), is cached with the upper left corner in four cachings as starting point.
Further, it in step 2), is cached with the upper left corner in four cachings for starting point, by successively reading and writing clockwise.
Meanwhile the present invention also provides the continuous U-shaped layout tile caching methods of the achievable data address of another kind, including with
Lower step:
1) by 2N×2NCaching be divided into multi-level buffer block, and level cache block includes that four rectangular arrays are arranged
Caching, L2 cache block include the level cache block of four rectangular arrays arrangement, and so on, N grades of cache blocks include four
The N-1 grade cache blocks of rectangular array arrangement, wherein N >=2；
2)2N×2NCaching U-shaped read-write rule it is as follows；
When any level cache blocks are read and write, all grades of internal cache blocks must since any caching of level cache block into
Row read-write, also, in every level-one buffer stopper, any cache blocks in following one level cache blocks are starting point, by clockwise or inverse
Hour hands are successively read and write.
Further, in step 2), the U-shaped read-write rule is specifically included: in every level-one buffer stopper, following one level
Upper left corner cache blocks in cache blocks are starting point.
Further, in step 2), the U-shaped read-write rule is specifically included: in every level-one buffer stopper, following one level
Upper left corner cache blocks in cache blocks are starting point, by successively reading and writing clockwise.
In addition, the present invention also provides the continuous U-shaped layout tile caching method of other achievable data addresses, including with
Lower step；
1) by M × 2N×2NCaching be divided into M 2N×2NCaching；
2) by 2N×2NCaching be divided into multi-level buffer block, and level cache block includes that four rectangular arrays are arranged
Caching, L2 cache block include the level cache block ... ... of four rectangular arrays arrangement, and it is in square that N grades of cache blocks, which include four,
The N-1 grade cache blocks of shape array arrangement, wherein N >=2；
3)2N×2NCaching U-shaped read-write rule it is as follows:
When any level cache blocks are read and write, all grades of internal cache blocks must be since any caching of level cache block
Be written and read, also, in every level-one buffer stopper, any cache blocks in following one level cache blocks be starting point, by clockwise or
It successively reads and writes counterclockwise；
4) M 2N×2NCaching successively carry out sequence read-write.
Further, in step 3), the U-shaped read-write rule is specifically included: in every level-one buffer stopper, following one level
Upper left corner cache blocks in cache blocks are starting point.
Further, in step 3), the U-shaped read-write rule is specifically included: in every level-one buffer stopper, following one level
Upper left corner cache blocks in cache blocks are starting point, by successively reading and writing clockwise.
Compared with prior art, the present invention having following technical effect that
1. the present invention can set totally continuous for the data address in register, reduce when reading address biggishly
Location is crossed over, so that the conflict for reducing cache really lacks problem, improve data transfer efficiency.
2. the method for the present invention for improve in block reading and writing data due to address span it is big caused by cache conflict missing
Problem provides a kind of on piece caching of U-shaped storage layout, and it is all continuous for making the address of all data in entirely caching.
Detailed description of the invention
Fig. 1 is the U-shaped schematic layout pattern one that cache size is 2 × 2；
Fig. 2 is the U-shaped schematic layout pattern two that cache size is 2 × 2；
Fig. 3 is the U-shaped schematic layout pattern three that cache size is 2 × 2；
Fig. 4 is the U-shaped schematic layout pattern four that cache size is 2 × 2；
Fig. 5 is the U-shaped schematic layout pattern that cache size is 4 × 4；
Fig. 6 is the U-shaped schematic layout pattern that cache size is 8 × 8；
Fig. 7 is the U-shaped schematic layout pattern that cache size is 16 × 16；
Fig. 8 is multiple L2 cache block progress sequence read-write schematic diagrames.
Specific embodiment
The contents of the present invention are described in further detail below in conjunction with the drawings and specific embodiments:
A kind of continuous U-shaped layout tile caching method of achievable data address, comprising the following steps:
1) it chooses any four caching in tile and is used as cache blocks, four caching rectangular array arrangements；
2) with any caching in four cachings for starting point, read-write sequence is along clockwise or inverse along four turnings of rectangular array
Hour hands successively carry out.
2 × 2tile caching is as shown in Figure 1, sequence is upper left, upper right, bottom right, lower-left when reading and writing.
2 × 2tile caching is as shown in Fig. 2, sequence is upper left, lower-left, bottom right, upper right when reading and writing.
2 × 2tile caching is as shown in figure 3, sequence is lower-left, upper left, upper right, bottom right when reading and writing.
2 × 2tile caching is as shown in figure 4, sequence is upper right, upper left, lower-left, bottom right when reading and writing.
Meanwhile the present invention also provides the continuous U-shaped layout tile caching methods of second of achievable data address, including with
Lower step:
First by 2N×2NCaching is divided into 42N-1×2N-1Caching, caching in upper left is named as A, and upper right is from caching life
Entitled B, bottom right caching are named as C, and caching in lower-left is obviously D；The son caching of ABCD is drawn in the same manner respectively
Point, until being divided into the level cache block of 2 × 2 sizes.
It is ABCD that this four son cachings, which write back sequence, is respectively written and read the son caching of ABCD in the same manner, and appoint
When level cache block is read and write, all grades of internal cache blocks must be written and read since any caching of level cache block, and
And in every level-one buffer stopper, any cache blocks in following one level cache blocks are starting point, by successively reading clockwise or counterclockwise
It writes.
Meanwhile the continuous U-shaped layout tile caching method of data address can be realized the present invention also provides the third, including with
Lower step:
To 2N×2NTile caching, is divided into 2N/MA 2N×2MRectangle caches, wherein M < N, by each 2N×2MIt draws
It is divided into 2N/MA 2M×2MSon caching, 2N/MA 2M×2MCache blocks write back according to linear sequence, all 2M×2M's
Caching is divided and is read and write in the mode in above-mentioned second method, i.e., caching in upper left is named as A, and upper right caches name certainly
For B, caching in bottom right is named as C, and caching in lower-left is obviously D, and it is ABCD that this four son cachings, which write back sequence, until being divided into
The sequence that writes back of the sub- cache blocks of level cache block 2 × 2, sub- cache blocks is also U-shaped read-write.
The tile of U-shaped storage layout is cached, data buffer storage address calculation, and defining reading and writing data sequence is Umap, in tile
Abscissa is tileX, and ordinate tileY, tileX, tileY and Umap are binary number；It is calculated in tile according to Umap
Corresponding abscissa tileX and ordinate tileY, data buffer storage address are Tileaddr, and Umap [m] represents m of Umap；
For the storage address indexing means of U-shaped layout, include the following steps；
TileY={ Umap [7], Umap [5], Umap [3], Umap [1] }.
TileX={ (Umap [6] ^Umap [7]), (Umap [4] ^Umap [5]), (Umap [2] ^Umap [3]), (Umap
[0]^Umap[1])}。
Tileaddr={ TileY, TileX }.
The calculation method of allocation index can be extended according to the size of tile.
Definition tile be an on piece data buffer storage, address Addr, abscissa tileX, ordinate tileY,
Store up a data, serial number Umap, then during read-write, with U-shaped read-write data the following steps are included:
1) data of continuation address are read and write, the Umap of first data is 0, and hereafter every read-write takes a data Umap to add 1；
2) value of tileX and tileY is calculated using Umap；
TileY={ Umap [7], Umap [5], Umap [3], Umap [1] }.
TileX={ (Umap [6] ^Umap [7]), (Umap [4] ^Umap [5]), (Umap [2] ^Umap [3]), (Umap
[0]^Umap[1])}。
3) it combines tileY and tileX to obtain Addr, data are stored in tile by Addr={ tileY, tileX }
Corresponding address in or data taken out from corresponding address write back.
Embodiment 1
Such as Fig. 1, tile cache size is 2 × 2, secondly U-shaped layout read-write sequence is read and write right using upper left is read and write first
On, bottom right is then read and write, the U-shaped read-write sequence of lower-left is finally read and write.
Embodiment 2
Such as Fig. 5, tile cache size is 4 × 4, and U-shaped layout read-write sequentially uses two layers of U-shaped storage method, single 2 ×
Using the storage mode in embodiment 1 in 2 memory block；Using 2 × 2 pieces of upper left is first stored outside 2 × 2 block, secondly store right
Upper 2 × 2 pieces, 2 × 2 pieces of bottom right is then stored, finally stores the U-shaped read-write mode of 2 × 2 pieces of lower-left.
Embodiment 3
Such as Fig. 6, tile cache size is 8 × 8, U-shaped layout storage order using three layers of U-shaped storage method, single 2 ×
Using the storage mode in embodiment 1 in 2 memory block；4 × 4 memory block is using the storage mode in embodiment 2；4 × 4 deposit
It stores up using 4 × 4 pieces of upper left is first stored outside block, then secondly 4 × 4 pieces of upper right of storage stores 4 × 4 pieces of bottom right, finally stores lower-left
4 × 4 pieces of storage mode.
Embodiment 4
Such as Fig. 7, tile cache size is 16 × 16, and U-shaped layout storage order uses four layers of U-shaped storage method, single 2
Using the storage mode in embodiment 1 in × 2 memory block；4 × 4 memory block is using the storage mode in embodiment 2；8×8
Memory block using the storage mode in embodiment 3；Using 8 × 8 pieces of upper left is first stored outside 8 × 8 memory blocks, upper right is secondly stored
8 × 8 pieces, 8 × 8 pieces of bottom right is then stored, finally stores the storage mode of 8 × 8 pieces of lower-left.
Embodiment 5
As shown in figure 8, the tile caching by 16 × 16 is divided into 44 × 16 rectangular blocks, this four rectangular blocks are write back
Sequence is from top to bottom, the label that sequence is each small rectangle of writing back in 4 × 16 rectangular block, 4 × 16 rectangular block is 4
A 4 × 4 memory block, 4 × 4 memory block is using the storage mode in embodiment 2, the then successively memory block to 44 × 4
Carry out sequential storage.
Claims (9)
1. a kind of continuous U-shaped layout tile caching method of achievable data address, which comprises the following steps:
1) four cachings in tile are chosen and are used as cache blocks, four caching rectangular array arrangements；
2) with any caching in four cachings for starting point, read-write sequence successively carries out clockwise or counterclockwise along rectangular array.
2. the continuous U-shaped layout tile caching method of achievable data address according to claim 1, it is characterised in that:
In step 2), cached with the upper left corner in four cachings as starting point.
3. the continuous U-shaped layout tile caching method of achievable data address according to claim 2, it is characterised in that:
In step 2), cached with the upper left corner in four cachings for starting point, by successively reading and writing clockwise.
4. a kind of continuous U-shaped layout tile caching method of achievable data address, which comprises the following steps:
1) by 2N×2NCaching be divided into multi-level buffer block, and level cache block includes the caching of four rectangular arrays arrangement,
L2 cache block includes the level cache block of four rectangular arrays arrangement, and N grades of cache blocks include four rectangular array arrangements
N-1 grade cache blocks, wherein N >=2；
2)2N×2NThe U-shaped read-write rule of caching is as follows；
When any level cache blocks are read and write, all grades of internal cache blocks must be read since any caching of level cache block
It writes,
Also,
In every level-one buffer stopper, any cache blocks in following one level cache blocks are starting point, are pressed clockwise or counterclockwise successively
Read-write.
5. the continuous U-shaped layout tile caching method of achievable data address according to claim 4, it is characterised in that:
In step 2), the U-shaped read-write rule is specifically included；
In every level-one buffer stopper, the upper left corner cache blocks in following one level cache blocks are starting point.
6. the continuous U-shaped layout tile caching method of achievable data address according to claim 5, it is characterised in that:
In step 2), the U-shaped read-write rule is specifically included；
In every level-one buffer stopper, upper left corner cache blocks in following one level cache blocks are starting point, by successively reading and writing clockwise.
7. a kind of continuous U-shaped layout tile caching method of achievable data address, which comprises the following steps:
1) by M × 2N×2NCaching be divided into M 2N×2NCaching；
2) by 2N×2NCaching be divided into multi-level buffer block, and level cache block includes the caching of four rectangular arrays arrangement,
L2 cache block includes the level cache block of four rectangular arrays arrangement, and N grades of cache blocks include four rectangular array arrangements
N-1 grade cache blocks, wherein N >=2；
3)2N×2NCaching U-shaped read-write rule it is as follows；
When any level cache blocks are read and write, all grades of internal cache blocks must be carried out since any caching of level cache block
Read-write,
Also,
In every level-one buffer stopper, any cache blocks in following one level cache blocks are starting point, are pressed clockwise or counterclockwise successively
Read-write；
4) M 2N×2NCaching successively carry out sequence read-write.
8. the continuous U-shaped layout tile caching method of achievable data address according to claim 7, it is characterised in that:
In step 3), the U-shaped read-write rule is specifically included；
In every level-one buffer stopper, the upper left corner cache blocks in following one level cache blocks are starting point.
9. the continuous U-shaped layout tile caching method of achievable data address according to claim 8, it is characterised in that:
In step 3), the U-shaped read-write rule is specifically included；
In every level-one buffer stopper, upper left corner cache blocks in following one level cache blocks are starting point, by successively reading and writing clockwise.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101241420A (en) * | 2008-03-20 | 2008-08-13 | 杭州华三通信技术有限公司 | Method and memory apparatus for promoting write address incontinuous data storage efficiency |
| CN102103499A (en) * | 2009-12-17 | 2011-06-22 | Arm有限公司 | Forming a windowing display in a frame buffer |
| CN104035894A (en) * | 2014-06-17 | 2014-09-10 | 西安电子科技大学 | Parallel access memory system based on optical interconnection |
| CN104424621A (en) * | 2013-08-30 | 2015-03-18 | Arm有限公司 | Graphics processing systems |
| US20170061682A1 (en) * | 2015-08-27 | 2017-03-02 | Samsung Electronics Co., Ltd. | Rendering method and apparatus |
| CN107590085A (en) * | 2017-08-18 | 2018-01-16 | 浙江大学 | A kind of dynamic reconfigurable array data path and its control method with multi-level buffer |
-
2018
- 2018-10-16 CN CN201811203554.6A patent/CN109446110A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101241420A (en) * | 2008-03-20 | 2008-08-13 | 杭州华三通信技术有限公司 | Method and memory apparatus for promoting write address incontinuous data storage efficiency |
| CN102103499A (en) * | 2009-12-17 | 2011-06-22 | Arm有限公司 | Forming a windowing display in a frame buffer |
| CN104424621A (en) * | 2013-08-30 | 2015-03-18 | Arm有限公司 | Graphics processing systems |
| CN104035894A (en) * | 2014-06-17 | 2014-09-10 | 西安电子科技大学 | Parallel access memory system based on optical interconnection |
| US20170061682A1 (en) * | 2015-08-27 | 2017-03-02 | Samsung Electronics Co., Ltd. | Rendering method and apparatus |
| CN107590085A (en) * | 2017-08-18 | 2018-01-16 | 浙江大学 | A kind of dynamic reconfigurable array data path and its control method with multi-level buffer |
Non-Patent Citations (2)
| Title |
|---|
| E. WES BETHEL,DAVID CAMP,ET.AL: ""Improving Performance of Structured-Memory, Data-Intensive Applications on Multi-core Platforms via a Space-Filling Curve Memory Layout"", 《2015 IEEE INTERNATIONAL PARALLEL AND DISTRIBUTED PROCESSING SYMPOSIUM WORKSHOP》 * |
| 沈琦；郑建国: ""基于精益理念的生产线布局优化研究"", 《山东工业技术》 * |
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