CN109379296A - A kind of chip realizes the method and device of upper CPU protocol massages stratification flow control - Google Patents
A kind of chip realizes the method and device of upper CPU protocol massages stratification flow control Download PDFInfo
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- CN109379296A CN109379296A CN201811247996.0A CN201811247996A CN109379296A CN 109379296 A CN109379296 A CN 109379296A CN 201811247996 A CN201811247996 A CN 201811247996A CN 109379296 A CN109379296 A CN 109379296A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/10—Flow control; Congestion control
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/10—Flow control; Congestion control
- H04L47/24—Traffic characterised by specific attributes, e.g. priority or QoS
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L67/00—Network arrangements or protocols for supporting network services or applications
- H04L67/50—Network services
- H04L67/56—Provisioning of proxy services
- H04L67/568—Storing data temporarily at an intermediate stage, e.g. caching
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- Data Exchanges In Wide-Area Networks (AREA)
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Abstract
Present invention discloses the method and devices that a kind of chip realizes upper CPU protocol massages stratification flow control, the method includes the multiple DMA channels of poll, when being polled to current DMA channel has message to send and have sending permission, message is sent, until all DMA channels are all without sending permission；If current DMA channel does not have message to need to send, other channels are transferred to the sending permission of the DMA channel.The present invention is realized solves the problems, such as that low priority message is hungry to death under the premise of guaranteeing that high priority message obtains larger communication bandwidth.
Description
Technical field
The present invention relates to a kind of flow control techniques of upper CPU protocol massages, realize upper CPU more particularly, to a kind of chip
The method and device of protocol massages stratification flow control.
Background technique
DMA (direct memory access, direct memory access (DMA)) refer to external equipment not by CPU directly with
Installed System Memory exchanges the interfacing of data, is a kind of mechanism of fast transfer of data, is realized by dma controller.
Existing dma controller uses strict priority flow control methods to the DMA channel of different priorities, i.e., high preferential
The DMA channel of grade preferentially sends message, and higher priority channel message can send lower priority after being all sent completely
The message in channel.But the stringent according to priority scheduling mode of this multi-channel DMA, very likely occur when communication flows is larger
Low priority message is blocked the phenomenon that (hungry to death) completely.
Summary of the invention
It is an object of the invention to overcome the deficiencies of existing technologies, a kind of upper CPU protocol massages level of chip realization is provided
Change the method and device of flow control.
To achieve the above object, the following technical solutions are proposed by the present invention: a kind of upper CPU protocol massages stratification of chip realization
The method of flow control, comprising:
S0 increases a buffer area message amount field and packet accouter word to each DMA channel in dma controller
Section configures the buffer area message amount and initializes the corresponding packet accouter in each channel according to the priority in channel；
S1, judges whether the buffer area message amount of current first passage is greater than 0, if more than S2 is then entered step,
S4 is entered step if being less than；
S2, judges whether the packet accouter of presently described first passage is greater than 0, if more than message is then sent and will be current
The packet accouter of the first passage subtracts 1, and enters step S3；
Current first passage is added 1, the lower second channel of poll by S3；
S4, selects that buffer area message is most in rest channels and the relatively high third channel of priority sends message, and will
The packet accouter of presently described first passage subtracts 1, the packet accouter of the third channel is added 1, and enter step S3；
S5, until the packet accouter in all channels is 0, then return step S0 reconfigures initial value.
Preferably, in S1, message amount that the buffer area message amount is stored by chip according to channel current buffer
It is configured.
Preferably, in S1, the higher corresponding packet accouter initial value in channel of initialization priority is bigger, conversely, report
Literary counter initial value is smaller.
Preferably, in S4, buffer area message is most in selection rest channels and the relatively high third channel of priority is sent
The process of message includes: the buffer area message amount successively compared in channel with the sequence of priority from high to low, is buffered
The channel that area's message is most and priority is relatively high.
Preferably, the selection higher channel of priority continues to compare when the buffer area message amount is equal.
The present invention also provides another technical solutions: a kind of upper CPU protocol massages stratification flow control of chip realization
The device of system, comprising:
Initialization module, for increasing a buffer area message amount field and report to each DMA channel in dma controller
Literary counter field configures the buffer area message amount and initializes the corresponding message in each channel according to the priority in channel
Counter；
Whether buffer area message amount judgment module, the buffer area message amount for judging current first passage are big
In 0, if more than packet accouter judgment module is then entered, dynamic adjustment module is entered if being less than；
Packet accouter judgment module, for judging whether the packet accouter of presently described first passage is greater than 0, if greatly
In then sending message and subtract 1 for the packet accouter of presently described first passage, and enter the lower channel module of poll；
The lower channel module of poll, for current first passage to be added 1, the lower second channel of poll；
Dynamic adjustment module, for selecting in rest channels buffer area message most and the relatively high third channel of priority
Message is sent, and the packet accouter of presently described first passage is subtracted 1, the packet accouter of the third channel is added 1, and
Into the lower channel module of poll；
Initially reset module then returns to initialization module and reconfigures after being 0 for the packet accouter in all channels
Initial value.
Preferably, the initialization module configures corresponding buffering area report according to the message amount that channel current buffer stores
Literary quantity.
Preferably, the initialization module initializes the higher corresponding packet accouter initial value in channel of priority more
Greatly, conversely, packet accouter initial value is smaller.
Preferably, the dynamic adjustment module successively compares the report of the buffer area in channel with the sequence of priority from high to low
Literary quantity obtains the channel that buffer area message is most and priority is relatively high.
Preferably, when the dynamic adjustment module compares buffer area message amount, buffer area message amount is then selected when equal
The higher channel of priority is selected to continue to compare.
The beneficial effects of the present invention are: the present invention passes through the transmission route according to current communication flows feature to DMA channel
Limit carries out dynamic adjustment, realizes the reasonable disposition of resource, on the one hand avoids the resource for the DMA channel that no message needs to send
Waste；On the other hand, it is transferred to the longest DMA channel of buffer queue by the way that right will be sent, packet accouter value can be made
Smaller i.e. priority is lower, but the biggish channel of portfolio sends more messages, thus guaranteeing the acquisition of high priority message
Solve the problems, such as that low priority message is hungry to death under the premise of larger communication bandwidth.
Detailed description of the invention
Fig. 1 is the flow diagram of the method for the present invention；
Fig. 2 is the schematic illustration of apparatus of the present invention.
Specific embodiment
Below in conjunction with attached drawing of the invention, clear, complete description is carried out to the technical solution of the embodiment of the present invention.
A kind of disclosed chip realizes the method and device of upper CPU protocol massages stratification flow control, leads to
It crosses and dynamic adjustment is carried out to the sending permission of DMA channel, realize before guaranteeing that high priority message obtains larger communication bandwidth
It puts and solves the problems, such as that low priority message is hungry to death.
Referring to figs. 1 and 2, a kind of disclosed chip realizes upper CPU protocol massages stratification flow control
The method of system, comprising the following steps:
S0 increases a buffer area message amount field and packet accouter word to each DMA channel in dma controller
Section configures buffer area message amount and initializes the corresponding packet accouter in each channel according to the priority in channel.
Wherein, buffer area message amount field (BufMsgNum) is used for the message amount of recording channel buffer area, i.e. basis
The message amount of each channel current buffer storage is configured；Packet accouter field (Cnt) is for identifying the excellent of channel
First grade indicates that the DMA channel sends the weighted value of message.In the present embodiment, initial configuration packet accouter, according to channel
Priority initializes the corresponding packet accouter in each channel, and the corresponding packet accouter initial value in the higher channel of priority is more
Greatly, conversely, packet accouter initial value is smaller.If a dma controller has 4 DMA channels, the current of each DMA channel is delayed
The message amount for rushing area's storage is respectively 4,2,3,2, the priority of 4 DMA channels sequentially from high to low, in this way, when initialization,
The buffer area message amount of 4 DMA channels is configured to 4,2,3,2, and packet accouter can successively be initialized as 4,2,1,0,
That is there is the permission of 2 messages in permission of the channel 4 configured with 4 transmission messages, channel 3, and there is 1 transmission message in channel 2
Permission, channel 1 then without send message permission.Start to be polled between multiple DMA channels after the completion of initialization, enter
Below step S1.
S1, judges whether the buffer area message amount (BufMsgNum) of current first passage (chanX) is greater than 0, if more than
S2 is then entered step, enters step S4 if being equal to 0.
Judge that current channel needs to send either with or without message, if it is greater than 0, then it represents that the channel has message to need to send out
It send, is transferred to below step S2；If being equal to 0, then it represents that the channel does not have message to need to send, then enters step S4.With above-mentioned
For example, as current channel be channel 4, corresponding buffer area message amount be 4, that is, be greater than 0, indicate that message needs to send out
It send, so into following step S2.
S2, judges whether the packet accouter (Cnt) of current first passage is greater than 0, if more than then sending message and will work as
The packet accouter of preceding first passage subtracts 1, and enters step S3, is directly entered step S3 if being equal to 0.
I.e. after above-mentioned S1 judges to obtain currently (chanX) and has message needs transmission, continue to judge channel X either with or without hair
Permission is sent, sending permission is indicated if it is greater than 0, then sends message.After message is sent completely, by current channel X
Packet accouter subtract 1 (chanX Cnt-1), and step S3 is gone successively to, into the poll in next channel.Work as equal to 0 explanation
Prepass X does not have sending permission, then is directly entered step S3, into the poll in next channel.All DMA channel packet accouters
After being kept to 0, reconfiguring packet accouter is initial value.
Current first passage is added 1 (chanX+1), the lower second channel of poll by S3.
I.e. according to above-mentioned steps S1 and S2, the next second channel of poll, next second channel here also just at
Current first passage in above-mentioned steps S1 and S2.
S4, selects that buffer area message is most in rest channels and the relatively high third channel of priority (chanY) sends report
Text, and the packet accouter of current first passage is subtracted 1 (chanX Cnt-1), the packet accouter of third channel is added 1
(chanY Cnt+1), and enter step S3.
Even current first passage X does not have message to need to send, then sending permission is transferred buffer area in other channels
Message number longest and the higher channel Y of priority.In the present embodiment, by successively comparing it with the sequence of priority from high to low
Buffer area message amount in remaining channel, if when channel buffer message amount is equal, then selecting priority in comparison procedure
Compared with higher channel is continued with other channels, the channel that buffer area message is most and priority is relatively high is obtained, i.e., will be worked as
The transmission right of the preceding first passage sent without message is transferred to the longest third channel Y of buffer queue.And by current
The packet accouter of one channel X subtracts 1, while the packet accouter of third channel Y is added 1.
S5, until the packet accouter in all channels is 0, then return step S0 reconfigures initial value.
That is, when all channels all without message sending permission after, then to packet accouter according to step S0 carry out
It reinitializes.
To sum up, the present invention is primarily based on chip and realizes weighted round-robin scheduling algorithm (WRR), specifically as above-mentioned: initialization
Configuration message counter indicates that the DMA channel sends the weighted value of message, when being polled to current DMA channel and having message transmission,
Packet accouter, which is greater than 0, just sending permission, is sent completely rear packet accouter and subtracts 1, all DMA channel packet accouters are kept to
After 0, it is reconfigured for initial value.
Secondly, it is preferable that dynamic adjustment is carried out according to sending permission of the current communication flows feature to DMA channel,
Said chip increases dynamic adjustment module on the basis of realizing weighted round-robin scheduling algorithm, realizes resource by transfer sending permission
Reasonable disposition.It is specifically as above-mentioned: if current DMA channel X does not have message to need to send, by comparing each channel buffer message
Worth next channel Y out of quantity (BufMsgNum), subtracts 1 for the packet accouter of current channel X, the message meter in next channel
Number device adds 1, that is, it is longest next logical to realize that the transmission right for the current channel X that no message is sent is transferred to buffer queue
Road.The advantage is: on the one hand avoiding no message and the DMA channel sent is needed to result in waste of resources, due to all channels
Packet accouter, which is kept to 0, can just reinitialize, and not adjust packet accouter when if not sending message, can hinder to count and think highly of
New initialization, to never have sending permission after causing other channel counters to be kept to 0；On the other hand, the message meter of channel Y
Number device adds 1, i.e., will send right and be transferred to the longest DMA channel of buffer queue, packet accouter value can be made smaller i.e. excellent
First grade is lower, but the biggish channel of portfolio sends more messages.
As shown in Fig. 2, a kind of revealed upper CPU protocol massages stratification flow control of chip realization of the embodiment of the present invention
Device, comprising:
Initialization module, for increasing a buffer area message amount field and report to each DMA channel in dma controller
Literary counter field configures the buffer area message amount and initializes the corresponding message in each channel according to the priority in channel
Counter.
Whether buffer area message amount judgment module, the buffer area message amount for judging current first passage are big
In 0, if more than packet accouter judgment module is then entered, dynamic adjustment module is entered if being less than.
Packet accouter judgment module, for judging whether the packet accouter of presently described first passage is greater than 0, if greatly
In then sending message and subtract 1 for the packet accouter of presently described first passage, and enter the lower channel module of poll.
The lower channel module of poll, for current first passage to be added 1, the lower second channel of poll.
Dynamic adjustment module, for selecting in rest channels buffer area message most and the relatively high third channel of priority
Message is sent, and the packet accouter of presently described first passage is subtracted 1, the packet accouter of the third channel is added 1, and
Into the lower channel module of poll.
Initially reset module then returns to initialization module and reconfigures after being 0 for the packet accouter in all channels
Initial value.
Above-mentioned initialization module, buffer area message amount judgment module, packet accouter judgment module, the lower channel of poll
The working principle of module, dynamic adjustment module and initially reset module can refer to the statement of above-mentioned steps S0~S5, here no longer
It repeats.
Technology contents and technical characteristic of the invention have revealed that as above, however those skilled in the art still may base
Make various replacements and modification without departing substantially from spirit of that invention, therefore, the scope of the present invention in teachings of the present invention and announcement
It should be not limited to the revealed content of embodiment, and should include various without departing substantially from replacement and modification of the invention, and be this patent Shen
Please claim covered.
Claims (10)
1. a kind of method that chip realizes upper CPU protocol massages stratification flow control, which is characterized in that the described method includes:
S0 increases a buffer area message amount field and packet accouter field to each DMA channel in dma controller, matches
It sets the buffer area message amount and the corresponding packet accouter in each channel is initialized according to the priority in channel；
S1, judges whether the buffer area message amount of current first passage is greater than 0, if more than S2 is then entered step, if waiting
S4 is entered step in 0；
S2, judges whether the packet accouter of presently described first passage is greater than 0, if more than message is then sent and will be presently described
The packet accouter of first passage subtracts 1, and enters step S3, is directly entered step S3 if being equal to 0；
Current first passage is added 1, the lower second channel of poll by S3；
S4, selects that buffer area message is most in rest channels and the relatively high third channel of priority sends message, and will be current
The packet accouter of the first passage subtracts 1, the packet accouter of the third channel is added 1, and enter step S3；
S5, until the packet accouter in all channels is 0, then return step S0 reconfigures initial value.
2. the method according to claim 1, wherein the buffer area message amount is by chip according to logical in S1
The message amount of road current buffer storage is configured.
3. the method according to claim 1, wherein initializing the higher corresponding report in channel of priority in S1
Literary counter initial value is bigger, conversely, packet accouter initial value is smaller.
4. the method according to claim 1, wherein in S4, select in rest channels buffer area message at most and
It includes: successively to be compared in channel with the sequence of priority from high to low that the relatively high third channel of priority, which sends the process of message,
Buffer area message amount, obtain the channel that buffer area message is most and priority is relatively high.
5. according to the method described in claim 4, it is characterized in that, when the buffer area message amount is equal select priority compared with
Continue to compare in high channel.
6. the device that a kind of chip realizes upper CPU protocol massages stratification flow control, which is characterized in that described device includes:
Initialization module, by giving each DMA channel to increase based on a buffer area message amount field and message in dma controller
Number device field configures the buffer area message amount and initializes the corresponding packet counting in each channel according to the priority in channel
Device；
Buffer area message amount judgment module, for judging whether the buffer area message amount of current first passage is greater than 0,
If more than packet accouter judgment module is then entered, dynamic adjustment module is entered if being less than；
Packet accouter judgment module, for judging whether the packet accouter of presently described first passage is greater than 0, if more than then
It sends message and the packet accouter of presently described first passage is subtracted 1, and enter the lower channel module of poll；
The lower channel module of poll, for current first passage to be added 1, the lower second channel of poll；
Dynamic adjustment module, for selecting, buffer area message is most in rest channels and the relatively high third channel of priority is sent
Message, and the packet accouter of presently described first passage is subtracted 1, the packet accouter of the third channel is added 1, and enter
The lower channel module of poll；
Initially reset module then returns to initialization module and reconfigures initially after being 0 for the packet accouter in all channels
Value.
7. device according to claim 6, which is characterized in that the initialization module is stored according to channel current buffer
Message amount configure corresponding buffering area message amount.
8. device according to claim 6, which is characterized in that the higher channel of the initialization module initialization priority
Corresponding packet accouter initial value is bigger, conversely, packet accouter initial value is smaller.
9. device according to claim 6, which is characterized in that dynamic adjustment module is with priority from high to low suitable
Sequence successively compares the buffer area message amount in channel, obtains the channel that buffer area message is most and priority is relatively high.
10. device according to claim 9, which is characterized in that the dynamic adjustment module compares buffer area message amount
When, then select the higher channel of priority to continue to compare when buffer area message amount is equal.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111970271A (en) * | 2020-08-14 | 2020-11-20 | 苏州盛科科技有限公司 | Preemptive scheduling method and device for TSN (transport stream network) message |
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Application publication date: 20190222 |