CN109244076A - 3D memory device - Google Patents
3D memory device Download PDFInfo
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- CN109244076A CN109244076A CN201811026959.7A CN201811026959A CN109244076A CN 109244076 A CN109244076 A CN 109244076A CN 201811026959 A CN201811026959 A CN 201811026959A CN 109244076 A CN109244076 A CN 109244076A
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- 239000004065 semiconductor Substances 0.000 claims description 109
- 238000009413 insulation Methods 0.000 claims description 22
- 238000010276 construction Methods 0.000 claims description 19
- 239000000126 substance Substances 0.000 claims description 19
- 229910052760 oxygen Inorganic materials 0.000 claims description 9
- 239000001301 oxygen Substances 0.000 claims description 9
- 239000004020 conductor Substances 0.000 claims description 8
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- 239000011229 interlayer Substances 0.000 claims description 7
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- 238000003860 storage Methods 0.000 description 18
- 238000000231 atomic layer deposition Methods 0.000 description 16
- 229920002120 photoresistant polymer Polymers 0.000 description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 14
- 229910052710 silicon Inorganic materials 0.000 description 14
- 239000010703 silicon Substances 0.000 description 14
- 238000004519 manufacturing process Methods 0.000 description 12
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- 238000000151 deposition Methods 0.000 description 9
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- 230000005641 tunneling Effects 0.000 description 8
- 230000008021 deposition Effects 0.000 description 7
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
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- 229920005591 polysilicon Polymers 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 3
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
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- Semiconductor Memories (AREA)
Abstract
Disclosing a kind of 3D memory device includes: nucleus, and the nucleus has channel hole；Auxiliary area, the auxiliary area include virtual aperture and/or groove；The 3D memory device is substrate along the bottom perpendicular to the 3D memory device surface direction, wherein the bottom in the channel hole has an epitaxial layer, and the bottom of the virtual aperture and/or groove has oxide skin(coating).The problems such as embodiment of the present invention forms oxide skin(coating) in the virtual aperture of auxiliary area and/or groove, and epitaxial layer is formed in the channel hole of nucleus, and solution forms uneven epitaxial layer bring epitaxial layer and current leakage.
Description
Technical field
The present invention relates to memory technology fields, in particular to 3D memory device.
Background technique
The raising of the storage density of memory device and the progress of semiconductor fabrication process are closely related.With semiconductors manufacture
The characteristic size of technique is smaller and smaller, and the storage density of memory device is higher and higher.In order to further increase storage density,
Develop the memory device (that is, 3D memory device) of three-dimensional structure.3D memory device includes along the multiple of vertical direction stacking
Storage unit can double up integrated level on the chip of unit area, and can reduce cost.
3D memory device includes the nucleus to form storage unit and the auxiliary area for forming peripheral structure.It is stored in 3D
In device, such as 3D nand flash memory, the channel hole bottom of nucleus is needed again to form epitaxial layer.During this, some
Auxiliary area, for example, stepped area (Stair Step, SS) virtual aperture (Dummy Hole) and run through array contact
Bottom groove (Trench) in (Through Array Contact, TAC) area's barrier (barrier) is also opening, because
This can form epitaxial layer in such as virtual aperture (Dummy Hole) and channel bottom together.
Groove at virtual aperture and TAC barrier is different from the diameter in channel hole and height, causes epitaxial layer uneven
The problems such as even and current leakage.
Summary of the invention
In view of the above problems, it the purpose of the present invention is to provide a kind of 3D memory device, can solve due in auxiliary region
Domain forms the problems such as uneven epitaxial layer bring epitaxial layer and current leakage.
According to an aspect of the present invention, a kind of 3D memory device is provided, comprising:
Nucleus, the nucleus have channel hole；
Auxiliary area, the auxiliary area include virtual aperture and/or groove；
The 3D memory device is substrate along the bottom perpendicular to the 3D memory device surface direction, wherein the ditch
The bottom in road hole has epitaxial layer, and the bottom of the virtual aperture and/or groove has oxide skin(coating).
Preferably, the auxiliary area includes stepped area and has in array contact region, the stepped area
The virtual aperture, it is described that there is the groove in array contact region.
Preferably, to all have barrier insulating layer-electric charge capture layer-tunnelling in the channel hole, virtual aperture and groove exhausted
Edge layer-channel layer-dielectric substance layer structure.
Preferably, when oxide skin(coating) is formed on the bottom of the virtual aperture and the groove, the channel hole is closing
's.
Preferably, when epitaxial layer is formed on the bottom in the channel hole, the virtual aperture and the groove are closed.
Preferably, the channel hole extends to the underlying substrate of the semiconductor structure, and in the semiconductor structure
The first groove of certain depth is formed in substrate.
Preferably, the epitaxial layer is formed in first groove.
Preferably, the virtual aperture and the groove extend to the underlying substrate of the semiconductor structure, and described
The second groove of certain depth is formed in the substrate of semiconductor structure.
Preferably, the oxide skin(coating) is formed in the second groove.
Preferably, the nucleus includes laminated construction, and the laminated construction includes that multiple interlayers for being alternately stacked are exhausted
Edge layer and multiple sacrificial layers.
3D memory device provided by the invention, forms oxide skin(coating) in the virtual aperture of auxiliary area and/or groove, in core
Epitaxial layer is formed in the channel hole in heart district domain, solve due to auxiliary area formed epitaxial layer bring epitaxial layer it is uneven and
The problems such as current leakage.
Further, oxide skin(coating), then the shape in channel hole are first formed in virtual aperture and/groove by same mask layer
At epitaxial layer, technology difficulty is simplified.
Further, epitaxial layer is first formed in channel hole by same mask layer, then is formed in virtual aperture and/groove
Oxide skin(coating) simplifies technology difficulty.
Detailed description of the invention
By referring to the drawings to the description of the embodiment of the present invention, above-mentioned and other purposes of the invention, feature and
Advantage will be apparent from, in the accompanying drawings:
Fig. 1 shows the flow chart of the manufacturing method of 3D memory device according to a first embodiment of the present invention；
Fig. 2A-Fig. 2 L shows cutting for manufacturing method each stage of 3D memory device according to a first embodiment of the present invention
Face figure；
Fig. 3 shows the flow chart of the manufacturing method of 3D memory device according to another embodiment of the present invention；
Fig. 4 A- Fig. 4 L shows cutting for manufacturing method each stage of 3D memory device according to a first embodiment of the present invention
Face figure.
Specific embodiment
The various embodiments that the present invention will be described in more detail that hereinafter reference will be made to the drawings.In various figures, identical element
It is indicated using same or similar appended drawing reference.For the sake of clarity, the various pieces in attached drawing are not necessarily to scale.
With reference to the accompanying drawings and examples, specific embodiments of the present invention will be described in further detail.
" top " described in the present invention refers to positioned at the top of base plan, can refer to directly connecing between material
Touching is also possible to interval setting.
Fig. 1 shows the flow chart of the manufacturing method of 3D memory device according to a first embodiment of the present invention.Fig. 2A-Fig. 2 M
Show the sectional view in manufacturing method each stage of 3D memory device according to a first embodiment of the present invention.
In step s 102, semiconductor structure is provided.
This semiconductor structure is at least part that will be used for structure of the follow-up process to ultimately form 3D memory device.
Semiconductor structure may include nucleus and auxiliary area, wherein nucleus is the region for including storage unit, auxiliary area
It is the region for including peripheral structure.
In the sectional view of the semiconductor structure shown in Fig. 2A, semiconductor structure 200a includes nucleus 210, stepped region
Domain 220 and run through region array contact (TAC) 230.Nucleus 210 is used to form storage array, and stepped area 220 is used for
Interconnection is formed, the region TAC 230 is used to form through array barrier structure (Through Array Barrier, TAB).It needs to refer to
Out, the layout of nucleus 210, stepped area 220 and the region TAC 230 in figure not necessarily indicates these areas in reality
Position in the 3D memory device on border.
Nucleus 210, stepped area 220 and the region TAC 230 can have common substrate 201.The material of substrate 201
For example, silicon.Laminated construction 240 and insulation system 250 are equipped on substrate 201, laminated construction 240 covers core space 210,
Insulation system 250 covers stepped area 220 and the region TAC 230.The insulation system 250 is for example made of silica.
Laminated construction 240 includes the multiple interlayer insulating films 241 and multiple sacrificial layers 242 being alternately stacked, sacrificial layer 242
Conductor layer will be substituted for.In the present embodiment, interlayer insulating film 241 is for example made of silica, and sacrificial layer 242 is for example by nitrogenizing
Silicon composition can successively served as a contrast using chemical vapor deposition (CVD), atomic layer deposition (ALD) or other suitable deposition methods
On bottom 201 replace deposited metal between dielectric substance layer (such as: silica) and metal substitute sacrificial layer (such as: silicon nitride).
Dielectric layer 260 and the first hard mask layer 270 are additionally provided on laminated construction 240 and the insulation system 250.Medium
Layer 260 is for example made of silica, and the first hard mask layer 270 is for example made of silicon nitride.
Although there is described herein the exemplary composition of initial semiconductor structure, it is to be understood that, one or more features
It can be omitted, substitute or increase to from this semiconductor structure in this semiconductor structure.In addition, each layer illustrated
Material be only exemplary, such as the material of substrate 201 can also be other siliceous substrates, such as SOI (insulator
Upper silicon), SiGe, Si:C etc..
In step S104, the semiconductor structure is etched to form channel hole in nucleus, is formed in auxiliary area
Virtual aperture and/or groove.
Here, by with along with lithographic process in the nucleus and auxiliary area of semiconductor structure be distributed to form channel
Hole, virtual aperture and groove.When auxiliary area includes stepped area 220, virtual aperture can be formed.When auxiliary area includes TAC
When region 230, groove can be formed.When auxiliary area includes stepped area 220 and the region 230 TAC, virtual aperture can be formed simultaneously
And groove.
In this step, the process of photoetching can be various known appropriate steps.For example, growth hard mask layer, covering
It is exposed after photoresist layer, then performs etching, cleans.
In the sectional view of the semiconductor structure exemplified by Fig. 2 B, have in the nucleus 210 of semiconductor structure 200b
Multiple channel holes 211.The first hard mask layer 270, dielectric layer 260 and laminated construction 240 are run through in each channel hole 211, reach lining
Bottom 201 forms the first groove of certain depth.There are multiple virtual apertures 221 in stepped area 220；Have in the region TAC 230
Multiple grooves 231.Each virtual aperture 221 and groove 231 run through the first hard mask layer 270, dielectric layer 260 and insulation system
250, substrate 201 is reached, the second groove of certain depth is formed.
In step s 106, confining bed is formed on the semiconductor structure to close the channel hole, the virtual aperture
And/or groove.
In the present embodiment, on the semiconductor structure with high rate deposition closed material to form confining bed 280, institute
It states confining bed 280 and closes the channel hole 211, virtual aperture 221 and groove 231.The confining bed 280 is for example by silica
Composition.
In step S108, the second hard mask layer is covered on the confining bed.
In the present embodiment, the second hard mask layer 290 of covering is so as at the subsequent bottom for being directed to virtual aperture and/or groove respectively
Bottom the formation oxide skin(coating), epitaxial layer in portion, channel hole.
In the sectional view of the semiconductor structure exemplified by Fig. 2 C, the surface of semiconductor structure 200c covers confining bed
280 and second hard mask layer 290.The second hard mask layer 290 may include amorphous carbon layer (for example, APFM (A-C)) and anti-reflective herein
Penetrate dielectric coated (for example, silicon oxynitride (SiON)).It will be understood, however, that the second hard mask layer 290 can choose other materials
Material.The number of plies of second hard mask layer 290 can also change, such as the second hard mask layer 290 can only have one layer or more than being equal to
Two layers.
In step s 110, second hard mask layer and the confining bed positioned at auxiliary area are etched to expose
State virtual aperture and/or groove.
The sectional view of the semiconductor structure exemplified by Fig. 2 D-2E illustrates the process of this step, first in semiconductor junction
The surface of structure 200c covers photoresist layer 300, is exposed by the photomask for the auxiliary area, then through over etching,
Photoresist pattern needed for being formed, obtains semiconductor structure 200d, wherein the photoresist layer 300 includes photoresist coating (Photo
Resist Coating, PR)；Later, by 290 He of the second hard mask layer of photoresist pattern etch on semiconductor structure 200d
Positioned at the confining bed 280 of the auxiliary area and to expose the virtual aperture 221 and/or groove 231, semiconductor junction is obtained
Structure 200e, the confining bed 280 only closes the channel hole 211 of the nucleus 210 at this time.
Dry method is also carried out in a preferred embodiment, after etching to remove photoresist (Asher) and wet-cleaning (WET
Clean)。
In step S112, oxide skin(coating) is formed in the bottom of the virtual aperture and the groove.
In the sectional view of the semiconductor structure exemplified by Fig. 2 F, the deposition oxide in semiconductor structure 200e, such as
Silica.The oxide of the deposition is filled into the virtual aperture 221 of stepped area 220 and/or the groove 231 in the region TAC 230
In, specifically, the oxide of the deposition is filled into the second groove, to form semiconductor structure 200f.Form the oxygen
The method of compound layer is, for example, that situ steam generates (In-Situ Steam Generation, ISSG), thermal oxide (Thermal
) or atomic layer deposition (Atomic Layer Deposition, ALD) etc. Oxidation.
In step S114, removal is located at the confining bed of the nucleus to expose the channel hole.
In the sectional view of the semiconductor structure exemplified by Fig. 2 G, removal be located at the nucleus confining bed 280 with
The channel hole 211 is exposed, then wet-cleaning (WET Clean) is carried out, to form semiconductor structure 200g.Removal institute
The method for stating the confining bed 280 of nucleus may, for example, be planarization, such as chemical mechanical grinding (CMP).
In step S116, epitaxial layer is formed in the bottom in the channel hole.
In the sectional view of the semiconductor structure exemplified by Fig. 2 H, in the ditch of the nucleus 210 of semiconductor structure 200g
The bottom in road hole forms epitaxial layer and specifically forms epitaxial layer in the first groove, to form semiconductor structure 200h.Institute
The material for stating epitaxial layer is, for example, silicon.The mode for forming epitaxial layer may, for example, be selective epitaxial growth (Selective
Epitaxial Growth, SEG).
It further include that step S118 (not shown) and step S120 (do not show in figure in a preferred embodiment
Out).
In step S118, barrier insulating layer-electric charge capture is sequentially formed in the channel hole, virtual aperture and groove
Layer-tunneling insulation layer-channel layer-dielectric substance layer, selected material can be oxidenitride oxide-polysilicon-oxygen
The single layer and/or multiple layer combination structure of compound, but not limited to this material and combination that place refers to.
In the forming process of 3D storage component part, in addition to the epitaxial layer of each 211 bottom of channel hole, each virtual aperture 221 with
And outside the oxide skin(coating) of each groove 231, also other can be executed for each channel hole 211, each virtual aperture 221 and each groove 231
Technique.
In the sectional view of the semiconductor structure exemplified by Fig. 2 I, for example, can also be formed in channel hole 211 along its side wall
Form oxidenitride oxide-polysilicon-oxide (ONOPO) structure from outside to inside.To 211 bottom of channel hole
ONOPO structure perform etching, until leaking out epitaxial layer 212 and over etching 212 certain depth of epitaxial layer, partly led to be formed
Body structure 200i.
Wherein, the ONOPO structure sequentially formed from outside to inside is respectively barrier insulating layer 213, electric charge capture layer
214, tunneling insulation layer 215, channel layer 216 and dielectric substance layer 217.Layer 213,214 and 215 constitutes accumulation layer.Fig. 2 I's
In example, the exemplary materials of barrier insulating layer 213 and tunneling insulation layer 215 are silica, electric charge capture layer 214 it is exemplary
Material is silicon nitride, forms oxide-nitride-oxide (ONO) structure；216 exemplary materials of channel layer are polysilicon.But
It is appreciated that these layers can choose other materials.For example, the material of barrier insulating layer 213 may include high K (dielectric constant)
Oxide layer；Electric charge capture layer 214 can be floating gate structure, for example including polycrystalline silicon material；The material of channel layer 216 can be with
Including the semiconductor materials such as monocrystalline silicon, monocrystalline germanium, SiGe, Si:C, SiGe:C, SiGe:H.The exemplary material of dielectric substance layer 217
Material is silica.
In the sectional view of the semiconductor structure exemplified by Fig. 2 J, masking oxide layer 217 is removed in channel hole 211, so
Semiconductor material growing (e.g. polycrystalline silicon growth) is carried out afterwards, to make channel layer 216 be connected to epitaxial layer 212, to be formed
Semiconductor structure 200j.This step would generally form channel layer in semicon-ductor structure surface together.
In the technique executed for each channel hole, filled layer 218 can be also formed in channel hole 211, exemplified by Fig. 2 K
In the sectional view of semiconductor structure, in each channel hole 211 of the core space 210 of semiconductor structure 200j, filling is formed respectively
Layer 218.The exemplary materials of filled layer 218 are silica.Forming 218 method of filled layer is, for example, atomic layer deposition.Filled layer
218 are filled with each channel hole 211.So far, terminate for technique performed by channel hole 211.
Similarly, it can also be formed in virtual aperture 221 and sequentially form oxide-nitride-oxygen from outside to inside along its side wall
Compound-polysilicon-oxide (ONOPO) structure.The ONOPO structure of 221 bottom of virtual aperture is performed etching, until leaking out oxygen
Compound layer 222 and over etching 222 certain depth of oxide skin(coating), to form semiconductor structure 200i.It is described from outside to inside according to
The ONOPO structure of secondary formation is respectively barrier insulating layer 223, electric charge capture layer 224, tunneling insulation layer 225, channel layer 226
And dielectric substance layer 227.The dielectric substance layer 227 in virtual aperture 221 is removed, it is (e.g. more then to carry out semiconductor material growing
Crystal silicon growth), to make channel layer 226 be connected to oxide skin(coating) 222, to form semiconductor structure 200j.This step would generally
Channel layer is formed in semicon-ductor structure surface together.Filled layer 228 can also be formed by also being formed in virtual aperture 221, filled layer 228
Exemplary materials are silica.Forming 228 method of filled layer is, for example, atomic layer deposition.Filled layer 228 is filled with each virtual aperture
221.So far, terminate for technique performed by virtual aperture 221.
Similarly, it can also be formed in groove 231 and sequentially form oxide-nitride-oxidation from outside to inside along its side wall
Object-polysilicon-oxide (ONOPO) structure.The ONOPO structure of 231 bottom of groove is performed etching, until leaking out oxide
Layer 232 and over etching 232 certain depth of oxide skin(coating), to form semiconductor structure 200i.The successively shape from outside to inside
At ONOPO structure be respectively barrier insulating layer 233, electric charge capture layer 234, tunneling insulation layer 235, channel layer 236 and be situated between
Electric matter layer 237.The dielectric substance layer 237 in groove 231 is removed, then carrying out semiconductor material growing, (e.g. polysilicon is raw
It is long), to make channel layer 236 be connected to oxide skin(coating) 232, to form semiconductor structure 200j.This step would generally exist together
Semicon-ductor structure surface forms channel layer.Filled layer 238 can also be formed by also being formed in groove 231, the exemplary material of filled layer 238
Material is silica.Forming 238 method of filled layer is, for example, atomic layer deposition.Filled layer 238 is filled with each groove 231.So far, needle
Technique performed by groove 231 is terminated.
In the step s 120, the sacrificial layer in the laminated construction for being located at nucleus is replaced by conductor layer.
In the sectional view of the semiconductor structure shown in figure L, the sacrificial layer 241 in laminated construction 240 is replaced by conductor
Layer 243, to obtain semiconductor structure 200l.
The manufacturing method of 3D memory device provided by the invention, forms oxygen in the virtual aperture of auxiliary area and/or groove
Compound layer forms epitaxial layer in the channel hole of nucleus, solves due to forming epitaxial layer bring extension in auxiliary area
The problems such as layer is uneven and current leakage.
Further, oxide skin(coating), then the shape in channel hole are first formed in virtual aperture and/groove by same mask layer
At epitaxial layer, technology difficulty is simplified.
Fig. 3 shows the flow chart of the manufacturing method of 3D memory device according to another embodiment of the present invention；Fig. 4 A- Fig. 4 K
Show the sectional view in manufacturing method each stage of 3D memory device according to a first embodiment of the present invention.
In step s 302, semiconductor structure is provided.
This semiconductor structure is at least part that will be used for structure of the follow-up process to ultimately form 3D memory device.
Semiconductor structure may include nucleus and auxiliary area, wherein nucleus is the region for including storage unit, auxiliary area
It is the region for including peripheral structure.
In the sectional view of the semiconductor structure shown in Fig. 4 A, semiconductor structure 400a includes nucleus 410, stepped region
Domain 420 and run through region array contact (TAC) 430.Nucleus 410 is used to form storage array, and stepped area 420 is used for
Interconnection is formed, the region TAC 430 is used to form through array barrier structure (Through Array Barrier, TAB).It needs to refer to
Out, the layout of nucleus 410, stepped area 420 and the region TAC 430 in figure not necessarily indicates these areas in reality
Position in the 3D memory device on border.
Nucleus 410, stepped area 420 and the region TAC 430 can have common substrate 401.The material of substrate 401
For example, silicon.Laminated construction 440 and insulation system 450 are equipped on substrate 401, laminated construction 440 covers core space 410,
Insulation system 450 covers stepped area 420 and the region TAC 430.The insulation system 450 is for example made of silica.
Laminated construction 440 includes the multiple interlayer insulating films 441 and multiple sacrificial layers 442 being alternately stacked, sacrificial layer 442
Conductor layer will be substituted for.In the present embodiment, interlayer insulating film 441 is for example made of silica, and sacrificial layer 442 is for example by nitrogenizing
Silicon composition can successively be existed using chemical vapor deposition (CVD), atomic layer deposition (ALD) or other suitable deposition methods
On substrate 401 replace deposited metal between dielectric substance layer (such as: silica) and metal substitute sacrificial layer (such as: silicon nitride).
Dielectric layer 460 and the first hard mask layer 470 are additionally provided on laminated construction 440 and the insulation system 450.Medium
Layer 460 is for example made of silica, and the first hard mask layer 470 is for example made of silicon nitride.
Although there is described herein the exemplary composition of initial semiconductor structure, it is to be understood that, one or more features
It can be omitted, substitute or increase to from this semiconductor structure in this semiconductor structure.In addition, each layer illustrated
Material be only exemplary, such as the material of substrate 401 can also be other siliceous substrates, such as SOI (insulator
Upper silicon), SiGe, Si:C etc..
In step s 304, the semiconductor structure is etched to form channel hole in nucleus, is formed in auxiliary area
Virtual aperture and/or groove.
Here, by with along with lithographic process in the nucleus and auxiliary area of semiconductor structure be distributed to form channel
Hole, virtual aperture and groove.When auxiliary area includes stepped area 420, virtual aperture can be formed.When auxiliary area includes TAC
When region 430, groove can be formed.When auxiliary area includes stepped area 420 and the region 430 TAC, virtual aperture can be formed simultaneously
And groove.
In this step, the process of photoetching can be various known appropriate steps.For example, growth hard mask layer, covering
It is exposed after photoresist layer, then performs etching, cleans.
In the sectional view of the semiconductor structure exemplified by Fig. 4 B, have in the nucleus 410 of semiconductor structure 400b
Multiple channel holes 411.The first hard mask layer 470, dielectric layer 460 and laminated construction 440 are run through in each channel hole 411, reach lining
Bottom 401 forms the first groove of certain depth.There are multiple virtual apertures 421 in stepped area 420；Have in the region TAC 430
Multiple grooves 431.Each virtual aperture 421 and groove 431 run through the first hard mask layer 470, dielectric layer 460 and insulation system
450, substrate 401 is reached, the second groove of certain depth is formed.
In step S306, confining bed is formed on the semiconductor structure to close the channel hole, the virtual aperture
And/or groove.
In the present embodiment, on the semiconductor structure with high rate deposition closed material to form confining bed 480, institute
It states confining bed 480 and closes the channel hole 411, virtual aperture 421 and groove 431.The confining bed 480 is for example by silica
Composition.
In step S308, the second hard mask layer is covered on the confining bed.
In the present embodiment, the second hard mask layer 490 of covering is so as at the subsequent bottom for being directed to virtual aperture and/or groove respectively
Bottom the formation oxide skin(coating), epitaxial layer in portion, channel hole.
In the sectional view of the semiconductor structure exemplified by Fig. 4 C, the surface of semiconductor structure 400c covers confining bed
480 and second hard mask layer 490.The second hard mask layer 490 may include amorphous carbon layer (for example, APFM (A-C)) and anti-reflective herein
Penetrate dielectric coated (for example, silicon oxynitride (SiON)).It will be understood, however, that the second hard mask layer 490 can choose other materials
Material.The number of plies of second hard mask layer 490 can also change, such as the second hard mask layer 490 can only have one layer or more than being equal to
Two layers.
In step s310, second hard mask layer and the confining bed positioned at nucleus are etched to expose
State channel hole.
The sectional view of the semiconductor structure exemplified by Fig. 4 D-4E illustrates the process of this step, first in semiconductor junction
The surface of structure 400c covers photoresist layer 500, is exposed by the photomask for the auxiliary area, then through over etching,
Photoresist pattern needed for being formed, obtains semiconductor structure 400d, wherein the photoresist layer 500 includes photoresist coating (Photo
Resist Coating, PR)；Later, by 490 He of the second hard mask layer of photoresist pattern etch on semiconductor structure 400d
Positioned at the confining bed 480 of the nucleus and to expose the channel hole 411, semiconductor structure 400e is obtained, at this time institute
State virtual aperture 421 and/or groove 431 that confining bed 480 only closes the auxiliary area.
Dry method is also carried out in a preferred embodiment, after etching to remove photoresist (Asher) and wet-cleaning (WET
Clean)。
In step S312, epitaxial layer is formed in the bottom in the channel hole.
In the sectional view of the semiconductor structure exemplified by Fig. 4 F, in the ditch of the nucleus 410 of semiconductor structure 400e
The bottom in road hole forms epitaxial layer and specifically forms epitaxial layer in the first groove, to form semiconductor structure 400f.Institute
The material for stating epitaxial layer is, for example, silicon.The mode for forming epitaxial layer may, for example, be selective epitaxial growth (Selective
Epitaxial Growth, SEG).
In step S314, removal is located at the confining bed of the auxiliary area to expose the virtual aperture and/or groove.
In the sectional view of the semiconductor structure exemplified by Fig. 4 G, removal be located at the auxiliary area confining bed 480 with
The virtual aperture 421 and/or groove 431 are exposed, then wet-cleaning (WET Clean) is carried out, to form semiconductor junction
Structure 400g.The method for removing the confining bed 480 of the auxiliary area may, for example, be planarization, such as chemical mechanical grinding
(CMP)。
In step S316, oxide skin(coating) is formed in the bottom of the virtual aperture and the groove.
In the sectional view of the semiconductor structure exemplified by Fig. 4 H, oxygen is deposited in the auxiliary area of semiconductor structure 400g
Compound, such as silica.The oxide of the deposition is filled into virtual aperture 421 and/or the region TAC 430 of stepped area 420
Groove 431 in, specifically, the oxide of the deposition is filled into the second groove, to form semiconductor structure 400h.Shape
Method at the oxide skin(coating) is, for example, that situ steam generates (In-Situ Steam Generation, ISSG), thermal oxide
(Thermal Oxidation) or atomic layer deposition (Atomic Layer Deposition, ALD) etc..
It further include that step S318 (not shown) and step S320 (do not show in figure in a preferred embodiment
Out).
In step S318, barrier insulating layer-electric charge capture is sequentially formed in the channel hole, virtual aperture and groove
Layer-tunneling insulation layer-channel layer-dielectric substance layer, selected material can be oxidenitride oxide-polysilicon-oxygen
The single layer and/or multiple layer combination structure of compound, but not limited to this material and combination that place refers to.In 3D storage component part
In forming process, other than the oxide skin(coating) of the epitaxial layer of each 411 bottom of channel hole, each virtual aperture 421 and each groove 431,
Also other techniques can be executed for each channel hole 411, each virtual aperture 421 and each groove 431.
In the sectional view of the semiconductor structure exemplified by Fig. 4 I, for example, can also be formed in channel hole 411 along its side wall
Form oxidenitride oxide-polysilicon-oxide (ONOPO) structure from outside to inside.To 411 bottom of channel hole
ONOPO structure performs etching, until simultaneously over etching 412 certain depth of epitaxial layer of epitaxial layer 412 is leaked out, to form semiconductor
Structure 400i.
Wherein, the ONOPO structure sequentially formed from outside to inside is respectively barrier insulating layer 413, electric charge capture layer
414, tunneling insulation layer 415, channel layer 416 and dielectric substance layer 417.Layer 413,414 and 415 constitutes accumulation layer.Fig. 4 I's
In example, the exemplary materials of barrier insulating layer 413 and tunneling insulation layer 415 are silica, electric charge capture layer 414 it is exemplary
Material is silicon nitride, forms oxide-nitride-oxide (ONO) structure；416 exemplary materials of channel layer are polysilicon.But
It is appreciated that these layers can choose other materials.For example, the material of barrier insulating layer 413 may include high K oxide layer；Electricity
Lotus capture layer 414 can be floating gate structure, for example including polycrystalline silicon material；The material of channel layer 416 may include monocrystalline
The semiconductor materials such as silicon, monocrystalline germanium, SiGe, Si:C, SiGe:C, SiGe:H.The exemplary materials of dielectric substance layer 417 are oxidation
Silicon.
In the sectional view of the semiconductor structure exemplified by Fig. 4 J, masking oxide layer 417 is removed in channel hole 411, so
Semiconductor material growing (e.g. polycrystalline silicon growth) is carried out afterwards, to make channel layer 416 be connected to epitaxial layer 412, to be formed
Semiconductor structure 400j.This step would generally form channel layer in semicon-ductor structure surface together.
In the technique executed for each channel hole, filled layer 418 can be also formed in channel hole 411, exemplified by Fig. 4 K
In the sectional view of semiconductor structure, in each channel hole 411 of the core space 410 of semiconductor structure 400j, filling is formed respectively
Layer 418.The exemplary materials of filled layer 418 are silica.Forming 418 method of filled layer is, for example, atomic layer deposition.Filled layer
418 are filled with each channel hole 411.So far, terminate for technique performed by channel hole 411.
Similarly, it can also be formed in virtual aperture 421 and sequentially form oxide-nitride-oxygen from outside to inside along its side wall
Compound-polysilicon-oxide (ONOPO) structure.The ONOPO structure of 421 bottom of virtual aperture is performed etching, until leaking out oxygen
Compound layer 422 and over etching 422 certain depth of oxide skin(coating), to form semiconductor structure 400i.It is described from outside to inside according to
The ONOPO structure of secondary formation is respectively barrier insulating layer 423, electric charge capture layer 424, tunneling insulation layer 425, channel layer 426
And dielectric substance layer 427.The dielectric substance layer 427 in virtual aperture 421 is removed, it is (e.g. more then to carry out semiconductor material growing
Crystal silicon growth), to make channel layer 426 be connected to oxide skin(coating) 422, to form semiconductor structure 400j.This step would generally
Channel layer is formed in semicon-ductor structure surface together.Filled layer 428 can also be formed by also being formed in virtual aperture 421, filled layer 428
Exemplary materials are silica.Forming 428 method of filled layer is, for example, atomic layer deposition.Filled layer 428 is filled with each virtual aperture
421.So far, terminate for technique performed by virtual aperture 421.
Similarly, it can also be formed in groove 431 and sequentially form oxide-nitride-oxidation from outside to inside along its side wall
Object-polysilicon-oxide (ONOPO) structure.The ONOPO structure of 431 bottom of groove is performed etching, until leaking out oxide
Layer 432 and over etching 432 certain depth of oxide skin(coating), to form semiconductor structure 400i.The successively shape from outside to inside
At ONOPO structure be respectively barrier insulating layer 433, electric charge capture layer 434, tunneling insulation layer 435, channel layer 436 and be situated between
Electric matter layer 437.The dielectric substance layer 437 in groove 431 is removed, then carrying out semiconductor material growing, (e.g. polysilicon is raw
It is long), to make channel layer 436 be connected to oxide skin(coating) 432, to form semiconductor structure 400j.This step would generally exist together
Semicon-ductor structure surface forms channel layer.Filled layer 438 can also be formed by also being formed in groove 431, the exemplary material of filled layer 438
Material is silica.Forming 438 method of filled layer is, for example, atomic layer deposition.Filled layer 438 is filled with each groove 431.So far, needle
Technique performed by groove 431 is terminated.
In step s 320, the sacrificial layer in the laminated construction for being located at nucleus is replaced by conductor layer.
In the sectional view of the semiconductor structure shown in figure L, the sacrificial layer 241 in laminated construction 240 is replaced by conductor
Layer 443, to obtain semiconductor structure 400l.
The manufacturing method of 3D memory device provided by the invention, forms oxygen in the virtual aperture of auxiliary area and/or groove
Compound layer forms epitaxial layer in the channel hole of nucleus, solves due to forming epitaxial layer bring extension in auxiliary area
The problems such as layer is uneven and current leakage.
Further, oxide skin(coating), then the shape in channel hole are first formed in virtual aperture and/groove by same mask layer
At epitaxial layer, technology difficulty is simplified.
Flow chart has been used to be used to illustrate operation performed by method according to an embodiment of the present application herein.It should be understood that
, the operation of front not necessarily accurately carries out in sequence.On the contrary, various steps can be handled according to inverted order or simultaneously
Suddenly.Meanwhile or during other operations are added to these, or from these processes remove a certain step or number step operation.For example, certain
A little steps are not necessarily, it is convenient to omit, or replace with other steps.
Above-described embodiment is formed by semiconductor structure, and using subsequent conventional steps, three-dimensional storage can be obtained
Part.
With reference to shown in Fig. 2 L and Fig. 4 L, a kind of three-dimensional storage part according to an embodiment of the invention, it may include core space
Domain (210/410), stepped area (220/420) and run through array contact region (230/430).There is channel hole in nucleus
(211/411), there is virtual aperture (221/421) in stepped area, it is described that there is groove (231/ in array contact region
431).Three-dimensional storage part is substrate (201/401) along the bottom perpendicular to three-dimensional storage part surface direction, wherein the ditch
The bottom in road hole (211/411) has the bottom tool of epitaxial layer, the virtual aperture (221/421) and/or groove (231/431)
There is oxide skin(coating).The auxiliary area includes stepped area (220/420) and runs through array contact region (230/430).It is described
Barrier insulating layer-electric charge capture is all had in channel hole (211/411), virtual aperture (221/421) and groove (231/431)
Layer-tunneling insulation layer-channel layer-dielectric substance layer structure.In the virtual aperture (221/421) and the groove (231/431)
Bottom formed oxide skin(coating) when, the channel hole (211/411) is closed.In the bottom of the channel hole (211/411)
When forming epitaxial layer, the virtual aperture (221/421) and the groove (231/431) are closed.The channel hole (211/
411) underlying substrate (201/401) of the semiconductor structure is extended to, and forms one in the substrate of the semiconductor structure
First groove of depthkeeping degree.The epitaxial layer is formed in first groove.The virtual aperture (221/421) and the ditch
Slot (231/431) extends to the underlying substrate (201/401) of the semiconductor structure, and in the substrate of the semiconductor structure
Form the second groove of certain depth.The oxide skin(coating) is formed in the second groove.Nucleus (210/410) packet
It includes laminated construction (240/440), the laminated construction (240/440) includes the multiple interlayer insulating films (241/ being alternately stacked
And multiple conductor layers (243/443) 441).
3D memory device provided by the invention, forms oxide skin(coating) in the virtual aperture of auxiliary area and/or groove, in core
Epitaxial layer is formed in the channel hole in heart district domain, solve due to auxiliary area formed epitaxial layer bring epitaxial layer it is uneven and
The problems such as current leakage.
Other details of three-dimensional storage part, such as structure, the periphery interconnection of storage array etc., and the weight of non-present invention
Point, herein not reinflated description.
In the context of the present invention, three-dimensional storage part can be 3D flash memory, such as 3DNAND flash memory.
It is as described above according to the embodiment of the present invention, these embodiments details all there is no detailed descriptionthe, also not
Limiting the invention is only the specific embodiment.Obviously, as described above, can make many modifications and variations.This explanation
These embodiments are chosen and specifically described to book, is principle and practical application in order to better explain the present invention, thus belonging to making
Technical field technical staff can be used using modification of the invention and on the basis of the present invention well.The present invention is only by right
The limitation of claim and its full scope and equivalent.
Claims (10)
1. a kind of 3D memory device, comprising:
Nucleus, the nucleus have channel hole；
Auxiliary area, the auxiliary area include virtual aperture and/or groove；
The 3D memory device is substrate along the bottom perpendicular to the 3D memory device surface direction, wherein the channel hole
Bottom there is epitaxial layer, the bottom of the virtual aperture and/or groove has oxide skin(coating).
2. 3D memory device according to claim 1, wherein the auxiliary area includes stepped area and connects through array
Region is touched, there is the virtual aperture in the stepped area, it is described that there is the groove in array contact region.
3. 3D memory device according to claim 1, wherein all have resistance in the channel hole, virtual aperture and groove
Keep off insulating layer-electric charge capture layer-tunneling insulation layer-channel layer-dielectric substance layer structure.
4. 3D memory device according to claim 1, wherein form oxygen in the bottom of the virtual aperture and the groove
When compound layer, the channel hole is closed.
5. 3D memory device according to claim 1, wherein described when epitaxial layer is formed on the bottom in the channel hole
Virtual aperture and the groove are closed.
6. 3D memory device according to claim 1, wherein the channel hole extends to the bottom of the semiconductor structure
Substrate, and in the substrate of the semiconductor structure formed certain depth the first groove.
7. 3D memory device according to claim 6, wherein the epitaxial layer is formed in first groove.
8. 3D memory device according to claim 1, wherein the virtual aperture and the groove, which extend to, described partly leads
The underlying substrate of body structure, and in the substrate of the semiconductor structure formed certain depth the second groove.
9. 3D memory device according to claim 8, wherein the oxide skin(coating) is formed in the second groove.
10. 3D memory device according to claim 1, wherein the nucleus includes laminated construction, the lamination knot
Structure includes the multiple interlayer insulating films being alternately stacked and multiple conductor layers.
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