CN108110040A - Power semiconductor and its manufacturing method - Google Patents
Power semiconductor and its manufacturing method Download PDFInfo
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- CN108110040A CN108110040A CN201711061805.7A CN201711061805A CN108110040A CN 108110040 A CN108110040 A CN 108110040A CN 201711061805 A CN201711061805 A CN 201711061805A CN 108110040 A CN108110040 A CN 108110040A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 383
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 58
- 229920005591 polysilicon Polymers 0.000 claims description 46
- 239000000463 material Substances 0.000 claims description 8
- 230000000149 penetrating effect Effects 0.000 claims description 6
- 239000004020 conductor Substances 0.000 claims description 2
- 230000000994 depressogenic effect Effects 0.000 claims description 2
- 238000000034 method Methods 0.000 description 20
- 230000002441 reversible effect Effects 0.000 description 16
- 230000000694 effects Effects 0.000 description 9
- 238000011084 recovery Methods 0.000 description 9
- 238000002347 injection Methods 0.000 description 7
- 239000007924 injection Substances 0.000 description 7
- 210000000746 body region Anatomy 0.000 description 5
- 230000005684 electric field Effects 0.000 description 5
- 238000000605 extraction Methods 0.000 description 5
- 239000012535 impurity Substances 0.000 description 5
- 230000002708 enhancing effect Effects 0.000 description 4
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- 230000008901 benefit Effects 0.000 description 3
- 239000000969 carrier Substances 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 3
- 230000005611 electricity Effects 0.000 description 3
- 230000007246 mechanism Effects 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 238000004088 simulation Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
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- 238000010586 diagram Methods 0.000 description 2
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- 230000004048 modification Effects 0.000 description 2
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- 230000009467 reduction Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
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- 238000005086 pumping Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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Abstract
The invention discloses power semiconductor and its manufacturing method, wherein the power semiconductor includes：The first semiconductor region has the first conduction type；At least one second semiconductor regions, are arranged in the first semiconductor region, and the surface of the second semiconductor regions is flushed with the surface of the first semiconductor region, and the second semiconductor regions have second conduction type opposite with the first conduction type；First insulating layer is arranged on the surface of the first semiconductor region and the second semiconductor regions；Position on first insulating layer corresponding to the second semiconductor regions is provided at least one opening；Position in the surface of second semiconductor regions corresponding to opening is formed at least one sunk area, and sunk area is the semi-conducting material with the first conduction type.The power semiconductor that the embodiment of the present invention is provided can shorten the length in lateral resistance area while surface temperature is reduced, so as to reduce the size of power semiconductor.
Description
Technical field
The present invention relates to technical field of semiconductors, and in particular to power semiconductor and its manufacturing method.
Background technology
Power semiconductor needs have processing high voltage, the ability of high current.Figure 1A and Figure 1B is respectively with diode
To be illustrated Longitudinal cross section schematic of the existing power semiconductor when bearing forward bias and reverse biased, wherein 100
It is P-doped zone for N-type substrate, 200,300 be first electrode, and 400 be insulating layer, and 500 be second electrode.In lateral position
On, first electrode 300 is known as active area with the part that P-doped zone 200 contacts；First electrode 300 connects with P-doped zone 200
The lateral edges of tactile edge to P-doped zone 200 are known as lateral resistance area, and lateral resistance area can be equivalent to resistance R；Active area
It is known as termination environment with the part outside lateral resistance area.
As shown in Figure 1A, when first electrode 300 plus positive voltage, second electrode 500 plus negative voltage (during forward conduction),
The how sub- hole of P-doped zone 200 flows to N-doped zone 100 by the edge of P-doped zone 200, in 100 shape of N-doped zone
Into excess holes (i.e. excess carriers).Since the doping concentration on 200 surface of P-doped zone is higher, resistance is smaller, p-type doping
The hole of 200 lateral edges of area (lateral edges are position shown in thick line in Figure 1A and Figure 1B, and dotted arrow show hole path)
The surface can be collected in and flow into N-doped zone 100 (lateral hole injection also referred to as occurs).
As shown in Figure 1B, when first electrode 300 plus negative voltage, second electrode 500 plus positive voltage (during Reverse recovery),
The excess holes of N-doped zone 100 flows into P-doped zone 200, is further extracted by first electrode 300.Also due to p-type
The doping concentration on 200 surface of doped region is higher, resistance is smaller, and the hole of 200 near side edges of P-doped zone can be collected in the table
Surface current enters P-doped zone 200.The voltage difference of electrode is higher during due to Reverse recovery, and carrier during Reverse recovery gathers
Effect is more prominent so that the surface temperature of P-doped zone 200 is higher than other regions；And the superfluous current-carrying that moment is extracted
Son is more, and temperature is higher.
During forward conduction, if the length in lateral resistance area is shorter, not even zero (not having lateral resistance area), then due to P
100 surface dopant concentration of type doped region is higher, resistance is smaller, and the pressure drop for causing first electrode 300 to lateral edges is smaller so that PN
Junction bias is larger, has and pours in N-doped zone 100 by lateral edges compared with multi-hole；Longer lateral resistance area enables to
The pressure drop of one electrode 300 to lateral edges increases, and PN junction bias reduces at lateral edges, and moment pours in N-doped zone by lateral edges
100 number of cavities is reduced, so as to reduce the lateral injection of carrier.
During Reverse recovery, the right end that lateral resistance area is equivalent to resistance R of the hole current shown in Figure 1B flows to left end,
So that the voltage of right end forms self-biasing effect higher than left end namely lateral resistance area, specifically, since first electrode 300 is
Negative voltage, second electrode 500 are positive voltage, then lateral edges and the voltage difference of second electrode 500 are less than first electrode 300 and second
The voltage difference of electrode 500.Set lateral resistance region that can reduce the reverse biased of PN junction at lateral edges and reduce side as a result,
The electric field strength of edge so that the number of cavities that moment is reversed extraction is reduced, so as to reduce the table in reversely restoring process
The temperature in face.The length in lateral resistance area is longer, and self-biasing effect is stronger, and the number of cavities that moment is reversed extraction is fewer, instead
Into recovery process, the temperature on the surface is lower.
Therefore, to solve the temperature on the surface of P-doped zone 200, in the prior art usually by the horizontal stroke in lateral resistance area
It is made longer to length, moment pours in the number of cavities of N-doped zone 100 by lateral edges, reduction moment is reversed to reduce
The electric field strength of PN junction at the number of cavities and lateral edges of extraction.However, the length in lateral resistance area is longer, power semiconductor
The size of device entirety is bigger.For example, the high-voltage diode for being currently used for 3.3kV, the width in lateral resistance area reach
Hundred even hundreds of microns.
The content of the invention
In view of this, it is existing to solve an embodiment of the present invention provides a kind of power semiconductor and its manufacturing method
Power semiconductor larger-size problem for reduction device surface temperature.
First aspect present invention provides a kind of power semiconductor, including：The first semiconductor region has first
Conduction type；At least one second semiconductor regions, are arranged in the first semiconductor region, and second semiconductor
The surface in region is flushed with the surface of the first semiconductor region, and second semiconductor regions have and the described first conduction
The second opposite conduction type of type；First insulating layer is arranged on the first semiconductor region and second semiconductor region
On the surface in domain；Position on first insulating layer corresponding to second semiconductor regions is provided at least one open
Mouthful；Position in the surface of second semiconductor regions corresponding to the opening is formed at least one sunk area,
The sunk area is the semi-conducting material with first conduction type.
Optionally, the power semiconductor further includes：First electrode is arranged on the institute of second semiconductor regions
It states on surface, the first electrode is in the sunk area away from second semiconductor regions and first semiconductor region
The one side that domain is in contact is contacted with second semiconductor regions；Second electrode is arranged on the another of the first semiconductor region
On one surface.
Optionally, surface of the first electrode not with the sunk area contacts.
Optionally, the power semiconductor further includes：Doped polysilicon layer is arranged on first insulating layer；
Second insulating layer is arranged on the doped polysilicon layer；The 3rd opening is formed in the second insulating layer, the described 3rd opens
It is mouthful corresponding with second semiconductor regions, and be located at and the discontiguous doped polycrystalline silicon face of the sunk area.
Optionally, the power semiconductor further includes：At least one the third semiconductor region is arranged on described first
On semiconductor regions, and the surface of the third semiconductor region is flushed with the surface of the first semiconductor region,
The third semiconductor region has the second conduction type.
Optionally, the power semiconductor further includes：Electrode is contacted, is arranged in the second insulating layer, it is described
Contact electrode is by penetrating through the opening of first insulating layer, the doped polysilicon layer and the second insulating layer and described the
Three semiconductor regions contact.
Optionally, the power semiconductor further includes：At least one the fourth semiconductor region is arranged on described first
On semiconductor regions, and the surface of described the fourth semiconductor region is flushed with the surface of the first semiconductor region,
Described the fourth semiconductor region has the first conduction type, and the doped polysilicon layer passes through on first insulating layer
Opening is contacted with described the fourth semiconductor region.
Optionally, the power semiconductor is diode.
Second aspect of the present invention provides a kind of manufacturing method of power semiconductor, including：There is provided has first to lead
The first semiconductor region of electric type；At least one second semiconductor regions are formed in the first semiconductor region, it is described
The surface of second semiconductor regions is flushed with the surface of the first semiconductor region, and second semiconductor regions have
Second conduction type opposite with first conduction type；In the first semiconductor region and second semiconductor regions
The surface on form the first insulating layer；Correspond to the position shape of second semiconductor regions on first insulating layer
Into at least one first opening；Have the by described first injection that is open into the surface of second semiconductor regions
The semi-conducting material of one conduction type forms at least one sunk area.
Optionally, the method further includes：First electrode is set on the surface of second semiconductor regions, institute
State what first electrode was in contact in separate second semiconductor regions of the sunk area with the first semiconductor region
One side is contacted with second semiconductor regions；Second electrode is set on another surface of the first semiconductor region.
Optionally, include in described the step of first electrode is being set on the surface of second semiconductor regions：
The second opening is formed on first insulating layer, second opening does not expose the surface of the sunk area；Described
Two openings set the first electrode.
Optionally, further included described before the step of second opening sets the first electrode：Described
Doped polysilicon layer is formed on first insulating layer；Second insulating layer is formed on the doped polysilicon layer；Described second absolutely
The 3rd opening is formed in edge layer, the 3rd opening is corresponding with second semiconductor regions, and is located at and the depressed area
The discontiguous doped polycrystalline silicon face in domain.
Optionally, the method further includes：At least one 3rd semiconductor region is formed in the first semiconductor region
Domain, the surface of the third semiconductor region are flushed with the surface of the first semiconductor region, the 3rd semiconductor
Region has the second conduction type.
Optionally, the method further includes：Formed above the third semiconductor region penetrate through the second insulating layer,
The opening of the doped polysilicon layer, first insulating layer；Contact electrode, the contact are formed in the second insulating layer
Electrode is by penetrating through the opening and the described 3rd half of first insulating layer, the doped polysilicon layer and the second insulating layer
Conductive region contacts.
Optionally, the method further includes：At least one 4th semiconductor region is formed in the first semiconductor region
Domain, the surface of described the fourth semiconductor region are flushed with the surface of the first semiconductor region, the 4th semiconductor
Region has the first conduction type；Opening is formed on first insulating layer above described the fourth semiconductor region, it is described
Doped polysilicon layer is contacted by the opening on first insulating layer with described the fourth semiconductor region.
The power semiconductor and its manufacturing method that the embodiment of the present invention is provided, in the first conduction type
The second semiconductor regions with the second conduction type on semiconductor region are set, are led in the first semiconductor region and the second half
First insulating layer is set on the surface of body region, and the position that the second semiconductor regions are corresponded on the first insulating layer sets at least one
A opening, in order to correspond to the position injection of opening half with the first conduction type in the surface of the second semiconductor regions
Conductor material forms at least one sunk area, so that in the first semiconductor region and the PN junction of the second semiconductor regions
During positively biased, the how sub- hole on surface is collected in the second semiconductor regions can bypass the first semiconductor of edge inflow of sunk area
Region forms excess holes (i.e. excess carriers), and the path in hole, increase are extended in the lateral resistance area of similary length
The pressure drop in lateral resistance area so that PN junction bias reduces, and moment pours in the first half by the lateral edges of the second semiconductor regions and leads
The number of cavities of body region is reduced, so as to reduce the surface temperature；In the first semiconductor region and the PN of the second semiconductor regions
When knot bears higher reverse biased, the excess holes in the first semiconductor region is collected in surface and flows into the second semiconductor region
Domain, and when further being extracted by electrode, the edge of sunk area can be also bypassed in the second semiconductor regions, thus equally long
The path in hole, the self-biasing effect in enhancing lateral resistance area so that moment is reversed pumping are extended in the lateral resistance area of degree
The number of cavities taken is reduced, and the electric field strength at this and corresponding hole concentration effect is reduced, so as to reduce Reverse recovery (i.e.
During PN junction reverse biased) during the surface temperature.It can be seen that above-mentioned power semiconductor can reduce surface temperature
Shorten the length in lateral resistance area while spending, so as to reduce the size of power semiconductor.
Description of the drawings
The features and advantages of the present invention can be more clearly understood by reference to attached drawing, attached drawing is schematically without that should manage
It solves to carry out any restrictions to the present invention, in the accompanying drawings：
Figure 1A shows Longitudinal cross section schematic during existing diode forward bias；
Figure 1B shows Longitudinal cross section schematic during existing diode reverse biased；
Fig. 2 shows a kind of Longitudinal cross section schematic of power semiconductor according to embodiments of the present invention；
Fig. 3 A show the Longitudinal cross section schematic of another power semiconductor according to embodiments of the present invention；
Fig. 3 B show the Longitudinal cross section schematic of another power semiconductor according to embodiments of the present invention；
Fig. 4 A show the Longitudinal cross section schematic of another power semiconductor according to embodiments of the present invention；
Fig. 4 B show the Longitudinal cross section schematic of another power semiconductor according to embodiments of the present invention；
Fig. 5 shows a kind of flow chart of the manufacturing method of power semiconductor according to embodiments of the present invention；
Fig. 6 A-6E show that each step is corresponding in the manufacturing method of power semiconductor according to embodiments of the present invention
Schematic diagram；
Fig. 7 shows the flow chart of the manufacturing method of another power semiconductor according to the present invention；
Fig. 8 A-8E show that each step is corresponding in the manufacturing method of power semiconductor according to embodiments of the present invention
Schematic diagram.
Specific embodiment
In order to make the purpose of the present invention, advantage, preparation method clearer, below in conjunction with implementation of the attached drawing to the present invention
Example is described in detail, and the example of the embodiment is shown in the drawings, and part-structure has directly given excellent wherein in attached drawing
The structural material of choosing, it is clear that described embodiment is part of the embodiment of the present invention, instead of all the embodiments.It needs
Illustrate, the embodiment being described with reference to the drawings is exemplary, and the structural material shown in embodiment is also exemplary, only
It for explaining the present invention, and is not construed as limiting the claims, the attached drawing of each embodiment of the present invention is merely to signal
Purpose, therefore be not necessarily to scale.Based on the embodiments of the present invention, those skilled in the art are not making wound
All other embodiments obtained under the premise of the property made work, belong to the scope of protection of the invention.
It should be noted that the first conduction type in the application can be N-type, then the second conduction type is p-type；Or
First conduction type is p-type, then the second conduction type is N-type.
Embodiment one
Fig. 2 shows a kind of Longitudinal cross section schematic of power semiconductor according to embodiments of the present invention, such as Fig. 2 institutes
Show, which includes the first semiconductor region 1, at least one second semiconductor regions 2,41 and of the first insulating layer
At least one sunk area 6, wherein the first semiconductor region 1 have the first conduction type, and the second semiconductor regions 2 have and the
The second opposite conduction type of one conduction type, the surface and the surface of the first semiconductor region 1 of the second semiconductor regions 2 are neat
Flat, the first insulating layer 41 is arranged on the surface of 1 and second semiconductor regions 2 of the first semiconductor region, the first insulating layer 41
The upper position corresponding to the second semiconductor regions 2 is provided at least one opening, is corresponded in the surface of the second semiconductor regions 2
At least one sunk area 6 is formed in the position of opening, sunk area 6 is the semi-conducting material with the first conduction type.
Although illustrating only a sunk area 6 in Fig. 2, it should be appreciated to those skilled in the art that more sunk areas 6 are also
Feasible.Power semiconductor of the power semiconductor of the embodiment of the present invention especially suitable for diode etc..
Hereinafter, using the first semiconductor type as N-type, the second semiconductor type is the detailed description embodiment of the present invention exemplified by p-type.
As shown in Fig. 2, when being applied in voltage between 1 and second semiconductor regions 2 of the first semiconductor region, such as be applied in
During forward bias, the how sub- hole in the second semiconductor regions 2 flows to the first semiconductor by the edge of the second semiconductor regions 2
Region 1 forms excess holes (i.e. excess carriers) in the first semiconductor region 1.Due to the hole collection of the second semiconductor regions 2
In when the surface flows to the first semiconductor region 1, it is necessary to around sunk area 6 edge, thus in the transverse direction of similary length
Extend the path in hole in resistance area, the pressure drop in increase lateral resistance area so that PN junction bias reduces, and moment passes through the second half
The lateral edges (lateral edges are position shown in thick line in Fig. 2, and dotted line show hole path) of conductive region 2 pour in the first half and lead
The number of cavities of body region 1 is reduced.
On the other hand, the lateral resistance area shown in Figure 1A is equivalent to R, and lateral resistance area shown in Fig. 2 is equivalent to R1+R2
+ R3, wherein R1 are equivalent to the resistance of the left side edge of sunk area 6, R2 be equivalent to sunk area 6 bottom margin resistance,
R3 is equivalent to the resistance of the right side edge of sunk area 6.Since the depth of sunk area 6 is deeper, when the second semiconductor regions 2
When surface dopant concentration is higher, resistance R2 is more than resistance R (doping concentration is higher, and resistance is smaller), and the presence of resistance R1, R3 is into one
The resistance in step increase lateral resistance area so that PN junction bias further reduces, the lateral edges that moment passes through the second semiconductor regions 2
The number of cavities for pouring in the first semiconductor region 1 is further reduced.
When being applied in higher reverse biased between 1 and second semiconductor regions 2 of the first semiconductor region, the first half lead
The excess holes of body region flows into the second semiconductor regions 2.When the hole of the near side edges of the second semiconductor regions 2 is collected in
When the surface flows into the second semiconductor regions 2, it is also desirable to around the edge of sunk area 6, thus in the laterally electricity of similary length
Extend the path in hole in resistance area, the self-biasing effect in enhancing lateral resistance area reduces electric field strength at this and corresponding
Hole concentration effect so that by lateral edges moment be reversed extraction number of cavities reduce, so as to reduce Reverse recovery (i.e.
During PN junction reverse biased) during the surface temperature.
It should be added that sunk area 6 can be fully located in lateral resistance area (as shown in Figure 2).
Above-mentioned power semiconductor sets in the first semiconductor region with the first conduction type and is led with second
Second semiconductor regions of electric type set the first insulation on the surface of the first semiconductor region and the second semiconductor regions
Layer, the position that the second semiconductor regions are corresponded on the first insulating layer sets at least one opening, in order in the second semiconductor
Corresponding to semi-conducting material of the position injection with the first conduction type of opening in the surface in region, at least one recess is formed
Region so that in the first semiconductor region and the PN junction positively biased of the second semiconductor regions, collects in the second semiconductor regions
Edge inflow the first semiconductor region formation excess holes (the i.e. superfluous load of sunk area can be bypassed in the how sub- hole on surface by gathering
Stream), the path in hole, the pressure drop in increase lateral resistance area so that PN junction are extended in the lateral resistance area of similary length
Bias reduces, and the number of cavities that moment pours in the first semiconductor region by the lateral edges of the second semiconductor regions is reduced, so as to
Reduce the surface temperature；When the PN junction of the first semiconductor region and the second semiconductor regions bears higher reverse biased, the
Excess holes in semiconductor region is collected in surface and flows into the second semiconductor regions, and when further being extracted by electrode,
Also the edge of sunk area can be bypassed in second semiconductor regions, thus extends hole in the lateral resistance area of similary length
Path, the self-biasing effect in enhancing lateral resistance area reduces the electric field strength at this and corresponding hole concentration effect, makes
Moment be reversed the number of cavities of extraction and reduce, so as to reduce Reverse recovery when PN junction reverse biased (i.e.) surface in the process
Temperature.It can be seen that above-mentioned power semiconductor can shorten the length in lateral resistance area while surface temperature is reduced
Degree (simulation result shows that the width in lateral resistance area can be decreased to existing 50-75%, for example, 55%, 60%, 65%,
70%), so as to reducing the size of power semiconductor.For example, in 3.3kV fast recovery diodes, it is laterally electric in the prior art
Resistance sector width is up to 120 μm or more, but the lateral resistance area of semiconductor devices that the embodiment of the present invention is provided only needs 30 μm, by
This can reduce the additional area of semiconductor devices, increase active region area, improve the utilization rate of semiconductor devices.
Power semiconductor in the present embodiment can also include first electrode 3 and second electrode 5.As shown in Fig. 2, the
One electrode 3 is arranged on the surface of the second semiconductor regions 2, and first electrode 3 is in sunk area 6 away from the second semiconductor regions
2 one sides being in contact with the first semiconductor region 1, contact with the second semiconductor regions 2 namely sunk area 6 is located at the first electricity
Between the lateral edges (lateral edges are position shown in thick line in figure) of 3 and second semiconductor regions 2 of pole.First electrode 3 not with it is recessed
Fall into the surface contact in region 6.In fig. 2, second electrode 5 is arranged on another surface of the first semiconductor region 1, but this hair
It is bright to be not limited to this, in fact, second electrode 5 can also be arranged on the table with the first semiconductor region 1 of 3 homonymy of first electrode
On face；Alternatively, it as shown in Fig. 2, can be arranged on and above-mentioned " surface " (upper surface in figure) opposite surface (i.e. lower surface)；Again
Or side surface can be arranged on, the application does not limit herein.
Optionally, in Fig. 2, the width of sunk area 6 is 35-55 μm, and depth is 2-6 μm, doping concentration 1.2e18.It is recessed
The distance for falling into the right side edge in region 6 and the right side edge of the second semiconductor regions 2 is 10-25 μm, the left side of sunk area 6
The distance of edge and first electrode 3 is 30-40 μm.The width of the first semiconductor region 1 is 100-120 μm, and depth is 10-15 μm,
Surface dopant concentration is 1e17-5e17.The inside doping concentration of substrate 1 is 1.5e13-5e13, and thickness is 200-250 μm.
As a kind of optional embodiment of the present embodiment, which further includes 8 He of doped polysilicon layer
Second insulating layer 42.
Doped polysilicon layer 8 is arranged on the first insulating layer 41.Second insulating layer 42 is arranged on doped polysilicon layer 8.
As shown in Figure 3A, in the lateral resistance area above the second semiconductor regions 2, it is disposed with the first insulating layer
41st, doped polysilicon layer 8 and second insulating layer 42.First electrode 3 extends to the second insulating layer above covering lateral resistance area
42.The DOPOS doped polycrystalline silicon 8 in lateral resistance area is independently arranged, i.e., is not contacted with the doped polysilicon layer of other parts.
Above-mentioned DOPOS doped polycrystalline silicon can improve the voltage that semiconductor devices is resistant to as field plate.
Embodiment two
Difference lies in the power semiconductor in the present embodiment further includes at least one 3rd half and leads with embodiment one
Body region 7.As shown in Figure 3A, which is arranged in the first semiconductor region 1, and the 3rd semiconductor region
The surface in domain 7 is flushed with the surface of the first semiconductor region 1, and the third semiconductor region 7 has the second conduction type, i.e. p-type.The
Three semiconductor regions 7 have been sequentially arranged above the first insulating layer 41, doped polysilicon layer 8 and second insulating layer 42.
Above-mentioned the third semiconductor region 7 can be used as field limiting ring, improve the pressure-resistant of power semiconductor.3rd semiconductor region
Doped polysilicon layer above domain is independently arranged and (is not contacted with the doped polysilicon layer of other parts), makes as floating field plate
With the pressure-resistant of power semiconductor can be further improved.Simulation result shows obtaining transverse direction same as the prior art
In the case of resistance value (i.e. the resistance value in lateral resistance area), the lateral resistance of the semiconductor devices with floating field plate in the present embodiment
Sector width can be reduced to existing 50-75%, such as 55%, 60%, 65%, 70%, pressure-resistant to reach 3.3kV or so.
Further, which can also include contact electrode 13.As shown in Figure 3B, the contact electrode 13
It is arranged in second insulating layer 42, contact electrode 13 is by penetrating through the first insulating layer 41, doped polysilicon layer 8 and second insulating layer
42 opening is contacted with the third semiconductor region 7.Electrode 13 is contacted so that the third semiconductor region 7 and the doped polycrystalline above it
Silicon layer 8 is electrically connected, and forms contact field plate, it is resistance in reversely restoring process can to further improve power semiconductor
Pressure.Such as simulation result shows that the pressure-resistant of semiconductor devices with contact field plate can reach 4.5kV or so.
Embodiment three
Difference lies in the power semiconductor in the present embodiment further includes at least one with embodiment one and embodiment two
A the fourth semiconductor region 9.As shown in Figure 4 A and 4 B shown in FIG., which is arranged in the first semiconductor region 1,
And the surface of the fourth semiconductor region 9 is flushed with the surface of the first semiconductor region 1, and the fourth semiconductor region 9 has first
Conduction type, i.e. N-type.The fourth semiconductor region 9 has been sequentially arranged above the first insulating layer 41, doped polysilicon layer 8 and
Two insulating layers 42, and doped polysilicon layer 8 is contacted by the opening on the first insulating layer 41 with the fourth semiconductor region 9.
Above-mentioned the fourth semiconductor region makees that cut-off ring can be used as, the independently arranged DOPOS doped polycrystalline silicon 8 contacted with cut-off ring
(not contacted with the doped polysilicon layer of other parts) can be used as field plate.
It should be added that in above-described embodiment one, two, three, most of the first semiconductor region 1 is lightly doped district
11, the part contacted with second electrode 5 is heavily doped region 12, so as to form good Ohmic contact with second electrode 5.The second half
Conductive region 2 can be heavy doping；Alternatively, only the place contacted with first electrode 3 be heavy doping, so as to first electrode 3
Form good Ohmic contact.The third semiconductor region 7 can be heavy doping；Alternatively, set contact electrode 13 when, only with
It is heavy doping to contact the place that electrode 13 contacts, so as to form good Ohmic contact with contacting electrode 13.
Example IV
Fig. 5 shows a kind of flow chart of the manufacturing method of power semiconductor according to embodiments of the present invention, can be with
For manufacturing embodiment one or embodiment two or the power semiconductor described in its any one optional embodiment.Such as
Shown in Fig. 5, this method comprises the following steps：
S101：The first semiconductor region with the first conduction type is provided.
S102：At least one second semiconductor regions, the table of the second semiconductor regions are formed in the first semiconductor region
Face is flushed with the surface of the first semiconductor region, and the second semiconductor regions have opposite with the first conduction type second to lead
Electric type.
As shown in Figure 6A, 1 be N-type the first semiconductor region, 2 be the second semiconductor regions 2.Form the second semiconductor region
The method in domain 2 can first form the groove of the second semiconductor regions in the first semiconductor region 1, then fill p-type in a groove
Then semiconductor flushes filled P-type semiconductor and the surface of the first semiconductor region 1 by levelling process；Alternatively,
Can by techniques such as ion implanting or thermal diffusions to the flat surface implanting impurity ion of the first semiconductor region 1, so as to
Form the second semiconductor regions 2.
S103：The first insulating layer is formed on the surface of the first semiconductor region and the second semiconductor regions.
As shown in Figure 6B, 4 be the first insulating layer.
S104：Position corresponding to the second semiconductor regions on the first insulating layer forms at least one first opening.
S105：It is open by first into the surface of the second semiconductor regions and injects the semiconductor with the first conduction type
Material forms at least one sunk area.
As shown in Figure 6 C, 6 be sunk area.
S106：First electrode is set on the surface of the second semiconductor regions, and first electrode is in sunk area away from the
The one side that two semiconductor regions are in contact with the first semiconductor region is contacted with the second semiconductor regions.
As illustrated in fig. 6e, the lateral edges of 3 and second semiconductor regions 2 of first electrode are located at the both sides of sunk area 6 respectively.
Step S106 can be that opening is first formed on the first insulating layer 4, and opening does not expose the surface of sunk area 6, such as
Shown in Fig. 6 D；First electrode 3 finally is set in opening, as illustrated in fig. 6e.
S107：Second electrode is set on another surface of the first semiconductor region.
Such as another surface that can be oppositely arranged on the surface with the first semiconductor 1 sets second electrode 5, it can also be
Side sets second electrode 5, and the application does not limit this.
The manufacturing method of above-mentioned power semiconductor is formed in the first semiconductor region with the first conduction type
The second semiconductor regions with the second conduction type are formed on the surface of the first semiconductor region and the second semiconductor regions
First insulating layer, the position corresponding to the second semiconductor regions on the first insulating layer form at least one opening, pass through first
Be open semi-conducting material of the injection with the first conduction type into the surface of the second semiconductor regions, forms at least one recess
Region, so as to shorten the length in lateral resistance area while surface temperature is reduced, so as to reduce power semiconductor
Size, specifically refer to embodiment one.
Embodiment five
Fig. 7 shows the flow chart of the manufacturing method of another power semiconductor according to the present invention, can be used for
Manufacture the power semiconductor described in embodiment one to embodiment three or its any one optional embodiment.Such as Fig. 7 institutes
Show, this method comprises the following steps：
S201：The first semiconductor region with the first conduction type is provided.
S202：At least one second semiconductor regions and at least one 3rd semiconductor are formed in the first semiconductor region
Region.The surface of second semiconductor regions is flushed with the surface of the first semiconductor region, and the second semiconductor regions have with
The second opposite conduction type of first conduction type.The surface of the third semiconductor region and the surface of the first semiconductor region are neat
Flat, the third semiconductor region has the second conduction type.Second semiconductor regions and the third semiconductor region can be formed synchronously,
It can also be respectively formed, be preferably synchronous formed.
As shown in Figure 8 A, the first semiconductor region can include lightly doped district 11 and heavily doped region 12.Can be light in N-type
By techniques such as ion implanting or thermal diffusions to for setting a face impurity ion of second electrode on the semiconductor of doping,
Form heavily doped region 12.The step of forming heavily doped region 12 only need to be before the step of " setting second electrode 5 ".
As shown in Figure 8 A, 2 be the second semiconductor regions, and 7 be the third semiconductor region, and the third semiconductor region is led for p-type
Electricity.The method for forming the second semiconductor regions 2 and the third semiconductor region 7 can be by works such as ion implanting or thermal diffusions
Skill is to the flat surface implanting impurity ion of the first semiconductor region 1.
S203：The first insulating layer is formed on the surface of the first semiconductor region and the second semiconductor regions, and second
The first opening is formed on the first insulating layer above semiconductor regions and above the first semiconductor region.
As shown in Figure 8 B, 41 be the first insulating layer.
It should be added that a kind of alternative as step S202, it can also be first on the first insulating layer
Form opening, the opening as ion implanting window, using ion implantation by window to the first semiconductor region inject from
Son forms the third semiconductor region, and the insulation of layer can be formed in open bottom again before doped polysilicon layer is formed
Layer, that is, form the first insulating layer as shown in Figure 8 B.If being initially formed the third semiconductor region, the first insulating layer 41 is re-formed, then
The surface of first insulating layer can also flush.
S204：Doped polysilicon layer is formed on the first insulating layer.
As shown in Figure 8 B, 8 be doped polysilicon layer.Due on 2 top of the second semiconductor regions and the fourth semiconductor region 9
First insulating layer 41 of side is formed with the first opening, thus doped polysilicon layer 8 by the first opening on the first insulating layer with
There are contact in second semiconductor regions, the fourth semiconductor region.Doped polysilicon layer has the first conduction type.
Since the doped polysilicon layer of 2 top of the second semiconductor regions disconnects, the top of the second semiconductor regions 2 has
Portion of doped polysilicon is not contacted with sunk area 6, and the DOPOS doped polycrystalline silicon not contacted with sunk area 6 can be used as field plate.
S205：Opening is formed on doped polysilicon layer so that the doped polysilicon layer above the second semiconductor regions breaks
It opens, the doped polysilicon layer above doped polysilicon layer, the fourth semiconductor region above the third semiconductor region disconnects two-by-two,
And the doped polysilicon layer above adjacent the third semiconductor region disconnects two-by-two.
S206：To semiconductor impurities of the DOPOS doped polycrystalline silicon layer surface injection with the first conduction type, and cause tool
The semiconductor impurities for having the first conduction type inject the second semiconductor regions and the first semiconductor region by the first opening, with shape
Into sunk area and the fourth semiconductor region.
S207：Second insulating layer is formed on doped polysilicon layer.
As shown in Figure 8 C, 42 be second insulating layer.
S208：The 3rd opening is formed over the second dielectric, and the 3rd opening is corresponding with the second semiconductor regions, and position
In with the discontiguous doped polycrystalline silicon face of sunk area.
S209：The second opening is formed in the first insulating layer, doped polysilicon layer, second insulating layer, second opening is not
Expose the surface of sunk area.
After the step as shown in Figure 8 C.
S210：First electrode is set on the surface of the second semiconductor regions.
As in fig. 8d, first electrode 3 is extended in second insulating layer.First electrode 3 is in sunk area 6 away from second
The one side that semiconductor regions 2 are in contact with the first semiconductor region 1 is contacted with the second semiconductor regions 2.Namely first electrode 3
It is located at the both sides of sunk area 6 respectively with the lateral edges of the second semiconductor regions 2.
In addition, the 3rd opening is formed in second insulating layer 42, therefore first electrode 3 passes through the 3rd opening and doped polycrystalline
Silicon contacts, so as to which the field plate for enhancing the portion of doped polysilicon while voltage is applied to first electrode 3 acts on.
S211：Second electrode is set on another surface of the first semiconductor region.
The step refers to the step S107 of example IV.
It can be formed such as by above-mentioned steps, then in the surface of second insulating layer 42 and first electrode 3 formation passivation layer
Power semiconductor shown in Fig. 4 A.
As a kind of optional embodiment of the present embodiment, after step S210, can also as follows be formed such as
Power semiconductor shown in Fig. 4 B.
S212：Perforation second insulating layer, doped polysilicon layer, first insulating layer are formed above the third semiconductor region
Opening.
S213：Contact electrode is formed over the second dielectric, and contact electrode is by penetrating through the first insulating layer, DOPOS doped polycrystalline silicon
The opening of layer and second insulating layer is contacted with the third semiconductor region.
As described in Fig. 8 E, 13 be contact electrode.43 be passivation layer.
Although being described in detail on example embodiment and its advantage, those skilled in the art can not depart from
Various change is carried out to these embodiments in the case of the spiritual and defined in the appended claims protection domain of the present invention, is replaced
And modification, such modifications and variations are each fallen within be defined by the appended claims within the scope of.For other examples, ability
The those of ordinary skill in domain should be readily appreciated that the order of processing step can become while keeping in the scope of the present invention
Change.
In addition, the application range of the present invention is not limited to technique, mechanism, the system of the specific embodiment described in specification
It makes, material composition, means, method and step.It, will be easy as those of ordinary skill in the art from the disclosure
Ground understands, for current technique that is existing or will developing later, mechanism, manufacture, material composition, means, method or
Step, the knot that the function or acquisition that the corresponding embodiment that wherein they are performed with the present invention describes is substantially the same are substantially the same
Fruit can apply them according to the present invention.Therefore, appended claims of the present invention are intended to these techniques, mechanism, system
It makes, material composition, means, method or step are included in its protection domain.
Claims (15)
1. a kind of power semiconductor, which is characterized in that including：
The first semiconductor region has the first conduction type；
At least one second semiconductor regions, are arranged in the first semiconductor region, and second semiconductor regions
Surface flushed with the surface of the first semiconductor region, second semiconductor regions have and first conduction type
The second opposite conduction type；
First insulating layer is arranged on the surface of the first semiconductor region and second semiconductor regions；It is described
Position on first insulating layer corresponding to second semiconductor regions is provided at least one opening；
Position in the surface of second semiconductor regions corresponding to the opening is formed at least one sunk area,
The sunk area is the semi-conducting material with first conduction type.
2. power semiconductor according to claim 1, which is characterized in that further include：
First electrode is arranged on the surface of second semiconductor regions, and the first electrode is in the sunk area
The one side being in contact with the first semiconductor region away from second semiconductor regions, with second semiconductor regions
Contact；
Second electrode is arranged on another surface of the first semiconductor region.
3. power semiconductor according to claim 2, which is characterized in that the first electrode not with the depressed area
The surface contact in domain.
4. power semiconductor according to claim 2, which is characterized in that further include：
Doped polysilicon layer is arranged on first insulating layer；
Second insulating layer is arranged on the doped polysilicon layer；
The 3rd opening is formed in the second insulating layer, the 3rd opening is corresponding with second semiconductor regions, and
Positioned at the discontiguous doped polycrystalline silicon face of the sunk area.
5. power semiconductor according to claim 4, which is characterized in that further include：
At least one the third semiconductor region is arranged in the first semiconductor region, and the third semiconductor region
Surface flushed with the surface of the first semiconductor region, the third semiconductor region have the second conduction type.
6. power semiconductor according to claim 4, which is characterized in that further include：
Electrode is contacted, is arranged in the second insulating layer, the contact electrode is by penetrating through first insulating layer, described mixing
The opening of miscellaneous polysilicon layer and the second insulating layer is contacted with the third semiconductor region.
7. power semiconductor according to claim 6, which is characterized in that further include：
At least one the fourth semiconductor region is arranged in the first semiconductor region, and described the fourth semiconductor region
Surface flushed with the surface of the first semiconductor region, described the fourth semiconductor region have the first conduction type,
And the doped polysilicon layer is contacted by the opening on first insulating layer with described the fourth semiconductor region.
8. power semiconductor according to any one of claims 1 to 7, which is characterized in that the power semiconductor device
Part is diode.
9. a kind of manufacturing method of power semiconductor, which is characterized in that including：
The first semiconductor region with the first conduction type is provided；
At least one second semiconductor regions, the surface of second semiconductor regions are formed in the first semiconductor region
It is flushed with the surface of the first semiconductor region, and second semiconductor regions have and the first conduction type phase
The second anti-conduction type；
The first insulating layer is formed on the surface of the first semiconductor region and second semiconductor regions；
Position corresponding to second semiconductor regions on first insulating layer forms at least one first opening；
Be open half injected into the surface of second semiconductor regions with the first conduction type by described first
Conductor material forms at least one sunk area.
10. the manufacturing method of power semiconductor according to claim 9, which is characterized in that further include：
First electrode is set on the surface of second semiconductor regions, and the first electrode is in the sunk area
Away from the one side that second semiconductor regions are in contact with the first semiconductor region, connect with second semiconductor regions
It touches；
Second electrode is set on another surface of the first semiconductor region.
11. the manufacturing method of power semiconductor according to claim 10, which is characterized in that described described
Being set on the surface of two semiconductor regions the step of first electrode includes：
The second opening is formed on first insulating layer, second opening does not expose the surface of the sunk area；
In second opening, the first electrode is set.
12. the manufacturing method of power semiconductor according to claim 10, which is characterized in that described described
Before two openings set the step of first electrode, further include：
Doped polysilicon layer is formed on first insulating layer；
Second insulating layer is formed on the doped polysilicon layer；
The 3rd opening is formed in the second insulating layer, the 3rd opening is corresponding with second semiconductor regions, and
Positioned at the discontiguous doped polycrystalline silicon face of the sunk area.
13. the manufacturing method of power semiconductor according to claim 12, which is characterized in that further include：
At least one the third semiconductor region, the surface of the third semiconductor region are formed in the first semiconductor region
It is flushed with the surface of the first semiconductor region, the third semiconductor region has the second conduction type.
14. the manufacturing method of power semiconductor according to claim 13, which is characterized in that further include：
It is formed above the third semiconductor region and penetrates through the second insulating layer, the doped polysilicon layer, described first
The opening of insulating layer；
Contact electrode is formed in the second insulating layer, the contact electrode is by penetrating through first insulating layer, described mixing
The opening of miscellaneous polysilicon layer and the second insulating layer is contacted with the third semiconductor region.
15. the manufacturing method of power semiconductor according to claim 12, which is characterized in that further include：
At least one the fourth semiconductor region, the surface of described the fourth semiconductor region are formed in the first semiconductor region
It is flushed with the surface of the first semiconductor region, described the fourth semiconductor region has the first conduction type；
Opening is formed on first insulating layer above described the fourth semiconductor region, the doped polysilicon layer passes through institute
The opening stated on the first insulating layer is contacted with described the fourth semiconductor region.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN118431301A (en) * | 2024-03-29 | 2024-08-02 | 海信家电集团股份有限公司 | Diode module and method for manufacturing diode module |
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| JP2000150859A (en) * | 1998-11-18 | 2000-05-30 | Meidensha Corp | Diode |
| US20130214394A1 (en) * | 2012-02-22 | 2013-08-22 | Toyota Jidosha Kabushiki Kaisha | Semiconductor device |
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