CN108107962A - Image control circuit - Google Patents
Image control circuit Download PDFInfo
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- CN108107962A CN108107962A CN201711434182.3A CN201711434182A CN108107962A CN 108107962 A CN108107962 A CN 108107962A CN 201711434182 A CN201711434182 A CN 201711434182A CN 108107962 A CN108107962 A CN 108107962A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
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- Automation & Control Theory (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
A kind of image control circuit, including a current generating circuit, a voltage generation circuit, an image generation circuit, a circuit for detecting and a logic circuit.Current generating circuit generates a reference current according to a selection signal.Voltage generation circuit generates a reference voltage according to selection signal.Image generation circuit couples a resistance, and according to the reference current, generates an image current.Circuit for detecting detects the voltage of resistance, and the voltage of resistance is made comparisons with reference voltage, to generate a detection signal.Logic circuit is according to detection signal, enable or forbidden energy selection signal.When the voltage of resistance is less than reference voltage, logic circuit forbidden energy selection signal.When selection signal is disabled, current generating circuit increases reference current and voltage generation circuit increases reference voltage.
Description
Technical field
The present invention is related to a kind of image control circuit, and screen is given to provide analog signal in particular to a kind of
Image control circuit.
Background technology
General digital video analog converter (Video DAC) needs whether running check screen or other display equipment connect
On.The known controlling party genealogy of law is to provide normal operating voltage and gives digital video analog converter.When digital video simulation turns
After parallel operation enters working condition, start to detect whether screen is connected to converter.If screen exists, digital video analog-converted
Device enters normal operating conditions.If screen is not present, digital video analog converter power cut-off, and in a set time
Afterwards, then restart.However, during digital video analog converter is started, digital video analog converter has very
Big power attenuation.
The content of the invention
The present invention provides a kind of image control circuit, including a current generating circuit, a voltage generation circuit, one first shadow
As generation circuit, a circuit for detecting and a logic circuit.Current generating circuit generates one with reference to electricity according to a selection signal
Stream.Voltage generation circuit generates a reference voltage according to selection signal.First image generation circuit couples a first resistor, and
According to the reference current, one first image current is generated.Circuit for detecting detects the voltage of first resistor, and by the electricity of first resistor
Pressure is made comparisons with reference voltage, to generate a detection signal.Logic circuit is according to detection signal, enable or forbidden energy selection letter
Number.When the voltage of first resistor is less than reference voltage, logic circuit forbidden energy selection signal.When selection signal is disabled, electricity
Flowing generation circuit increases reference current and voltage generation circuit increase reference voltage.
Description of the drawings
Fig. 1 is the schematic diagram of the image control circuit of the present invention.
Fig. 2 is another schematic diagram of the image control circuit of the present invention.
Fig. 3 is an embodiment of the image generation circuit of the present invention.
Fig. 4 is an embodiment of the image generation circuit of the present invention.
Fig. 5 is an embodiment of the image generation circuit of the present invention.
Fig. 6 is an embodiment of current generating circuit.
Fig. 7 is an embodiment of the voltage generation circuit of the present invention.
Fig. 8 is the timing control figure of the image control circuit of the present invention.
Fig. 9 is another timing control figure of the image control circuit of the present invention.
Specific embodiment
For objects, features and advantages of the present invention can be clearer and more comprehensible, it is cited below particularly go out embodiment, and coordinate attached drawing,
It elaborates.Description of the invention provides different embodiments to illustrate the technical characteristic of different embodiments of the present invention.Its
In, the configuration of each component in embodiment is for purposes of discussion, not limiting the present invention.In addition, schema mark in embodiment
Number part repeat, be the relevance being not meant as between different embodiments for the purpose of simplifying the description.
Fig. 1 is the schematic diagram of the image control circuit of the present invention.As shown in the figure, image control circuit 100 generates image electricity
Flow IR, IG, IB.Picture is presented according to image current IR, IG, IB in screen 150.In one embodiment, image current IR, IG, IB
For the three primary colours of corresponding adjustment screen 150, i.e., red, green and the corresponding value of blueness are shown with adjusting the image on screen 150
Colourity, saturation degree and the brightness shown.In other embodiments, image control circuit 100 is to be incorporated into a Video Graphics Array
(Video Graphics Array；VGA) in system, and as a digital video analog converter (Video DAC).In this example
In, image control circuit 100 provides analog signal and gives screen 150.
In the present embodiment, image control circuit 100 include a current generating circuit 105, a voltage generation circuit 110,
Image generation circuit 115,120,125, circuit for detecting 130,135,140 and a logic circuit 145.Current generating circuit 105
According to a selection signal SENSEL, a reference current BIAS is generated.In one embodiment, current generating circuit 105 is according to selection
Signal SENSEL converts a reference voltage V BG1, to generate reference current BIAS.Not current limit generation circuit of the invention
105 circuit framework.As long as the circuit of electric current can be generated, current generating circuit 105 can be used as.
Voltage generation circuit 110 generates a reference voltage VREF according to selection signal SENSEL.In one embodiment, it is electric
Generation circuit 110 is pressed to convert a reference voltage V BG2 according to selection signal SENSEL, to generate reference voltage VREF.The present invention
The not circuit framework of stop voltage generation circuit 110.As long as the circuit of voltage can be generated, voltage generation circuit can be used as
110。
Image generation circuit 115 couples a first resistor (not shown), and according to reference current BIAS, generates image current
IR.In the present embodiment, image generation circuit 115 adjusts image current IR according to a control signal SCR.Image generation circuit
120 one second resistance (not shown)s of coupling, and according to reference current BIAS, generate an image current IG.In the present embodiment, shadow
As generation circuit 120 is according to control signal SCG adjustment image currents IG.Image generation circuit 125 couples a 3rd resistor (not
Display), and according to reference current BIAS, generate an image current IB.In the present embodiment, image generation circuit 125 is according to one
Control signal SCB adjustment image currents IB.
Circuit for detecting 130 detects the voltage of first resistor, and the voltage of first resistor is made comparisons with reference voltage VREF,
To generate a detection signal SENSE_R.In the present embodiment, when screen 150 couples image control circuit 100, stream can be made
Electric current through first resistor becomes smaller, so that the voltage of first resistor becomes smaller, therefore, by the voltage of detecting first resistor,
It can determine whether that screen 150 couples image control circuit 100.
Circuit for detecting 135 detects the voltage of second resistance, and the voltage of second resistance is made comparisons with reference voltage VREF,
To generate a detection signal SENSE_G.Circuit for detecting 140 detect 3rd resistor voltage, and by the voltage of 3rd resistor with
Reference voltage VREF makes comparisons, to generate a detection signal SENSE_B.Detection signal SENSE_R, SENSE_G and
SENSE_B also each has 150 coupling of screen in addition to for determining whether the coupling image control circuit 100 of screen 150 for judgement
When connecing image control circuit 100, the circuit of each detection signal is corresponded on screen 150 and connects the image control circuit 100
It whether there is failure with circuit/pin/interface of screen 150.
Logic circuit 145 is according to detection signal SENSE_R, SENSE_G and SENSE_B, enable or forbidden energy selection signal
SENSEL.For example, when the voltage of first resistor is less than reference voltage VREF, 145 forbidden energy selection signal of logic circuit
SENSEL.When selection signal SENSEL is disabled, current generating circuit 105 increases reference current BIAS and voltage generates electricity
Road 110 increases reference voltage VREF.
In one embodiment, in a baseline, 145 enable selection signal SENSEL of logic circuit.At this point, electric current generates
The reference current BIAS that circuit 105 is exported has the reference voltage that one first level and voltage generation circuit 110 are exported
VREF has one the 3rd level.However, when screen 150 couples image control circuit 100, the voltage of first resistor is less than reference
Voltage VREF.Therefore, 145 forbidden energy selection signal SENSEL of logic circuit.When selection signal SENSEL is disabled, electric current generates
The reference current BIAS that circuit 105 is exported has the reference voltage that a second electrical level and voltage generation circuit 110 are exported
VREF has one the 4th level.An embodiment according to the present invention, the first level can be second electrical level half or other be less than
The value of second electrical level；3rd level can be the half or other values commented on less than the 4th of the 4th level.Since electric current generates
Circuit 105 and voltage generation circuit 110 suitably adjust reference current BIAS and reference voltage according to selection signal SENSEL
The level of VREF, therefore the power attenuation of current generating circuit 105 and voltage generation circuit 110 can be reduced, and because electric current produces
The reference current that raw circuit 105 is exported to image generation circuit 115, image generation circuit 120 and image generation circuit 125
BIAS is adjusted, and causes the power attenuation of image generation circuit 115, image generation circuit 120 and image generation circuit 125
It is corresponding to reduce.
In other embodiments, since one or two in detection signal SENSE_R, SENSE_G and SENSE_B may
Because screen 150 or circuit/pin/interface of connection image control circuit 100 and screen 150 cannot be effectively defeated there are failure
Go out, therefore logic circuit 145 can generate selection signal SENSEL according to effective single detection signal.In addition, in the present embodiment,
Logic circuit 145 also generates control signal SCR, SCG and SCB, to control image generation circuit 115,120 and 125.Image produces
Raw circuit 115,120 and 125 is respectively according to control signal SCR, SCG and SCB, adjustment image current IR, IG and IB.
In one embodiment, in a baseline, logic circuit 145 does not export selection signal SENSEL, and directly produces
A raw control signal PDDAC, to starting current generation circuit 105 and voltage generation circuit 110 simultaneously.In this instance, electricity is treated
After flowing the generation reference current BIAS of generation circuit 105 and the generation reference voltage of voltage generation circuit 110 VREF, logic circuit
145 one control signal PDSENSE of generation give circuit for detecting 130,135 and 140.Circuit for detecting 130,135 and 140 is believed according to control
Number PDSENSE detects the voltage of first, second and third resistance.
Fig. 2 is another possible schematic diagram of the image control circuit of the present invention.Fig. 2 similar diagrams 1, the difference is that, shadow
Image forming control circuit 200 further includes a voltage generation circuit 205 and switch module 210.Voltage generation circuit 205 is believed according to control
Number PDDAC generates reference voltage V BG1 and VBG2.Reference voltage V BG1 can be same or different from reference voltage V BG2.Work as voltage
Generation circuit 205 only exports a reference voltage, then reference voltage V BG1 is identical to reference voltage V BG2；Work as voltage generation circuit
205 export multiple reference voltages, then reference voltage V BG1 may also be distinct from that reference voltage V BG2
Switch module 210 includes switch 215,220 and 225.Switch 215 is coupled to current generating circuit 105 and is produced with image
Between raw circuit 115, and image generation circuit 115 is given according to control signal PDR, transmission reference current BIAS.220 coupling of switch
Shadow is given between current generating circuit 105 and image generation circuit 120, and according to control signal PDG, transmission reference current BIAS
As generation circuit 120.Switch 225 is coupled between current generating circuit 105 and image generation circuit 125, and is believed according to control
Number PDB, transmission reference current BIAS give image generation circuit 125.
In the present embodiment, the first starting current generation circuit 105 of logic circuit 145, voltage generation circuit 110 and voltage production
Raw circuit 205, then turn on switch 215,220 and 225.Not current limit generation circuit 105, voltage generation circuit of the invention
110 and the boot sequence of voltage generation circuit 205, the turn-on sequence of switch 215,220 and 225 is not limited yet.In an embodiment
In, logic circuit 145 simultaneously turns on switch 215,220 and 225.In another embodiment, logic circuit 145 turns on switch one by one
215th, 220 and 225.Whether logic circuit 145 judges screen 150 according to detection signal SENSE_R, SENSE_G and SENSE_B
Couple image control circuit 200.When screen 150 does not couple image control circuit 200, as detection signal SENSE_R, SENSE_G
And none enable in SENSE_B, logic circuit 145 disconnect one by one switch 225,220 and 215, with reduce to power supply and other
The influence of circuit.In other embodiments, logic circuit 145 simultaneously switches off switch 215,220 and 225.When screen 150 is coupled to
Image control circuit 200, at least one of detection signal SENSE_R, SENSE_G and SENSE_B enable, then it represents that detection signal
Circuit in SENSE_R, SENSE_G and SENSE_B on the corresponding screen 150 of non-enable person is correspondingly connected with image control
The circuit of circuit 200 and screen 150/there may be failures for pin/interface.
Fig. 3 is an embodiment of the image generation circuit 115 of the present invention.As shown in the figure, image generation circuit 115 includes list
First circuit U A1~UAN and a first resistor 305.Due to the circuit framework all same of element circuit UA1~UAN, thus it is following only with
Exemplified by element circuit UA1.As shown in the figure, element circuit UA1 includes a transistor QA1, switch SWA1 and SWA2.Transistor QA1
Grid receive reference current BIAS, source electrode receives an operation voltage VPP.In the present embodiment, transistor QA1 is as an electricity
Stream source generates an electric current IA1 according to reference current BIAS.
Switch SWA1 is coupled between the drain electrode of transistor QA1 and a ground nodes GND.Switch SWA2 is coupled to transistor
Between the drain electrode of QA1 and first resistor 305.When switch SWA1 is switched on, switch SWA2 is disconnected.Therefore, image current IA1 flows
Enter ground nodes GND.When switch SWA2 is switched on, switch SWA1 is disconnected.
Therefore, image current IR is the sum of electric current IA1~IAN of each unit circuit U A1~UAN outputs, and image current
The size of IR can be by control switch SWA1~SWAP adjustment.Specifically, to be couple to the switch of first resistor 305 (such as
SWA2, SWA4, SWAN) exemplified by, when switch SWA2 and SWA4 is switched on, image current IR is total equal to electric current IA1's and IA2
With.When switch SWA2, SWA4 and SWAP are switched on, image current IR is equal to the summation of electric current IA1, IA2 and IAN.It is real one
It applies in example, switch SWA1~SWAP is controlled by logic circuit 145.Logic circuit 145 sends control signal SCR, to control
At least one of system switch SWA1~SWAP.In addition, the present invention does not limit the quantity of element circuit.In other embodiments,
Image generation circuit 115 only has single unit circuit.
In one embodiment, when screen 150 does not couple image control circuit 200, voltage of 305 upper end of first resistor etc.
In a preset value.When screen 150 couples image control circuit 200, due to 310 the first electricity of parallel connection of equivalent resistance of screen 150
Resistance 305, therefore the voltage of first resistor 305 is less than or equal to the preset value.Therefore, by the voltage of detecting first resistor 305 upper end,
It can be seen that screen 150 whether there is.In this instance, first resistor 305 is integrated in image generation circuit 115, but not to
The limitation present invention.In other embodiments, first resistor 305 is arranged at outside image generation circuit 115.In this instance, first
Resistance 305 can also be integrated among circuit for detecting 130.
Fig. 4 is an embodiment of the image generation circuit 120 of the present invention.As shown in the figure, image generation circuit 120 includes list
First circuit U B1~UBN and a second resistance 420.Due to the circuit framework all same of element circuit UB1~UBN, therefore below only
Illustrate unit circuit U B1.As shown in the figure, element circuit UB1 includes a transistor QB1 and switch SWB1 and SWB2.Transistor
The grid of QB1 receives reference current BIAS, and source electrode receives operation voltage VPP.In the present embodiment, transistor QB1 is as one
Current source generates electric current IB1 according to reference current BIAS.
Switch SWB1 is coupled between the drain electrode of transistor QB1 and ground nodes GND.Switch SWB2 is coupled to transistor
Between the drain electrode of QB1 and second resistance 420.In the present embodiment, second resistance 420 is integrated among image generation circuit 120,
But it is not to limit the present invention.In other embodiments, second resistance 420 is arranged at outside image generation circuit 120.When opening
When pass SWB1 is switched on, switch SWB2 is disconnected.Therefore, electric current IB1 flows into ground nodes GND.When switch SWB2 is switched on, open
SWB1 is closed to disconnect.
Therefore, image current IG is the sum of electric current IB1~IBN of each unit circuit U B1~UBN outputs, and image current
The size of IG can be by control switch SWB1~SWBP adjustment.Specifically, to be couple to the switch of second resistance 420 (such as
SWB2, SWB4, SWBN) exemplified by, when only switch SWB2 is switched on, image current IG is equal to electric current IB1.When switch SWB2 and
When SWB4 is switched on, image current IG is equal to the summation of electric current IB1 and IB2.When switch SWB2, SWB4 and SWBN are switched on,
Image current IG is equal to the summation of electric current IB1, IB2 and IBN.And in one embodiment, logic circuit 145 is believed through control
The switch that number SCG is turned on or off in image generation circuit 120, to adjust image current IG.
When screen 150 does not couple image control circuit 200, the voltage of second resistance 420 is equal to a preset value.Work as screen
During 150 coupling image control circuit 200, the second resistance 420 in parallel of resistance 310, therefore the voltage of second resistance 420 declines, and is less than
The preset value.
Fig. 5 is an embodiment of the image generation circuit 125 of the present invention.As shown in the figure, image generation circuit 125 includes list
First circuit U C1~UCN and a 3rd resistor 520.Due to the circuit framework all same of element circuit UC1~UCN, therefore below only
Illustrate unit circuit U C1.As shown in the figure, element circuit UC1 includes a transistor QC1 and switch SWC1 and SWC2.Transistor
The grid of QC1 receives reference current BIAS, and source electrode receives operation voltage VPP.In the present embodiment, transistor QC1 is as one
Current source generates electric current IC1 according to reference current BIAS.
Switch SWC1 is coupled between the drain electrode of transistor QC1 and ground nodes GND.Switch SWC2 is coupled to transistor
Between the drain electrode of QC1 and 3rd resistor 520.In the present embodiment, 3rd resistor 520 is integrated among image generation circuit 125,
But it is not to limit the present invention.In other embodiments, 3rd resistor 520 is arranged at outside image generation circuit 125.When opening
When pass SWC1 is switched on, switch SWC2 is disconnected.Therefore, electric current IC1 flows into ground nodes GND.When switch SWC2 is switched on, open
SWC1 is closed to disconnect.
Therefore, image current IG is the sum of electric current IC1~ICN of each unit circuit U C1~UCN outputs, and image current
The size of IB can be by control switch SWC1~SWCP adjustment.Specifically, to be couple to the switch of 3rd resistor 520 (such as
SWC2, SWC4, SWCN) exemplified by, when only switch SWC2 is switched on, image current IB is equal to electric current IC1.When switch SWC2 and
When SWC4 is switched on, image current IB is equal to the summation of electric current IC1 and IC2.In one embodiment, logic circuit 145 is through control
The switch that signal SCB processed is turned on or off in image generation circuit 125, to adjust image current IB.
When screen 150 does not couple image control circuit 200, the voltage of 3rd resistor 520 is equal to a preset value.Work as screen
During 150 coupling image control circuit 200, the 3rd resistor 520 in parallel of resistance 310, therefore the voltage of 3rd resistor 520 declines, and is less than
The preset value.
Fig. 6 is an embodiment of current generating circuit 105.In the present embodiment, current generating circuit 105 includes a computing
Amplifier 605, the switch 620 of transistor 610,615, one and a resistance 625.The inverting input of operational amplifier 605 receives
Reference voltage V BG1.The output terminal of the grid coupling operational amplifier 605 of transistor 610, source electrode receive an operation voltage
VPP, the in-phase input end of drain electrode coupling operational amplifier 605.The source electrode of transistor 615 receives operation voltage VPP, drain electrode
Couple the in-phase input end of operational amplifier 605.Switch 620 is coupled between the grid of transistor 610 and transistor 615.Electricity
Resistance 625 is coupled between the drain electrode of transistor 610 and ground nodes GND.When the output increase of operational amplifier 605, flow through
The electric current of transistor 610 becomes smaller, and therefore, the pressure difference of resistance 625 becomes smaller, smaller so as to be generated in the grid of transistor 610
Reference current BIAS.
In the present embodiment, when screen 150 does not couple image control circuit 200,145 enable selection signal of logic circuit
SENSEL, to turn on switch 620.So that reference current BIAS has one first level.When screen 150 couples image control
During circuit 200,145 forbidden energy selection signal SENSEL of logic circuit, to disconnect switch 620.So that reference current BIAS has
There is a second electrical level.In this instance, if transistor 610 is configured to identical with transistor 615, the first level is second electrical level
Half, if transistor 610 is configured to difference with transistor 615, the first level is less than second electrical level, the first level and the second electricity
It is flat that other proportionate relationships are presented.
The Fig. 6 is only used for the effect of diagram selection signal SENSEL, and does not limit the quantity of transistor, according to the present invention
Another embodiment, the transistor in parallel that current generating circuit includes, such as transistor 610 and transistor 615, or more
It is a, and the switch between transistor, such as 620 are acted on selection signal SENSEL, specifically control the grid of a certain transistor, example
Such as transistor 610, the size of the reference current BIAS picked out.
Fig. 7 is an embodiment of the voltage generation circuit 110 of the present invention.As shown in the figure, voltage generation circuit 110 includes one
Operational amplifier 705, a transistor 710, a resistance string 715 and a selector 740.The anti-phase input of operational amplifier 705
End receives reference voltage V BG2.The output terminal of the grid coupling operational amplifier 705 of transistor 710, source electrode receive operation electricity
Press VPP, the in-phase input end of drain electrode coupling operational amplifier 705.Resistance string 715 is coupled to the drain electrode of transistor 710 with connecing
Between ground node GND, to generate multiple partial pressure DV1~DV3.In the present embodiment, resistance string 715 include resistance 720,725,
730 and 735, but be not to limit the present invention.In other embodiments, resistance string 715 has more or fewer resistance.
Selector 740 selects one VREF as the reference voltage according to selection signal SENSEL from partial pressure DV1~DV3.
In one embodiment, when selection signal SENSEL is enabled, selector 740 will divide DV3 VREF as the reference voltage.Herein
In example, when selection signal SENSEL is disabled, selector 740 will divide DV2 VREF as the reference voltage, and partial pressure DV2 must
So it is less than former reference voltage VREF, so as to reduce power consumption, and the ratio for reducing power consumption is specifically dependent upon 720~resistance of resistance 735
Configuration.For example, in one embodiment, divide DV2 level be configurable to reference voltage VREF level half, partial pressure
The level of DV3 can also be configured to the half of the level of partial pressure DV2, then in the case where electric current is constant, can reduce half work(
Consumption.
Fig. 8 is the timing control figure of the image control circuit of the present invention.For convenience of description, controlled below with the image of Fig. 2
Exemplified by circuit 200.In a baseline 805,145 enable selection signal SENSEL of logic circuit.In the present embodiment, selection is worked as
When signal SENSEL is enabled, selection signal SENSEL is high level.Then, logic circuit 145 set control signal PDDAC as
Low level, to start voltage generation circuit 205,110 and current generating circuit 105.In this instance, current generating circuit
105 generate reference current BIAS according to reference voltage V BG1, and voltage generation circuit 110 generates ginseng according to reference voltage V BG2
Examine voltage VREF.In the present embodiment, since selection signal SENSEL is enabled, therefore the output one of current generating circuit 105 is smaller
Reference current, and voltage generation circuit 110 export a smaller reference voltage.Then, logic circuit 145 makes control one by one
Signal PDR, PDG and PDB are low level, to turn on switch 215,220 and 225 one by one.Therefore, image generation circuit 115,
120 and 125 act one by one.In this instance, image generation circuit 115,120 and 125 generates shadow according to reference current BIAS respectively
Image current IR, IG, IB.When image current IR, IG and IB flow separately through first, second and third resistance, if 150 non-coupling of screen
Image control circuit 200 is connect, then the voltage of first, second and third resistance is respectively equal to first, second and third preset value.So
And if screen 150 couples image control circuit 200, the voltage of first, second and third resistance is respectively smaller than first, second
And the 3rd preset value.
Therefore, 810 during one detects, logic circuit 145 sets control signal PDSENSE as low level, to start
Circuit for detecting 130,135 and 140.Circuit for detecting 130,135 and 140 judges that the voltage of first, second and third resistance is respectively
It is no to be less than reference voltage VREF, and generate detection signal SENSE_R, SENSE_G and SENSE_B.Due to detection signal SENSE_
R, SENSE_G and SENSE_B are identical, therefore detection signal SENSE_R is only shown in Fig. 8.In the present embodiment, due to screen 150
Image control circuit 200 is not coupled, therefore the voltage of first resistor is not below reference voltage VREF, therefore, detection signal SENSE_R
For low level.
815 during one operates, since screen 150 does not couple image control circuit 200, therefore the setting of logic circuit 145 is controlled
Signal PDSENSE processed is high level.Therefore, circuit for detecting 130,135 and 140 stoppings action.During this period, logic circuit 145
Control signal PDB, PDG and PDR are set one by one as high level.Therefore, switch 225,220 and 215 disconnects one by one, and image produces
Raw circuit 125,120 and 115 stops generating image current one by one.In other embodiments, logic circuit 145 simultaneously closes off switch
225th, 220 and 215.Therefore, image generation circuit 125,120 and 115 is simultaneously stopped action.Finally, the setting of logic circuit 145 control
Signal PDDAC processed is high level.At this point, current generating circuit 105,205 and 110 stopping of voltage generation circuit action.
Fig. 9 is another timing control figure of the image control circuit 200 of the present invention.In a baseline 905, logic circuit
145 first enable selection signal SENSEL, reset control signal PDDAC as low level, to starting current generation circuit 105,
Voltage generation circuit 205 and 110.Therefore, current generating circuit 105 generates reference current BIAS, and voltage generation circuit 110
Generate reference voltage VREF.At this point, reference current BIAS has one first level, and reference voltage VREF has one the 3rd electricity
It is flat.Then, logic circuit 145 sets control signal PDR, PDG and PDB as low level one by one, thus switch 215,220 and 225 by
One conducting.Therefore, image generation circuit 115,120 and 125 generates image current IR, IG, IB one by one.At this point, due to logic electricity
Road 145 makes control signal PDSENSE as high level, represents not yet to start circuit for detecting 130,135 and 140, therefore detection signal
SENSE_R is low level.
910 during one detects, logic circuit 145 sets control signal PDSENSE as low level, to start detecting electricity
Road 130,135 and 140.At this point, circuit for detecting 130,135 and 140 start detect first, second and third resistance voltage whether
Less than reference voltage VREF.Since the operating principle of circuit for detecting 130,135 and 140 is similar, thus it is following only with circuit for detecting 130
Exemplified by.It is assumed that screen 150 couples image control circuit 200.Since the voltage of first resistor is less than reference voltage VREF, therefore detect
It surveys signal SENSE_R and high level is changed to by low level.
915 during one operates, since detection signal SENSE_R is high level, therefore 145 forbidden energy selection signal of logic circuit
SENSEL.In the present embodiment, logic circuit 145 sets selection signal SENSEL as low level.Therefore, current generating circuit
105 increase reference current BIAS, and voltage generation circuit 110 increases reference voltage VREF.In this instance, reference current BIAS
One second electrical level is risen to by the first level, and reference voltage VREF rises to one the 4th level by the 3rd level.In this reality
It applies in example, the first level is the half of second electrical level, and the half that the 3rd level is the 4th level.During operation 915, it patrols
It collects circuit 145 and sets control signal PDSENSE as high level.Therefore, circuit for detecting 130,135 and 140 stops detecting first, the
Two and the voltage of 3rd resistor, therefore detection signal SENSE_R is low level.
In one embodiment, when control signal PDSENSE is high level, logic circuit 145 (is grasped in a set time
915 duration during work) after, control signal PDSNESE is set as low level.Therefore, 920 during detecting, detecting electricity
The voltage of first, second and third resistance is detected once again in road 130,135 and 140.It is assumed that screen 150 no longer couples image control
Circuit 200.Therefore, detection signal SENSE_R is low level.
During operation 925, logic circuit 145 sets control signal PDSENSE as high level, to stop detecting
First, the voltage of second and third resistance.During this period, since screen 150 does not couple image control circuit 200, therefore logic circuit
145 enable selection signal SENSEL.Therefore, current generating circuit 105 reduces reference current BIAS, and voltage generation circuit
110 reduce reference voltage VREF.In one embodiment, reference current BIAS is reduced to the first level by second electrical level, and joins
It examines voltage VREF and the 3rd level is reduced to by the 4th level.Then, logic circuit 145 set one by one control signal PDB, PDG and
PDR is high level, to disconnect switch 225,220 and 215 one by one.Therefore, image generation circuit 125,120 and 115 stops one by one
Only generate image current IB, IG and IR.
Due to image generation circuit 125,120 and 115, stopping acts one by one, therefore will not cause too big current jitter, and
And will not other circuits be caused with electromagnetic interference (EMI).Further, since logic circuit 145 according to circuit for detecting 130,135 and
140 detecting result, control current generating circuit 105 and voltage generation circuit 110, therefore image control is not coupled in screen 150
During circuit 200, reference current BIAS and reference voltage VREF is reduced, and image control circuit 200 is coupled in screen 150, is increased
Reference current BIAS and reference voltage VREF, therefore the power damage of voltage generation circuit 110 and current generating circuit 105 can be reduced
Consumption.
Unless otherwise defined, all vocabulary (including technology and scientific terms) belong in the technical field of the invention herein
The general understanding of those of ordinary skill.In addition, unless clear expression, definition of the vocabulary in general dictionary should be interpreted that and its phase
It is consistent to close meaning in the article of technical field, and should not be construed as perfect condition or too formal voice.
Although the present invention has been described by way of example and in terms of the preferred embodiments, however, it is not to limit the invention, any affiliated technology
Those of ordinary skill in field, without departing from the spirit and scope of the present invention, when can make a little change and retouch.Citing comes
It says, the system, device or method disclosed in the embodiment of the present invention can be with the realities of the combination of hardware, software or hardware and software
Body embodiment is realized.Therefore protection scope of the present invention is subject to appended as defined in claim.
Claims (16)
1. a kind of image control circuit, including：
Current generating circuit generates reference current according to selection signal；
Voltage generation circuit generates reference voltage according to the selection signal；
First image generation circuit couples first resistor, and generates the first image current according to the reference current；
Circuit for detecting detects the voltage of the first resistor, and the voltage of the first resistor and the reference voltage is made ratio
Compared with to generate the first detection signal；And
Logic circuit, according to selection signal described in the first detection signal enable or forbidden energy, wherein when the first resistor
When voltage is less than the reference voltage, selection signal described in the logic circuit forbidden energy, when the selection signal is disabled, institute
Stating current generating circuit increases the reference current and the voltage generation circuit increase reference voltage.
2. image control circuit according to claim 1, further includes：
Second image generation circuit couples second resistance, and generates the second image current according to the reference current；
The circuit for detecting, detects the voltage of the second resistance, and by the voltage of the second resistance and the reference voltage
It makes comparisons, to generate the second detection signal；
When none enable in first detection signal and second detection signal, then it represents that no display device is coupled to institute
State image control circuit；And
When the enable of at least one of first detection signal and second detection signal, then it represents that there is display device to be coupled to
The corresponding display dress of non-enable person in the image control circuit and the first detection signal and second detection signal
The circuit or the connection image control circuit and the circuit of the display device put/there are failures at pin/interface.
3. image control circuit according to claim 1, wherein the first image generation circuit includes：
The first transistor, grid receive the reference current, and source electrode receives operation voltage；
First switch is coupled between drain electrode and the ground nodes of the first transistor；And
Second switch is coupled between the drain electrode of the first transistor and the first resistor, wherein when the first switch
When being switched on, the second switch is not turned on, and when the second switch is switched on, the first switch is not turned on.
4. image control circuit according to claim 3, further includes：
Second image generation circuit, including：
Second transistor, grid receive the reference current, and source electrode receives the operation voltage；
3rd switch, is coupled between the drain electrode of the second transistor and the ground nodes；And
4th switch, is coupled between drain electrode and the second resistance of the second transistor, wherein when the described 3rd switch is led
When logical, the 4th switch disconnects, and when the described 4th switch is switched on, the 3rd switch disconnects；And
3rd image generation circuit, including：
Third transistor, grid receive the reference current, and source electrode receives the operation voltage；
5th switch, is coupled between the drain electrode of the third transistor and the ground nodes；And
6th switch, is coupled between drain electrode and the 3rd resistor of the third transistor, wherein when the described 5th switch is led
When logical, the 6th switch disconnects, and when the described 6th switch is switched on, the 5th switch disconnects.
5. image control circuit according to claim 4, further includes：
7th switch, is coupled between the current generating circuit and the first image generation circuit, to transmit the ginseng
It examines electric current and gives the first transistor；
8th switch, is coupled between the current generating circuit and the second image generation circuit, to transmit the ginseng
It examines electric current and gives the second transistor；And
9th switch, is coupled between the current generating circuit and the 3rd image generation circuit, to transmit the ginseng
It examines electric current and gives the third transistor.
6. image control circuit according to claim 5, wherein in baseline, choosing described in logic circuit elder generation enable
After selecting signal, start the current generating circuit and the voltage generation circuit, then turn on the described seven, the 8th and the 9th and open
It closes.
7. image control circuit according to claim 5, wherein the logic circuit turn on one by one described seven, the 8th and
9th switch.
8. image control circuit according to claim 5, wherein when the voltage of the first resistor is not less than the reference
During voltage, the logic circuit disconnects the nine, the 8th and the 7th switch one by one.
9. image control circuit according to claim 5, wherein when the voltage of the first resistor is not less than the reference
During voltage, selection signal described in the logic circuit enable, when the selection signal is enabled, the reference current has the
One level, when the selection signal is disabled, the reference current has second electrical level, and first level is less than described the
Two level.
10. image control circuit according to claim 5, wherein when the voltage of the first resistor is not less than the reference
During voltage, selection signal described in logic circuit elder generation enable, then the nine, the 8th and the 7th switch is disconnected one by one.
11. image control circuit according to claim 1, wherein the current generating circuit includes：
First operational amplifier has the first inverting input and the first in-phase input end, the first anti-phase input termination
Receive the first reference voltage；
4th transistor, grid couple the output terminal of first operational amplifier, and source electrode receives operation voltage, drain electrode
Couple first in-phase input end；
5th transistor, source electrode receive the operation voltage, and drain electrode couples first in-phase input end；And
Tenth switch, is coupled between the grid of the 4th transistor and the grid of the 5th transistor.
12. image control circuit according to claim 11, wherein the voltage of the first resistor is not less than the reference
During voltage, logic circuit conducting the tenth switch is described when the voltage of the first resistor is less than the reference voltage
Logic circuit disconnects the tenth switch.
13. image control circuit according to claim 1, wherein the voltage of the first resistor is not less than the reference electricity
During pressure, the selection signal is enabled, and when the selection signal is enabled, the reference voltage has the 3rd level, works as institute
When stating selection signal and being disabled, the reference voltage has the 4th level, and the 3rd level is less than the 4th level.
14. image control circuit according to claim 1, wherein the current generating circuit includes：
Second operational amplifier has the second inverting input and the second in-phase input end, the second anti-phase input termination
Receive the second reference voltage；
6th transistor, grid couple the output terminal of the second operational amplifier, and source electrode receives operation voltage, drain electrode
Couple second in-phase input end；
Resistance string is coupled between drain electrode and the ground nodes of the 6th transistor, to generate multiple partial pressures；And
Selector according to the selection signal, selects one as the reference voltage from the partial pressure.
15. image control circuit according to claim 14, wherein the 4th level is less than second reference voltage.
16. image control circuit according to claim 1, wherein the current generating circuit converts the first reference voltage,
To generate the reference current, the voltage generation circuit converts the second reference voltage, to generate the reference voltage, institute
The first reference voltage is stated not equal to second reference voltage.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711434182.3A CN108107962B (en) | 2017-12-26 | 2017-12-26 | Image control circuit |
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| CN201711434182.3A CN108107962B (en) | 2017-12-26 | 2017-12-26 | Image control circuit |
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| CN108107962B CN108107962B (en) | 2020-09-15 |
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Cited By (1)
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| WO2024049230A1 (en) * | 2022-09-02 | 2024-03-07 | 주식회사 엘엑스세미콘 | Patterned resistance detection circuit and method for detecting patterned resistance of display panel |
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