CN107819036B - Source and drain symmetrically interchangeable double bracket shape grid-control tunneling transistor and its manufacturing method - Google Patents
Source and drain symmetrically interchangeable double bracket shape grid-control tunneling transistor and its manufacturing method Download PDFInfo
- Publication number
- CN107819036B CN107819036B CN201711046023.6A CN201711046023A CN107819036B CN 107819036 B CN107819036 B CN 107819036B CN 201711046023 A CN201711046023 A CN 201711046023A CN 107819036 B CN107819036 B CN 107819036B
- Authority
- CN
- China
- Prior art keywords
- drain
- source
- interchangeable
- insulating layer
- heavy doping
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000005641 tunneling Effects 0.000 title claims abstract description 34
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 230000005669 field effect Effects 0.000 claims abstract description 24
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 55
- 239000010409 thin film Substances 0.000 claims description 54
- 230000004888 barrier function Effects 0.000 claims description 34
- 239000000758 substrate Substances 0.000 claims description 31
- 238000000151 deposition Methods 0.000 claims description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 17
- 229910052710 silicon Inorganic materials 0.000 claims description 17
- 239000010703 silicon Substances 0.000 claims description 17
- 238000009413 insulation Methods 0.000 claims description 15
- 230000009471 action Effects 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 13
- 239000002184 metal Substances 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 9
- 239000007769 metal material Substances 0.000 claims description 9
- 229920005591 polysilicon Polymers 0.000 claims description 8
- 235000008429 bread Nutrition 0.000 claims description 7
- 230000008569 process Effects 0.000 claims description 7
- 238000001259 photo etching Methods 0.000 claims description 6
- 239000002210 silicon-based material Substances 0.000 claims description 6
- 230000005611 electricity Effects 0.000 claims description 5
- 239000010408 film Substances 0.000 claims description 4
- 238000009792 diffusion process Methods 0.000 claims description 3
- 239000011810 insulating material Substances 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 238000009826 distribution Methods 0.000 claims 1
- 230000000694 effects Effects 0.000 abstract description 7
- 230000008901 benefit Effects 0.000 abstract description 6
- 230000003068 static effect Effects 0.000 abstract description 3
- 230000008859 change Effects 0.000 abstract description 2
- 238000005036 potential barrier Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000035508 accumulation Effects 0.000 description 3
- 238000009825 accumulation Methods 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 230000007246 mechanism Effects 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000010355 oscillation Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000002457 bidirectional effect Effects 0.000 description 1
- 230000002146 bilateral effect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
The present invention relates to source and drain symmetrically interchangeable double bracket shape grid-control tunneling transistor and its manufacturing methods, device of the present invention, which has, folds supplementary gate, double bracket grid and medianly zygomorphic structure feature, with stronger grid control ability and the interchangeable area of heavy doping source and drain can be controlled as source region or drain region by adjusting the voltage of the interchangeable electrode of source and drain, change tunnelling current direction.The present invention has the function of the advantages of achievable two-way switch, low speed paper tape reader static power disspation and reverse leakage current, stronger grid control ability, low subthreshold swing.In contrast to common MOSFETs type device, more excellent switching characteristic is realized using tunneling effect；In contrast to common tunneling field-effect transistor, the present invention has the symmetrically interchangeable two-way switch characteristic of source and drain not available for common tunneling field-effect transistor, therefore is suitble to promote and apply.
Description
Technical field
The present invention relates to super large-scale integration manufacturing fields, and in particular to one kind is suitable for low power consumption integrated circuit system
The source and drain made symmetrically interchangeable double bracket shape grid-control tunneling transistor and its manufacturing method.
Background technique
The basic unit MOSFETs of integrated circuit can become smaller and smaller according to the requirement of Moore's Law, size, therewith
What is come is not only that difficulty in manufacturing process is deepened, various ill effects also highlighting more.Nowadays IC design
Itself generates the limitation of the physical mechanism of electric current when used MOSFETs type device is due to its work, and subthreshold swing is not
60mV/dec can be lower than.And commonly tunneling field-effect transistor is as switching-type device in use, using carrier in semiconductor
Conduction mechanism of the tunneling effect as electric current occurs between energy band, subthreshold swing will be substantially better than MOSFETs type device
The 60mv/dec limit.However, common tunneling field-effect transistor source region and drain region use the impurity of different conduction-types, it is this non-
Symmetrical structure feature causes it that can not functionally replace the MOSFETs type device with symmetrical structure feature completely.With N-type tunnel
For wearing field effect transistor, if its source electrode and drain electrode exchanged, i.e., drain electrode is low potential, and source electrode is high potential, then tunnelling
Field effect transistor will be in the conductive state always, and the size of conducting electric current is no longer able to be well controlled by gate electrode
And adjusting, this makes the switching characteristic of entire tunneling field-effect transistor fail.
Summary of the invention
Goal of the invention
In order to effectively combine and utilize MOSFETs type device source electrode, the interchangeable and common tunneling field-effect transistor of drain electrode
The advantages of low subthreshold swing amplitude of oscillation, solving MOSFETs type device subthreshold swing can not reduce and common tunneling field-effect crystalline substance
Body pipe can only propose a kind of source and drain symmetrically interchangeable double bracket shape grid-control tunneling transistor as the deficiency of single-way switch, the present invention
Structure and its manufacturing method.The transistor has logic function and is currently based on the completely compatible advantage of MOSFETs integrated circuit
Feature, the symmetry of source and drain two-end structure, which allows to exchange by the voltage to source electrode and drain electrode, realizes that source and drain bi-directional symmetrical is opened
The function of pass has forward and reverse electric current than high and low subthreshold value with the interchangeable two-way switch characteristic of source-drain electrode, additionally
The working characteristics such as the amplitude of oscillation, high forward conduction electric current.
Technical solution
The present invention is achieved through the following technical solutions:
The symmetrical interchangeable double bracket shape grid-control tunneling transistor of source and drain, the silicon substrate comprising SOI wafer, it is characterised in that:
It is the substrate insulating layer of SOI wafer above the silicon substrate of SOI wafer, the top of the substrate insulating layer of SOI wafer is that monocrystalline silicon is thin
Film, the partial region for folding supplementary gate, the interchangeable intrinsic region a of source and drain, the interchangeable intrinsic region b of source and drain, heavy doping source and drain are interchangeable
The interchangeable area b of area a, heavy doping source and drain, the partial region of grid electrode insulating floor, double bracket shape gate electrode and insulating medium barrier layer
Partial region；The left and right ends of monocrystalline silicon thin film respectively constitute the interchangeable intrinsic region a of source and drain and the interchangeable intrinsic region b of source and drain；
The interchangeable area a of the heavy doping source and drain and interchangeable area b of heavy doping source and drain is built in the left and right sides of monocrystalline silicon thin film respectively, and source and drain can
It exchanges intrinsic region a counterweight doped source and drain three bread of interchangeable area a formation to wrap up in, the interchangeable intrinsic region b counterweight doped source and drain of source and drain can
Area b three bread of formation are exchanged to wrap up in；
The substrate of the bottom surface and SOI wafer of the interchangeable area a of heavy doping source and drain and the interchangeable area b of heavy doping source and drain is exhausted
The upper surface of edge layer contacts with each other；Grid electrode insulating layer is insulating material, to monocrystalline silicon thin film except the substrate with SOI wafer
Surface region other than the lower surface of insulating layer contact forms package, by monocrystalline silicon thin film, the interchangeable intrinsic region a of source and drain, source and drain
The cube that the interchangeable area a of interchangeable intrinsic region b, heavy doping source and drain and the interchangeable area b of heavy doping source and drain are constituted is all around
Outer surface and cube it is upper other than the upper surface of the interchangeable area a of heavy doping source and drain and the interchangeable area b of heavy doping source and drain
Surface is completely covered；The outer surface side wall and folding supplementary gate, double bracket shape gate electrode and insulation of grid electrode insulating layer are situated between
The partial region on matter barrier layer contacts with each other；It folds supplementary gate to be made of metal material or polycrystalline silicon material, falls frame in " recessed " shape
Front and rear sides outer surface and upper surface phase mutual connection above grid electrode insulating layer, with grid electrode insulating layer middle region part
Touching；Double bracket shape gate electrode is made of metal material or polycrystalline silicon material, positioned at the left and right sides of grid electrode insulating layer, and and grid
Upper and lower surface and left and right outer surface at left and right sides of electrode dielectric layer contact with each other, and overlooking viewing is in a pair of of double bracket shape,
Bracket shape gate electrode part corresponding to the every side of double bracket shape gate electrode is corresponding to the side grid electrode insulating layer and inside
The interchangeable intrinsic region a of the source and drain or interchangeable intrinsic region b of source and drain forms three faces and surrounds, and is powered on by controlling double bracket shape gate electrode
The field-effect of gesture controls the Carrier Profile inside the interchangeable intrinsic region a of the source and drain and interchangeable intrinsic region b of source and drain；Gate electrode is exhausted
Edge layer forms insulation barrier between double bracket shape gate electrode and monocrystalline silicon thin film, and grid electrode insulating layer is folding supplementary gate and list
Also insulation barrier is formed between polycrystal silicon film；Double bracket shape gate electrode and fold supplementary gate between by insulating medium barrier layer that
This insulation；Double bracket shape gate electrode is only to the interchangeable intrinsic region a of source and drain for being located at monocrystalline silicon thin film two sides and source and drain interchangeable
Sign area b has obvious field-effect control action, and to the middle section of monocrystalline silicon thin film without obvious control action；Fold supplementary gate only
There is obvious control action to monocrystalline silicon thin film middle section, and to the interchangeable intrinsic region a of source and drain for being located at monocrystalline silicon thin film two sides
There is no obvious control action with the interchangeable intrinsic region b of source and drain；The top of grid electrode insulating layer, which is removed, is folded the upper of supplementary gate covering
Upper surface other than surface region is covered by insulating medium barrier layer；The interchangeable electrode a of source and drain and the interchangeable electrode b of source and drain are
Metal material is constituted, and is located at the top of the interchangeable area a of heavy doping source and drain and the interchangeable area b of heavy doping source and drain, and phase each other
Mutually contact；The outer surface of the upper section and section below of the interchangeable electrode a of source and drain and the interchangeable electrode b of source and drain respectively with grid
Insulating medium barrier layer and grid electrode insulating layer contact with each other；Folding part at left and right sides of supplementary gate is in symmetrical structure, Neng Gou
The interchangeable electrode a of the source and drain and interchangeable electrode b of source and drain realizes same output characteristics in the case where symmetrically exchanging.
The manufacturing method of the symmetrical interchangeable double bracket shape grid-control tunneling transistor of source and drain, it is characterised in that:
Its manufacturing step is as follows:
Step 1: providing a SOI wafer, and bottom is the silicon substrate of SOI wafer, and the upper surface of silicon substrate is SOI wafer
Substrate insulating layer, the upper surface of the substrate insulating layer of SOI wafer is monocrystalline silicon thin film, passes through photoetching, etching technics removes SOI
The partial region in the outside of the monocrystalline silicon thin film surrounding above wafer；
Step 2: by ion implanting or diffusion technique, to the left and right sides of monocrystalline silicon thin film formed in step 1
Intermediate region symmetric position carry out high doped, be respectively formed the interchangeable area a of heavy doping source and drain and heavy doping source and drain be interchangeable
Area b；
Step 3: by oxidation or depositing technics, the upper surface of the monocrystalline silicon thin film after being close to doping and outer surface, shape
At planarization process after insulating medium layer, grid electrode insulating layer is preliminarily formed；
Step 4: by depositing technics, dielectric is deposited in the top of grid electrode insulating layer, is planarized to and exposes grid electricity
After the insulating layer of pole, then by etching technics etch away sections dielectric, preliminarily form SI semi-insulation dielectric barrier；
Step 5: by depositing technics, in wafer upper electrode metal or polysilicon, surface is planarized to exposing gate electrode
Insulating layer forms metal or polysilicon layer in the front and rear sides intermediate region of grid electrode insulating layer and two side areas, forms double include
Number shape gate electrode, and preliminarily form folding supplementary gate；
Step 6: dielectric is deposited above wafer, and middle section is etched away by etch areas, then pass through deposit
Technique deposits metal or polysilicon, is connected with the folding supplementary gate preliminarily formed in step 5, planarizes surface laggard one
Step, which is formed, folds supplementary gate and insulating medium barrier layer；
Step 7: by depositing technics, depositing dielectric above wafer, passes through photoetching, quarter again after planarizing surface
Etching technique removes grid electrode insulating floor and insulation Jie above the interchangeable area a and interchangeable area b of heavy doping source and drain of heavy doping source and drain
Matter barrier layer forms through-hole to the upper surface for exposing heavy doping source and drain interchangeable area a and the interchangeable area b of heavy doping source and drain, then leads to
It crosses deposit metal and forms the interchangeable electrode a of source and drain and the interchangeable electrode b of source and drain in through-holes, then is further by planarization process
Form insulating medium barrier layer.
Advantage and effect
The invention has the following advantages and beneficial effects:
1. the symmetrical interchangeable two-way switch characteristic of source and drain:
Device of the present invention is source and drain symmetrically interchangeable double bracket shape grid-control tunneling transistor, a left side for monocrystalline silicon thin film 1
Right both ends are respectively provided with tunneling structure independent of each other close to the part of grid electrode insulating layer 7, since device has bilateral symmetry
Structure, under the control action of double bracket shape gate electrode 8,1 left and right ends of monocrystalline silicon thin film are being contacted with grid electrode insulating layer 7
Nearby simultaneously tunnelling occurs for surface, in conjunction with supplementary gate 2 is folded to the adjustment effect of 1 center portion potential of monocrystalline silicon thin film, makes device
Part forms forward conduction and reversed blocking, passes through the voltage for adjusting source and drain interchangeable electrode a 9 and the interchangeable electrode b 10 of source and drain
It controls the interchangeable area a 5 of the heavy doping source and drain and interchangeable area b 6 of heavy doping source and drain and is used as source region or drain region, therefore changeable tunnelling
Current direction realizes source and drain of the invention symmetrically interchangeable two-way switch characteristic.
2. low subthreshold swing:
Since the present invention is the tunneling mechanism based on tunneling field-effect transistor, and symmetrical double bracket grid structure is used, by
In being located at source, leakage side bracket gate electrode intrinsic region a 3 interchangeable to source and drain and source and drain interchangeable respectively in three directions
Sign area b 4 forms three bread and wraps up in, and there is outstanding gate electrode control ability to make it possible to band under the control action of gate electrode 8 and exist
It is easier to bend under identical gate voltage, obtains bigger electric field strength, so that tunneling efficiency increases, compared to
MOSFETs type device and common tunneling field-effect transistor, can get lower subthreshold swing.
3. low speed paper tape reader static power disspation, low reverse leakage current and high forward and reverse electric current ratio:
By taking N-shaped as an example, the interchangeable area a 5 of heavy doping source and drain and the interchangeable area b 6 of heavy doping source and drain are adulterated at this time for p-type,
When between the interchangeable area a 5 of heavy doping source and drain, the interchangeable area b 6 of heavy doping source and drain there are when potential difference, and when double bracket grid electricity
Pole 8 is in subthreshold value or reverse-biased, always works at positively biased state due to folding supplementary gate 2, is located at 1 two sides of monocrystalline silicon thin film
The interchangeable intrinsic region a 3 of source and drain and the potential of the interchangeable intrinsic region b 4 of source and drain folded lower than 1 center portion of monocrystalline silicon thin film
The potential of 2 control section of supplementary gate, by the field-effect of double bracket gate electrode 8 control in interchangeable 3 He of intrinsic region a of source and drain
The hole and the interchangeable area a 5 of heavy doping source and drain and the interchangeable area b 6 of heavy doping source and drain that the interchangeable intrinsic region b 4 of source and drain is accumulated
It interior hole all can not be and common by by folding that supplementary gate 2 controls in the formed potential barrier of 1 center portion of monocrystalline silicon thin film
MOSFETs or tunnel field-effect transistor structure are compared, and both there is no the relatively stroke field intensity area domains between drain electrode and gate electrode (i.e.
Can not form and electron hole pair is largely formed by by tunnel-effect), and the auxiliary control action due to folding supplementary gate 2, in list
1 center portion of polycrystal silicon film is formed by that potential barrier can effectively be blocked in the interchangeable area a 5 of heavy doping source and drain and heavy doping source and drain can
The formation of hole current between exchange area b 6, between the interchangeable intrinsic region a 3 of source and drain and the interchangeable intrinsic region b 4 of source and drain.
Therefore the present invention has the advantages that low speed paper tape reader static power disspation, low reverse leakage current and high forward and reverse electric current ratio.
Detailed description of the invention
Fig. 1 is the top view of the symmetrical interchangeable double bracket shape grid-control tunneling transistor of source and drain of the present invention；
Fig. 2 is the sectional view along dotted line A of the symmetrical interchangeable double bracket shape grid-control tunneling transistor of source and drain of the present invention；
Fig. 3 is the sectional view along dotted line B of the symmetrical interchangeable double bracket shape grid-control tunneling transistor of source and drain of the present invention；
Fig. 4 is the sectional view along dotted line C of the symmetrical interchangeable double bracket shape grid-control tunneling transistor of source and drain of the present invention；
Fig. 5 is the top view of step 1；
Fig. 6 is the sectional view along dotted line A of step 1；
Fig. 7 is the sectional view along dotted line B of step 1；
Fig. 8 is the top view of step 2；
Fig. 9 is the sectional view along dotted line A of step 2；
Figure 10 is the sectional view along dotted line B of step 2；
Figure 11 is the top view of step 3；
Figure 12 is the sectional view along dotted line A of step 3；
Figure 13 is the sectional view along dotted line B of step 3；
Figure 14 is the top view of step 4；
Figure 15 is the sectional view along dotted line A of step 4；
Figure 16 is the sectional view along dotted line B of step 4；
Figure 17 is the top view of step 5；
Figure 18 is the sectional view along dotted line A of step 5；
Figure 19 is the sectional view along dotted line B of step 5；
Figure 20 is the sectional view along dotted line C of step 5；
Figure 21 is the top view of step 6；
Figure 22 is the sectional view along dotted line A of step 6；
Figure 23 is the sectional view along dotted line B of step 6；
Figure 24 is the sectional view along dotted line C of step 6；
Figure 25 is the top view of step 7；
Figure 26 is the sectional view along dotted line A of step 7；
Figure 27 is the sectional view along dotted line B of step 7；
Figure 28 is the sectional view along dotted line C of step 7.
Description of symbols:
1, monocrystalline silicon thin film；2, supplementary gate is folded；3, the interchangeable intrinsic region a of source and drain；4, the interchangeable intrinsic region b of source and drain；5 weights
The interchangeable area a of doped source and drain；6, the interchangeable area b of heavy doping source and drain；7, grid electrode insulating layer；8, double bracket gate electrode；9, source and drain
Interchangeable electrode a；10, the interchangeable electrode b of source and drain；11, substrate insulating layer；12, silicon substrate；13, insulating medium barrier layer.
Specific embodiment
Following further describes the present invention with reference to the drawings:
As shown in Figure 1, Figure 2, Figure 3 and Figure 4, the symmetrical interchangeable double bracket shape grid-control tunneling transistor of source and drain, it is brilliant comprising SOI
Round silicon substrate 12 is the substrate insulating layer 11 of SOI wafer, the substrate insulating layer of SOI wafer above the silicon substrate 12 of SOI wafer
11 top is monocrystalline silicon thin film 1, the partial region for folding supplementary gate 2, the interchangeable intrinsic region a 3 of source and drain, source and drain interchangeable
Levy area b 4, the interchangeable area a 5 of heavy doping source and drain, the interchangeable area b 6 of heavy doping source and drain, grid electrode insulating floor 7 partial region,
The partial region of double bracket shape gate electrode 8 and insulating medium barrier layer 13；The left and right ends of monocrystalline silicon thin film 1 respectively constitute source and drain
The interchangeable intrinsic region a 3 and interchangeable intrinsic region b 4 of source and drain；The interchangeable area a 5 of heavy doping source and drain and heavy doping source and drain are interchangeable
Area b 6 is built in the left and right sides of monocrystalline silicon thin film 1, the interchangeable area a of the interchangeable 3 counterweight doped source and drain of intrinsic region a of source and drain respectively
5 three bread of formation are wrapped up in, and the interchangeable area b 6 of the interchangeable 4 counterweight doped source and drain of intrinsic region b of source and drain forms three bread and wraps up in；
The lining of the bottom surface and SOI wafer of the interchangeable area a 5 of heavy doping source and drain and the interchangeable area b 6 of heavy doping source and drain
The upper surface of bottom insulating layer 11 contacts with each other；Grid electrode insulating layer 7 is insulating material, to monocrystalline silicon thin film 1 except brilliant with SOI
Surface region other than the lower surface that round substrate insulating layer 11 contacts forms package, by monocrystalline silicon thin film 1, source and drain interchangeable
Levy area a 3, the interchangeable intrinsic region b 4 of source and drain, the interchangeable area a 5 of heavy doping source and drain and heavy doping source and drain 6 structures of interchangeable area b
At cube outer surface all around and cube in addition to the interchangeable area a 5 of heavy doping source and drain and heavy doping source and drain it is interchangeable
Upper surface other than the upper surface of area b 6 is completely covered；The outer surface side wall of grid electrode insulating layer 7 with fold supplementary gate 2, double
The partial region of bracket shape gate electrode 8 and insulating medium barrier layer 13 contacts with each other；Supplementary gate 2 is folded by metal material or more
Crystal silicon material is constituted, and frame is fallen above grid electrode insulating layer 7 in " recessed " shape, before 7 middle region part of grid electrode insulating layer
Two side external surfaces and upper surface contact with each other afterwards；Double bracket shape gate electrode 8 is made of metal material or polycrystalline silicon material, is located at
The left and right sides of grid electrode insulating layer 7, and it is mutual with the upper and lower surface of 7 left and right sides of grid electrode insulating layer and left and right outer surface
Contact, overlooking viewing is in a pair of of double bracket shape, bracket shape gate electrode part pair corresponding to the every side of double bracket shape gate electrode 8
The side grid electrode insulating layer 7 and the internal corresponding source and drain interchangeable intrinsic region a 3 or interchangeable intrinsic region b 4 of source and drain form three
Face surrounds, and controls the interchangeable intrinsic region a 3 of source and drain and source and drain by the field-effect of potential added by control double bracket shape gate electrode 8
Carrier Profile inside interchangeable intrinsic region b 4；Grid electrode insulating layer 7 double bracket shape gate electrode 8 and monocrystalline silicon thin film 1 it
Between form insulation barrier, grid electrode insulating layer 7 also forms insulation barrier between supplementary gate 2 and monocrystalline silicon thin film 1 folding；It is double to include
It number shape gate electrode 8 and folds insulated from each other by insulating medium barrier layer 13 between supplementary gate 2；Double bracket shape gate electrode 8 is only right
The interchangeable intrinsic region a 3 of source and drain and the interchangeable intrinsic region b 4 of source and drain positioned at 1 two sides of monocrystalline silicon thin film have obvious field-effect to control
Effect, and to the middle section of monocrystalline silicon thin film 1 without obvious control action；Supplementary gate 2 is folded only to 1 central area of monocrystalline silicon thin film
There is obvious control action in domain, and interchangeable intrinsic to the interchangeable intrinsic region a 3 of source and drain and source and drain that are located at 1 two sides of monocrystalline silicon thin film
Area b 4 is without obvious control action；The top of grid electrode insulating layer 7 is in addition to the surface area for being folded the covering of supplementary gate 2
Upper surface covered by insulating medium barrier layer 13；The interchangeable electrode a 9 of the source and drain and interchangeable electrode b 10 of source and drain is metal
Material is constituted, and is located at the top of the interchangeable area a 5 of heavy doping source and drain and the interchangeable area b 6 of heavy doping source and drain, and phase each other
Mutually contact；The outer surface of the upper section and section below of the interchangeable electrode a 9 of source and drain and the interchangeable electrode b 10 of source and drain point
It does not contact with each other with gate insulation dielectric barrier 13 and grid electrode insulating layer 7；Folding 2 left and right sides part of supplementary gate is in symmetrical junction
Structure can realize same output in the case where the interchangeable electrode a 9 of source and drain and the interchangeable electrode b 10 of source and drain are symmetrically exchanged
Characteristic.
The present invention provides a kind of source and drain symmetrically interchangeable double bracket shape grid-control tunneling transistor, has symmetrical structure
Feature, it is interchangeable that the voltage by adjusting the interchangeable electrode a 9 and interchangeable electrode b 10 of source and drain of source and drain controls heavy doping source and drain
Area a 5 and the interchangeable area b 6 of heavy doping source and drain are used as source region or drain region, change tunnelling current direction, device is made to realize two-way tunnel
Perforate logical source and drain symmetrically interchangeable characteristic.
By taking the interchangeable area a 5 of the heavy doping source and drain and interchangeable area b 6 of heavy doping source and drain is p type impurity as an example, work as heavy doping
There are when potential difference between the interchangeable area a 5 of source and drain, the interchangeable area b 6 of heavy doping source and drain, and when double bracket gate electrode 8 is in negative
Reverse-biased is pressed, by double bracket gate electrode field-effect function influence, the interchangeable area a 5 of heavy doping source and drain can be to source and drain interchangeable
Hole can be provided to the interchangeable intrinsic region b 4 of source and drain by levying area a 3 and providing the interchangeable area b 6 of hole, heavy doping source and drain, therefore can be
The interchangeable intrinsic region a 3 of the source and drain and interchangeable intrinsic region b 4 of source and drain generates hole accumulation, so that the interchangeable intrinsic region a of source and drain
The 3 and interchangeable intrinsic region b 4 of source and drain shows p-type state at this time, and the hole accumulated makes interchangeable 3 He of intrinsic region a of source and drain
(i.e. source region, drain region are in low-resistance shape to resistance decrease to the interchangeable intrinsic region b 4 of source and drain under the action of double bracket gate electrode 8
State), but apply forward voltage always due to folding supplementary gate 2, intrinsic region a 3 interchangeable to the source and drain of two sides and source and drain are interchangeable
Hole in intrinsic region b 4 forms potential barrier, and to the interchangeable area a 5 of the heavy doping source and drain of two sides, the interchangeable area b of heavy doping source and drain
Hole in 6 also forms potential barrier, and is influenced by the applied forward voltage field-effect of supplementary gate 2 is folded, and folding auxiliary is controlled by
N-type semiconductor state can be presented in the center portion of the monocrystalline silicon thin film 1 of grid 2, so that the source and drain for showing p-type feature is interchangeable intrinsic
Area a 3 and the center portion for the monocrystalline silicon thin film 1 for being at this time N-type form reverse-biased PN junction structure under drain-source voltage effect, because
This is in negative pressure reverse-biased when double bracket gate electrode 8, brilliant since in transistor internal, there is above-mentioned reverse-biased PN junction structures
High resistant blocking state is integrally presented in body pipe；As the voltage that double bracket gate electrode 8 is applied gradually rises up to flat rubber belting from negative voltage
Near voltage, the interchangeable area a 5 of heavy doping source and drain will not provide a large amount of holes, heavy-doped source to the interchangeable intrinsic region a 3 of source and drain
A large amount of holes will not be provided to the interchangeable intrinsic region b 4 of source and drain by leaking interchangeable area b 6, simultaneously because source and drain is interchangeable intrinsic at this time
Field strength is lower in the area a 3 and interchangeable intrinsic region b 4 of source and drain, and band curvature degree is smaller, therefore will not be interchangeable in source and drain
A large amount of tunelling electrons holes pair are generated between intrinsic region a 3 and the conduction band and valence band of the interchangeable intrinsic region b 4 of source and drain, therefore in source
It leaks and both can not form a large amount of hole accumulations in the interchangeable intrinsic region a 3 and interchangeable intrinsic region b 4 of source and drain, also can not form a large amount of electronics
Accumulation, the interchangeable intrinsic region a 3 of the source and drain of transistor and the interchangeable intrinsic region b 4 of source and drain be in high-impedance state (i.e. source region and
Drain region is in high-impedance state), therefore entire transistor does not have obvious electric current and flows through, device has outstanding turn-off characteristic at this time
And Sub-Threshold Characteristic；The voltage being applied with double bracket gate electrode 8 further rises to forward bias condition by flat-band voltage,
At this time in the interchangeable intrinsic region a 3 of the source and drain and interchangeable intrinsic region b of source and drain 4 by 8 field-effect function influence of double bracket gate electrode,
It will appear larger electric field strength and stronger band curvature, therefore apparent tunnel-effect can occur, so that source and drain is interchangeable intrinsic
A large amount of electron hole pairs are formed in area a 3 and the interchangeable intrinsic region b 4 of source and drain, wherein interchangeable of the source and drain as source region one end
Levying hole caused by area can be discharged via the interchangeable area of heavy doping source and drain at the end, and generated electrons are via auxiliary by folding
The center portion for the monocrystalline silicon thin film 1 for helping grid 2 to control is formed by n-type region, flows to interchangeable as the source and drain of drain region one end
The valence band hole as caused by tunnel-effect occurs compound in intrinsic region, with the interchangeable intrinsic region of source and drain as drain region one end.
And the conduction band electron as caused by tunnel-effect can be via as drain region in the interchangeable intrinsic region of source and drain as drain region one end
The interchangeable area of heavy doping source and drain, it is compound with the generation of its valence band hole, continuous conducting electric current is formed by above-mentioned physical process.By
The concentration of electron-hole pairs caused by tunnel-effect can with the rising of the be applied voltage of double bracket gate electrode 8 and gradually on
Rise, the concentration of electron-hole pairs increase caused by the tunnel-effect to a certain extent when, transistor is transitted to by sub-threshold status
Forward conduction state.
Since device has symmetrical structure feature on source and drain direction, it is different from common tunneling field-effect
Transistor, a kind of modifiable bidirectional tunneling field effect transistor of source and drain resistance control formula conductivity type proposed by the invention, source
Area and drain region may be implemented to exchange function.
To reach device function of the present invention, the present invention proposes source and drain, and symmetrically interchangeable double bracket shape grid-control tunnelling is brilliant
Body pipe, nuclear structure feature are as follows:
Device of the present invention is a kind of source and drain symmetrically interchangeable double bracket shape grid-control tunneling transistor, has double bracket grid
The structure of pole, in contrast to planar structure, is located near gate electrode corner region when double bracket gate electrode 8 is in positively biased state
Electric field strength can be strengthened, cause generate carrier probability increase under same gate voltage so that subthreshold swing has
Decline, forward conduction electric current is increased；Device of the present invention is a kind of source and drain symmetrically interchangeable double bracket shape grid-control tunnel
Transistor is worn, two sides are in symmetrical structure.The center portion that monocrystalline silicon thin film 1 is controlled by folding supplementary gate 2, by being disposed at
The majority carrier of specific fixed voltage value, the interchangeable area of counterweight doped source and drain forms potential barrier, inhibits reverse-biased and subthreshold value shape
The size of leakage current under state.The center portion for folding the monocrystalline silicon thin film 1 that supplementary gate 2 is controlled can be mutual with heavy doping source and drain
The interchangeable area b 6 of area a 5, heavy doping source and drain is changed with opposite impurity type.It is symmetrical as possessed by device of the present invention
Structure, by the interchangeable source-drain electrode 19 of control and the interchangeable area a 5 of the control of interchangeable source-drain electrode 210 heavy doping source and drain and again
The interchangeable area b 6 of doped source and drain is used as source region or drain region, realizes the interchangeable two-way switch characteristic of device source and drain.
The unit of the symmetrical interchangeable double bracket shape grid-control tunneling transistor of source and drain proposed by the invention is in SOI wafer
Specific manufacturing technology steps are as follows:
Step 1: as shown in Fig. 5, Fig. 6 and Fig. 7, providing a SOI wafer, and bottom is the silicon substrate 12 of SOI wafer,
The upper surface of silicon substrate is the substrate insulating layer 11 of SOI wafer, and the upper surface of the substrate insulating layer 11 of SOI wafer is monocrystalline silicon thin film
1, the partial region in the outside of 1 surrounding of monocrystalline silicon thin film above SOI wafer is removed by photoetching, etching technics；
Step 2: as shown in Fig. 8, Fig. 9 and Figure 10, by ion implanting or diffusion technique, to formed in step 1
The intermediate region symmetric position of the left and right sides of monocrystalline silicon thin film 1 carries out high doped, and it is interchangeable to be respectively formed heavy doping source and drain
The area a 5 and interchangeable area b 6 of heavy doping source and drain；
Step 3: as shown in Figure 11, Figure 12 and Figure 13, by oxidation or depositing technics, the monocrystalline silicon after being close to doping is thin
The upper surface of film 1 and outer surface form planarization process after insulating medium layer, preliminarily form grid electrode insulating layer 7；
Step 4: as shown in Figure 14, Figure 15 and Figure 16, by depositing technics, in the top of grid electrode insulating layer 7, deposit is exhausted
Edge medium is planarized to after exposing grid electrode insulating layer 7, then by etching technics etch away sections dielectric, is preliminarily formed
SI semi-insulation dielectric barrier 13；
Step 5: as shown in Figure 17, Figure 18, Figure 19 and Figure 20, by depositing technics, in wafer upper electrode metal or more
Crystal silicon, planarization surface is to grid electrode insulating layer 7 is exposed, in the front and rear sides intermediate region and two lateral areas of grid electrode insulating layer 7
Domain forms metal or polysilicon layer, forms double bracket shape gate electrode 8, and preliminarily forms and fold supplementary gate 2；
Step 6: as shown in Figure 21, Figure 22, Figure 23 and Figure 24, dielectric is deposited above wafer, and pass through etched area
Domain etches away middle section, then by depositing technics to deposit the folding preliminarily formed in metal or polysilicon, with step 5 auxiliary
It helps grid 2 to be connected, is further formed folding supplementary gate 2 and insulating medium barrier layer 13 after planarizing surface；
Step 7: as shown in Figure 25, Figure 26, Figure 27 and Figure 28, by depositing technics, deposit insulation is situated between above wafer
Matter removes the interchangeable area a 5 of heavy doping source and drain by photoetching, etching technics again after planarizing surface and heavy doping source and drain is interchangeable
The grid electrode insulating floor 7 and insulating medium barrier layer 13 of the top area b 6 are to exposing the interchangeable area a 5 of heavy doping source and drain and heavy doping
The upper surface of the interchangeable area b 6 of source and drain forms through-hole, then forms the interchangeable electrode a 9 of source and drain in through-holes by depositing metal
With the interchangeable electrode b 10 of source and drain, then insulating medium barrier layer 13 is further formed by planarization process.
Claims (2)
1. the symmetrical interchangeable double bracket shape grid-control tunneling transistor of source and drain, the silicon substrate (12) comprising SOI wafer, feature exists
In: it is the substrate insulating layer (11) of SOI wafer above the silicon substrate (12) of SOI wafer, the substrate insulating layer (11) of SOI wafer
Top is monocrystalline silicon thin film (1), folds the partial region of supplementary gate (2), the interchangeable intrinsic region a(3 of source and drain), source and drain interchangeable
Levy area b(4), the interchangeable area a(5 of heavy doping source and drain), the interchangeable area b(6 of heavy doping source and drain), the part of grid electrode insulating layer (7)
Region, double bracket shape gate electrode (8) and insulating medium barrier layer (13) partial region；The left and right ends of monocrystalline silicon thin film (1)
Respectively constitute the interchangeable intrinsic region a(3 of source and drain) and the interchangeable intrinsic region b(4 of source and drain)；The interchangeable area a(5 of heavy doping source and drain) and again
The interchangeable area b(6 of doped source and drain) it is built in the left and right sides of monocrystalline silicon thin film (1), the interchangeable intrinsic region a(3 of source and drain respectively) right
The interchangeable area a(5 of heavy doping source and drain) formed three bread wrap up in, the interchangeable intrinsic region b(4 of source and drain) the interchangeable area b of counterweight doped source and drain
(6) three bread are formed to wrap up in；
The interchangeable area a(5 of heavy doping source and drain) and the interchangeable area b(6 of heavy doping source and drain) bottom surface and SOI wafer substrate
The upper surface of insulating layer (11) contacts with each other；Grid electrode insulating layer (7) is insulating material, to monocrystalline silicon thin film (1) except with
Surface region other than the lower surface of substrate insulating layer (11) contact of SOI wafer forms package, by monocrystalline silicon thin film (1), source
Leak interchangeable intrinsic region a(3), the interchangeable intrinsic region b(4 of source and drain), the interchangeable area a(5 of heavy doping source and drain) and heavy doping source and drain can
Exchange area b(6) outer surface all around of cube that is constituted and cube in addition to the interchangeable area a(5 of heavy doping source and drain) and
The interchangeable area b(6 of heavy doping source and drain) upper surface other than upper surface be completely covered；The outer surface of grid electrode insulating layer (7)
Side wall and the partial region phase mutual connection for folding supplementary gate (2), double bracket shape gate electrode (8) and insulating medium barrier layer (13)
Touching；It folds supplementary gate (2) to be made of metal material or polycrystalline silicon material, falls frame above grid electrode insulating layer (7) in " recessed " shape,
It contacts with each other with the front and rear sides outer surface of grid electrode insulating layer (7) middle region part and upper surface；Double bracket shape grid electricity
Pole (8) is made of metal material or polycrystalline silicon material, is located at the left and right sides of grid electrode insulating layer (7), and and grid electrode insulating
Upper and lower surface and left and right outer surface at left and right sides of layer (7) contact with each other, and overlook viewing in a pair of of double bracket shape, double bracket
Bracket shape gate electrode part corresponding to shape gate electrode (8) every side is corresponding to the side grid electrode insulating layer (7) and inside
The interchangeable intrinsic region a(3 of source and drain) or the interchangeable intrinsic region b(4 of source and drain) formed three faces surround, pass through control double bracket shape gate electrode
(8) field-effect of potential added by controls the interchangeable intrinsic region a(3 of source and drain) and source and drain interchangeable intrinsic region b(4) internal current-carrying
Son distribution；Grid electrode insulating layer (7) forms insulation barrier, grid electricity between double bracket shape gate electrode (8) and monocrystalline silicon thin film (1)
Pole insulating layer (7) also forms insulation barrier between folding supplementary gate (2) and monocrystalline silicon thin film (1)；Double bracket shape gate electrode (8)
And it folds insulated from each other by insulating medium barrier layer (13) between supplementary gate (2)；Double bracket shape gate electrode (8) is only single to being located at
The interchangeable intrinsic region a(3 of source and drain of polycrystal silicon film (1) two sides) and the interchangeable intrinsic region b(4 of source and drain) there is obvious field-effect control to make
With, and to the middle section of monocrystalline silicon thin film (1) without obvious control action；Supplementary gate (2) are folded only in monocrystalline silicon thin film (1)
There is an obvious control action in centre region, and to the interchangeable intrinsic region a(3 of source and drain for being located at monocrystalline silicon thin film (1) two sides) and source and drain can
Exchange intrinsic region b(4) without obvious control action；The top of grid electrode insulating layer (7), which is removed, is folded the upper of supplementary gate (2) covering
Upper surface other than surface region is covered by insulating medium barrier layer (13)；The interchangeable electrode a(9 of source and drain) and source and drain it is interchangeable
Electrode b(10) it is that metal material is constituted, it is located at the interchangeable area a(5 of heavy doping source and drain) and the interchangeable area b of heavy doping source and drain
(6) top, and contact each other；The interchangeable electrode a(9 of source and drain) and the interchangeable electrode b(10 of source and drain) upper section and
The outer surface of section below contacts with each other with gate insulation dielectric barrier (13) and grid electrode insulating layer (7) respectively；It folds auxiliary
Help part at left and right sides of grid (2), can be in the interchangeable electrode a(9 of source and drain in symmetrical structure) and the interchangeable electrode b(10 of source and drain) right
Claim to realize same output characteristics in the case where exchanging.
2. the manufacturing method of the symmetrical interchangeable double bracket shape grid-control tunneling transistor of source and drain as described in claim 1, feature exist
In:
Its manufacturing step is as follows:
Step 1: providing a SOI wafer, and bottom is the silicon substrate (12) of SOI wafer, and the upper surface of silicon substrate is SOI wafer
Substrate insulating layer (11), the upper surface of the substrate insulating layer (11) of SOI wafer is monocrystalline silicon thin film (1), passes through photoetching, etching
Technique removes the partial region in the outside of monocrystalline silicon thin film (1) surrounding above SOI wafer；
Step 2: by ion implanting or diffusion technique, to the left and right sides of monocrystalline silicon thin film formed in step 1 (1)
Intermediate region symmetric position carry out high doped, be respectively formed the interchangeable area a(5 of heavy doping source and drain) and heavy doping source and drain it is interchangeable
Area b(6)；
Step 3: by oxidation or depositing technics, the upper surface of the monocrystalline silicon thin film (1) after being close to doping and outer surface, shape
At planarization process after insulating medium layer, grid electrode insulating layer (7) are preliminarily formed；
Step 4: by depositing technics, dielectric is deposited in the top of grid electrode insulating layer (7), is planarized to and exposes grid electricity
After pole insulating layer (7), then by etching technics etch away sections dielectric, preliminarily form SI semi-insulation dielectric barrier
(13)；
Step 5: by depositing technics, in wafer upper electrode metal or polysilicon, surface is planarized to exposing grid electrode insulating
Layer (7) forms metal or polysilicon layer in the front and rear sides intermediate region of grid electrode insulating layer (7) and two side areas, is formed double
Bracket shape gate electrode (8), and preliminarily form and fold supplementary gate (2)；
Step 6: dielectric is deposited above wafer, and middle section is etched away by etch areas, then pass through depositing technics
Metal or polysilicon are deposited, is connected with the folding supplementary gate (2) preliminarily formed in step 5, behind planarization surface further
It is formed and folds supplementary gate (2) and insulating medium barrier layer (13)；
Step 7: by depositing technics, depositing dielectric above wafer, passes through photoetching, etching work again after planarizing surface
Skill removes the interchangeable area a(5 of heavy doping source and drain) and the interchangeable area b(6 of heavy doping source and drain) above grid electrode insulating layer (7) and exhausted
Edge dielectric barrier (13) to expose the interchangeable area a(5 of heavy doping source and drain) and the interchangeable area b(6 of heavy doping source and drain) upper surface,
Through-hole is formed, then forms the interchangeable electrode a(9 of source and drain in through-holes by depositing metal) and the interchangeable electrode b(10 of source and drain), then
Insulating medium barrier layer (13) are further formed by planarization process.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711046023.6A CN107819036B (en) | 2017-10-31 | 2017-10-31 | Source and drain symmetrically interchangeable double bracket shape grid-control tunneling transistor and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711046023.6A CN107819036B (en) | 2017-10-31 | 2017-10-31 | Source and drain symmetrically interchangeable double bracket shape grid-control tunneling transistor and its manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107819036A CN107819036A (en) | 2018-03-20 |
| CN107819036B true CN107819036B (en) | 2019-11-22 |
Family
ID=61603505
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201711046023.6A Active CN107819036B (en) | 2017-10-31 | 2017-10-31 | Source and drain symmetrically interchangeable double bracket shape grid-control tunneling transistor and its manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107819036B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113471205B (en) * | 2021-06-30 | 2023-11-03 | 沈阳工业大学 | Nonvolatile resettable bi-directional switching device and method of manufacturing the same |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012120653A1 (en) * | 2011-03-08 | 2012-09-13 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | Production method for semiconductor device and semiconductor device |
| CN103280464B (en) * | 2013-05-23 | 2016-02-24 | 清华大学 | A kind of without the longitudinal tunneling field-effect transistor of junction type |
| CN104409487B (en) * | 2014-12-08 | 2017-09-29 | 沈阳工业大学 | The two-way breakdown protection double grid insulation tunnelling enhancing transistor of body silicon and its manufacture method |
| US9385195B1 (en) * | 2015-03-31 | 2016-07-05 | Stmicroelectronics, Inc. | Vertical gate-all-around TFET |
-
2017
- 2017-10-31 CN CN201711046023.6A patent/CN107819036B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN107819036A (en) | 2018-03-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102714161B (en) | A body-tied asymmetric P-type field effect transistor | |
| WO2016150335A1 (en) | Tunnelling field effect transistor and manufacturing method therefor | |
| CN110164958B (en) | Asymmetric reconfigurable field effect transistor | |
| KR20150016769A (en) | Tunneling Field Effect Transistor and Manufacturing Method thereof | |
| CN103594376A (en) | Junction-modulated type tunneling field effect transistor and manufacturing method thereof | |
| CN107819027B (en) | A kind of source and drain resistive formula H-shaped grid-control two-way switch transistor and its manufacturing method | |
| CN102714222B (en) | Body links asymmetric n type field effect transistor | |
| CN110518059B (en) | Longitudinal floating field plate device with charge balance voltage-resisting layer and manufacturing method thereof | |
| CN107785436B (en) | Source and drain resistive formula rectangular grid control U-shaped channel bidirectional transistor and its manufacturing method | |
| CN107819036B (en) | Source and drain symmetrically interchangeable double bracket shape grid-control tunneling transistor and its manufacturing method | |
| CN103700631A (en) | Preparation method for non-junction MOS FET (metal oxide semiconductor field effect transistor) device | |
| CN107808905B (en) | Bilateral folds the double tunnelling type bidirectionally conductive transistors of grid-control source and drain and its manufacturing method | |
| CN107799607B (en) | Conduction type is adjustable, and source and drain resistive formula bilateral folds gate transistor and its manufacturing method | |
| CN107706235B (en) | A kind of rectangular grid control U-shaped channel two-way switch tunneling transistor and its manufacturing method | |
| CN107833925B (en) | A kind of source and drain resistive formula two-way switch field effect transistor and its manufacturing method | |
| CN107731914B (en) | The grid of falling U auxiliary control bilateral grid master control bidirectional tunneling transistor and its manufacturing method | |
| CN107731913B (en) | The double tunneling transistors of discrete double square grid-control U-shaped channel source and drain and its manufacturing method | |
| CN107799606B (en) | The discrete double square grid-control source and drain resistive transistor of double conduction types and its manufacturing method | |
| CN107799589B (en) | H-shaped grid-control source and drain symmetrically interchangeable type tunneling transistor and its manufacturing method | |
| CN104282754B (en) | High integration L-shaped grid-control Schottky barrier tunneling transistor | |
| CN107819028B (en) | H-shaped grid-control source and drain resistive formula conduction type is adjustable transistor npn npn and its manufacturing method | |
| CN107785437B (en) | Bracket-shaped grid-control source-drain resistance-variable bidirectional switch transistor and manufacturing method thereof | |
| CN107768430B (en) | Source and drain symmetrically interchangeable bidirectional tunneling field effect transistor and its manufacturing method | |
| CN107808904B (en) | Double-bracket-shaped grid-control bidirectional switch tunneling transistor and manufacturing method thereof | |
| CN107681005B (en) | The interchangeable transistor of the optional source and drain of source and drain resistive formula conduction type and its manufacturing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20201224 Address after: 233000 No.10, building 32, Zone 8, Guangcai market, bengshan District, Bengbu City, Anhui Province Patentee after: Bengbu Hongjing Technology Co.,Ltd. Address before: 110870 No. 111 Shenyang West Road, Shenyang economic and Technological Development Zone, Liaoning Patentee before: SHENYANG University OF TECHNOLOGY |
|
| TR01 | Transfer of patent right |
Effective date of registration: 20210429 Address after: 423, floor 4, block a, Xinhua future city building, No. 175, Litang Road, Changping District, Beijing 102200 Patentee after: Li Qiannan Address before: 233000 No.10, building 32, Zone 8, Guangcai market, bengshan District, Bengbu City, Anhui Province Patentee before: Bengbu Hongjing Technology Co.,Ltd. |
|
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20211129 Address after: 350800 Baiyang Village Central Road, Baizhang Town, Minqing County, Fuzhou, Fujian, China Patentee after: FUZHOU ZHONGDIAN NETWORK TECHNOLOGY DEVELOPMENT CO.,LTD. Address before: 102200 423, 4 / F, block a, Xinhua future city building, 175 Litang Road, Changping District, Beijing Patentee before: Li Qiannan |
|
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20220114 Address after: 102200 423, 4 / F, block a, Xinhua future city building, 175 Litang Road, Changping District, Beijing Patentee after: Li Gang Address before: 350800 Baiyang Village Central Road, Baizhang Town, Minqing County, Fuzhou, Fujian, China Patentee before: FUZHOU ZHONGDIAN NETWORK TECHNOLOGY DEVELOPMENT CO.,LTD. |
|
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20220411 Address after: 150000 No. 50, Daqing sub Road, Xiangfang District, Harbin, Heilongjiang Patentee after: Tongpu Information Technology Co.,Ltd. Address before: 102200 423, 4 / F, block a, Xinhua future city building, 175 Litang Road, Changping District, Beijing Patentee before: Li Gang |
|
| PE01 | Entry into force of the registration of the contract for pledge of patent right | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of invention: Source-drain symmetrical interchangeable double-bracket gate controlled tunneling transistor and its manufacturing method Effective date of registration: 20230112 Granted publication date: 20191122 Pledgee: Heilongjiang Xinzheng financing guarantee Group Co.,Ltd. Pledgor: Tongpu Information Technology Co.,Ltd. Registration number: Y2023230000014 |