CN107564985A

CN107564985A - Cell piece component, cell piece matrix and solar cell module

Info

Publication number: CN107564985A
Application number: CN201610510202.XA
Authority: CN
Inventors: 孙翔; 姚云江; 田野; 范北; 姜占锋
Original assignee: BYD Co Ltd
Current assignee: BYD Co Ltd
Priority date: 2016-06-30
Filing date: 2016-06-30
Publication date: 2018-01-09
Also published as: CN118398691A

Abstract

The invention discloses a kind of cell piece component, cell piece matrix and solar cell module, cell piece component includes：The multiple cell pieces and conductive strips arranged successively along longitudinal direction, each cell piece includes silicon chip, the front side conductive part being located on silicon chip smooth surface, two electrodes being located on silicon chip shady face and the lateral conduction part for being located on silicon chip side surface and being connected electrically in front side conductive part between an electrode, wherein, two electrodes extend transversely and are longitudinally spaced from distribution, conductive strips it is identical with the bearing of trend of electrode and with it is close to each other and two electrodes on the two neighboring cell piece electrically connect two cell piece serial or parallel connections so that adjacent respectively.According to the cell piece component of the present invention, the use length of conductive strips can be effectively reduced, the usage amount of conductive strips is reduced, reduces the fuel factor that conductive strips trigger, improve the overall power of cell piece component.

Description

Cell piece component, cell piece matrix and solar cell module

Technical field

The present invention relates to technical field of solar batteries, more particularly, to a kind of cell piece component, cell piece matrix and solar cell module.

Background technology

Crystal silicon solar cell sheet in correlation technique, smooth surface and shady face have both positive and negative polarity of the 2-3 root silver main gate lines as cell piece respectively, and these silver-colored main gate lines not only consume substantial amounts of silver paste, and decline because blocking incident light so as to cause the efficiency of cell piece.In addition, because both positive and negative polarity is respectively distributed on the smooth surface and shady face of cell piece, when cell piece is connected, need to be welded to the negative electrode of cell piece smooth surface on the positive electrode of adjacent cell piece shady face using conductive strips, so as to cause welding procedure cumbersome, welding material uses the problem of more, moreover, easily causing the breakage of cell piece and conductive strips during welding and in follow-up laminating technology.

In addition, cell piece matrix in correlation technique is typically to be sequentially connected in series by 72 or 60 cell pieces, form three loops of six string battery strings compositions, now, typically at least need three diodes, so that setting up a diode on each loop carries out bypass protection, because diode is generally disposed in the terminal box of battery, so as to add the cost of integrated junction box, the structural complexity of battery is caused to improve, and, when the series component being in series by multiple cell pieces is connected again, connecting cable dosage is very big, waste of material is a lot, power station cost is caused to increase.

The content of the invention

It is contemplated that at least solves one of technical problem present in prior art.Therefore, the invention reside in propose a kind of cell piece component, the power height of the cell piece component.

The present invention also proposes a kind of cell piece matrix with above-mentioned cell piece component.

The present invention also proposes a kind of solar cell module with above-mentioned cell piece matrix.

Cell piece component according to a first aspect of the present invention, including：The multiple cell pieces arranged successively along longitudinal direction, each cell piece includes silicon chip, the front side conductive part being located on the silicon chip smooth surface, two electrodes being located on the silicon chip shady face and the lateral conduction part for being located on the silicon chip side surface and being connected electrically between the front side conductive part and an electrode, wherein, two electrodes extend transversely and distribution are spaced apart on the longitudinal direction；Conductive strips, the conductive strips it is identical with the bearing of trend of the electrode and with it is close to each other and two electrodes on the two neighboring cell piece electrically connect two cell piece serial or parallel connections so that adjacent respectively.

According to the cell piece component of the present invention, the use length of conductive strips can be effectively reduced, the usage amount of conductive strips is reduced, reduces the fuel factor that conductive strips trigger, improve the overall power of cell piece component.

In certain embodiments, on the bearing of trend of the conductive strips, the development length of the conductive strips is more than or equal to the development length of each electrode turned on by the conductive strips, and the both ends of the conductive strips exceed or flushed in respectively the respective end of each electrode turned on by the conductive strips.

In certain embodiments, on the direction of the conductive strips bearing of trend, the span of the conductive strips is more than or equal to the span sum of two electrodes turned on by the conductive strips, and two sides of the conductive strips exceed or flushed in respectively two sides of two electrodes turned on by the conductive strips away from each other.

In certain embodiments, the conductive strips are identical including structure and are covered each by two electrodes turned on by the conductive strips just in the two half-unit being sequentially arranged on the conductive strips bearing of trend, each half portion.

In certain embodiments, on the direction of the conductive strips bearing of trend, the gap between every two adjacent cell pieces is less than or equal to 0.1mm.

In certain embodiments, the silicon chip is 20mm-60mm in the span where the lateral conduction part in side face directions.

In certain embodiments, the silicon chip is rectangle lamellar body and is split to form by square conventional silicon wafers body according to the constant rule of length.

In certain embodiments, the silicon chip is rectangle lamellar body, and recline respectively two long sides of the silicon chip of two electrodes are set and extended along the length direction of the silicon chip, and the lateral conduction part is located on a long side side surface of the silicon chip.

In certain embodiments, the first electrode and the non-second electrode electrically connected with the lateral conduction part, the silicon chip that two electrodes on each cell piece respectively electrically connect with the lateral conduction part include：Silicon chip, positive first kind diffusion layer and back side interlayer, wherein, the shady face of the silicon chip includes first area and second area, the positive first kind diffusion layer is located on the smooth surface of the silicon chip, the front side conductive part is located on the positive first kind diffusion layer, the back side interlayer is only defined and is covered with the first area, the first electrode is located on the back side interlayer, the second electrode is located on the second area and not contacted with the first electrode, wherein, the at least partially insulating barrier of the back side interlayer spreads channel type identical diffusion layer with the positive first kind.

In certain embodiments, the silicon chip also includes：Side interlayer, the side interlayer are located on the side surface of the silicon chip, and the lateral conduction part is located on the side interlayer, at least partially insulating barrier of the side interlayer or with the positive first kind diffusion channel type identical diffusion layer.

In certain embodiments, each cell piece also includes：Electric layer is carried on the back, the back of the body electric layer is located on the second area, and the second electrode is located in the back of the body electric layer and electrically connected with the back of the body electric layer.

In certain embodiments, each cell piece also includes：The grid line layer of the back side second, the grid line layer of the back side second and the second electrode are each provided on the second area, and the second electrode is electrically connected with the grid line layer of the back side second and is not stacked mutually.

In certain embodiments, the silicon chip also includes and positive different types of the second class of the back side diffusion layer of first kind diffusion layer, the second class of back side diffusion layer is only defined and is covered with the second area, and the grid line layer of the back side second and the second electrode are each provided on the second class of back side diffusion layer.

In certain embodiments, each cell piece also includes：The grid line layer of the back side first, the grid line layer of the back side first and the first electrode are each provided on the back side interlayer, and the first electrode is electrically connected with the grid line layer of the back side first and is not stacked mutually.

In certain embodiments, the back side interlayer is to spread channel type identical back side first kind diffusion layer with the positive first kind, the back side first kind diffusion layer is only defined and is covered with the first area, and the grid line layer of the back side first and the first electrode are each provided on the back side first kind diffusion layer.

In certain embodiments, the first area and the second area are non-discrete region.

In certain embodiments, the first area is distributed with the second area in X-shape is referred to, wherein, the first area includes the first connected region and multiple first discrete areas, multiple first discrete areas are spaced apart on the length direction of first connected region and connected with first connected region, the second area includes the second connected region and multiple second discrete areas, multiple second discrete areas are spaced apart on the length direction of second connected region and connected with second connected region, wherein, first connected region be arranged in parallel with second connected region, multiple first discrete areas and multiple second discrete areas replace one by one between first connected region and second connected region.

Cell piece matrix according to a second aspect of the present invention, it is in series by multiple cell piece parallel components, wherein, each cell piece parallel component is formed in parallel by multiple cell piece series components, wherein, each cell piece series component is cell piece component according to a first aspect of the present invention, and each multiple cell pieces in the cell piece component are sequentially connected in series by the conductive strips.

According to the cell piece matrix of the present invention, by setting the cell piece component of above-mentioned first aspect, so as to improve the overall power of cell piece matrix.

In certain embodiments, the cell piece parallel component is two, and each cell piece parallel component includes three cell piece series components.

Solar cell module according to a third aspect of the present invention, including first panel, the first tack coat, battery, the second tack coat and the second panel set gradually from sensitive side to backlight side, wherein, the battery is the cell piece component according to first aspect present invention or cell piece matrix according to a second aspect of the present invention.

According to the solar cell module of the present invention, by setting the cell piece matrix of above-mentioned second aspect or the cell piece component of above-mentioned first aspect, so as to improve the overall performance of solar cell module.

The additional aspect and advantage of the present invention will be set forth in part in the description, and partly will become apparent from the description below, or be recognized by the practice of the present invention.

Brief description of the drawings

Fig. 1 is the schematic diagram of cell piece component according to embodiments of the present invention；

Fig. 2 is the schematic diagram that conductive strips are removed in Fig. 1；

Fig. 3 is the schematic diagram of cell piece matrix according to embodiments of the present invention；

Fig. 4 is the circuit diagram of the cell piece matrix shown in Fig. 3.

Fig. 5 is according to embodiments of the present invention 1 cell piece light measuring intention；

Fig. 6 is the schematic diagram of the backlight side of the cell piece shown in Fig. 5；

Fig. 7 is the schematic diagram of a side of the cell piece shown in Fig. 5；

Fig. 8 is that two cell pieces shown in Fig. 6 use the schematic diagram that conductive strips are connected；

Fig. 9 is the schematic diagram that conductive strips are removed in Fig. 8；

Figure 10 is according to embodiments of the present invention 2 cell piece light measuring intention；

Figure 11 is the schematic diagram of the backlight side of the cell piece shown in Figure 10；

Figure 12 is the schematic diagram of a side of the cell piece shown in Figure 10；

Figure 13 is that two cell pieces shown in Figure 11 use the schematic diagram that conductive strips are connected；

Figure 14 is the schematic diagram that conductive strips are removed in Figure 13；

Figure 15 is according to embodiments of the present invention 3 cell piece light measuring intention；

Figure 16 is the schematic diagram of the backlight side of the cell piece shown in Figure 15；

Figure 17 is the schematic diagram of a side of the cell piece shown in Figure 15；

Figure 18 is that two cell pieces shown in Figure 16 use the schematic diagram that conductive strips are connected；

Figure 19 is the schematic diagram that conductive strips are removed in Figure 18；

Figure 20 is according to embodiments of the present invention 4 cell piece light measuring intention；

Figure 21 is the schematic diagram of the backlight side of the cell piece shown in Figure 20；

Figure 22 is the schematic diagram of a side of the cell piece shown in Figure 20；

Figure 23 is that two cell pieces shown in Figure 21 use the schematic diagram that conductive strips are connected；

Figure 24 is the schematic diagram that conductive strips are removed in Figure 23；

Figure 25 is according to embodiments of the present invention 5 cell piece light measuring intention；

Figure 26 is the schematic diagram of the backlight side of the cell piece shown in Figure 25；

Figure 27 is the schematic diagram of a side of the cell piece shown in Figure 25；

Figure 28 is the schematic diagram of another side of the cell piece shown in Figure 25；

Figure 29 is the preparation process figure of the backlight side of the cell piece shown in Figure 26；

Figure 30 is that two cell pieces shown in Figure 26 use the schematic diagram that conductive strips are connected；

Figure 31 is the schematic diagram that conductive strips are removed in Figure 30；

Figure 32 is according to embodiments of the present invention 6 cell piece light measuring intention；

Figure 33 is the schematic diagram of the backlight side of the cell piece shown in Figure 32；

Figure 34 is the schematic diagram of a side of the cell piece shown in Figure 32；

Figure 35 is the schematic diagram of another side of the cell piece shown in Figure 32；

Figure 36 is the preparation process figure of the backlight side of the cell piece shown in Figure 33；

Figure 37 is that two cell pieces shown in Figure 33 use the schematic diagram that conductive strips are connected；

Figure 38 is the schematic diagram that conductive strips are removed in Figure 37；

Figure 39 is according to embodiments of the present invention 7 cell piece light measuring intention；

Figure 40 is the schematic diagram of the backlight side of the cell piece shown in Figure 39；

Figure 41 is the schematic diagram of a side of the cell piece shown in Figure 39；

Figure 42 is the schematic diagram of another side of the cell piece shown in Figure 39；

Figure 43 is the preparation process figure of the backlight side of the cell piece shown in Figure 40；

Figure 44 is that two cell pieces shown in Figure 40 use the schematic diagram that conductive strips are connected；

Figure 45 is the schematic diagram that conductive strips are removed in Figure 44.

Reference：

Cell piece series component 1000；Cell piece parallel component 2000；Cell piece matrix 10000；

Conductive strips 1001；Busbar 1002；Cell piece component 100A；

Cell piece 100；Cell piece A；Cell piece B；Electrode A 1；Electrode A 2；Electrode B 1；Electrode B 2；

Silicon chip 1；Silicon chip 11；Anti-reflection layer 101；Passivation layer 102；

Positive first kind diffusion layer 12；Side interlayer 13；Back side interlayer 14；The back side the second class diffusion layer 15；

Front gate line layer 2；Positive face grid line 21；

Lateral conduction part 3；First electrode 4；Second electrode 5；

The second grid line layer of the back side 6；The sub- grid line 61 in the back side second；Carry on the back electric layer 60；

The first grid line layer of the back side 7；The sub- grid line 71 in the back side first.

Embodiment

Embodiments of the invention are described below in detail, the example of the embodiment is shown in the drawings, wherein same or similar label represents same or similar element or the element with same or like function from beginning to end.The embodiments described below with reference to the accompanying drawings are exemplary, it is intended to for explaining the present invention, and is not considered as limiting the invention.

Following disclosure provides many different embodiments or example is used for realizing the different structure of the present invention.In order to simplify disclosure of the invention, hereinafter the part and setting of specific examples are described.Certainly, they are only example, and purpose does not lie in the limitation present invention.In addition, the present invention can in different examples repeat reference numerals and/or letter.This repetition is the relation between itself not indicating discussed various embodiments and/or setting for purposes of simplicity and clarity.In addition, the invention provides various specific techniques and material examples, but those of ordinary skill in the art can be appreciated that the applicable property of other techniques and/or the use of other materials.

Below with reference to the accompanying drawings 1- Figure 45 describes the cell piece component 100A of embodiment according to a first aspect of the present invention.

The cell piece component 100A of embodiment according to a first aspect of the present invention, including：At least two cell pieces 100 and at least one conductive strips 1001.Wherein, cell piece 100 is back contact solar battery piece.

Specifically, each cell piece 100 includes silicon chip 1, the front side conductive part (such as front gate line layer 2 described below) being located on the smooth surface of silicon chip 1, two electrodes (such as first electrode 4 described below and second electrode 5) being located on the shady face of silicon chip 1 and the lateral conduction part 3 for being located on the side surface of silicon chip 1 and being connected electrically in front side conductive part between an electrode, wherein, two electrodes are opposite polarity and non-touching positive electrode and negative electrode.So, when the smooth surface of silicon chip 1 is by light irradiation, front side conductive part can collect the electric charge of a species from the smooth surface of silicon chip 1 and pass to be connected electrically electrode by lateral conduction part 3, another electrode obtains the electric charge of another species in the backlight surface side of silicon chip 1, and thus two electrodes can export electric energy.

Specifically, multiple cell pieces 100 according to smooth surface towards the same side, for example both face towards the sun, and mode of the shady face towards the same side, for example backwards to the sun is arranged in order along longitudinal direction, wherein, two electrodes on each cell piece 100 extend transversely and are longitudinally spaced from distribution, short circuit is avoided to ensure that two electrodes are not in contact with each other, here, it should be noted that, " bearing of trend of electrode " specifically described herein refers to the length direction of electrode, and " bearing of trends of conductive strips 1001 " described below refer to the length direction of conductive strips 1001.Here, it should be noted that, " transverse direction " specifically described herein refers to the horizontal direction shown in the bearing of trend, such as Fig. 1 and Fig. 2 of x wire, " longitudinal direction " refers to the vertical direction shown in the bearing of trend, such as Fig. 1 and Fig. 2 of vertical line, and x wire and vertical line are orthogonal straight line；In addition, " extending transversely " should include " extending along the direction parallel with x wire " and " extending along the direction with x wire into angle less than 45 ° " as broad understanding.

Specifically, conductive strips 1001 are identical with the bearing of trend of electrode fully to be electrically connected with electrode, improve electrical efficiency, wherein, conductive strips 1001 with it is close to each other and respectively be located at two neighboring cell piece 100 on two electrodes electrically connect two serial or parallel connections of cell piece 100 so that adjacent.Here,For clear expression,Illustrate,Referring to Figures 1 and 2,Assuming that two adjacent cell pieces 100 are respectively cell piece A and cell piece B,There is the electrode A 1 and electrode A 2 being spaced along the longitudinal on cell piece A,There is the electrode B 1 and electrode B 2 being spaced along the longitudinal on cell piece B,When cell piece A and cell piece B is arranged in order along longitudinal direction,Electrode A 1,Electrode A 2,Electrode B 1 and electrode B 2 are arranged in order along longitudinal direction,Now,Electrode A 2 and electrode B 1 are close to each other,Electrode A 1 and electrode B 2 are away from each other,Now,Conductive strips 1001 electrically connect with electrode A 2 and electrode B 1 so that electrode A 2 and electrode B 1 to be turned on respectively,Now,When electrode A 2 (be positive electrode or be negative electrode) identical with the polarity of electrode B 1,Cell piece A and cell piece B can be in parallel,And when electrode A 2 is different with the polarity of electrode B 1, (i.e. one is positive electrode,Another is negative electrode) when,Cell piece A and cell piece B can connect.

Below, only using the vertical direction shown in Fig. 1 and Fig. 2 as " longitudinal direction ", the horizontal direction shown in Fig. 1 and Fig. 2 is to illustrate exemplified by " transverse direction ", certainly, those skilled in the art are after following technical scheme has been read, it is clear that it is appreciated that other directions are the technical scheme of " longitudinal direction ".In addition, it should be noted that, orientation or position relationship shown in illustrations, it is for only for ease of the description present invention and simplifies description, rather than the device or element of instruction or hint meaning there must be specific orientation, with specific azimuth configuration and operation, therefore it is not considered as limiting the invention.

As depicted in figs. 1 and 2,Multiple cell pieces 100 are arranged in order in the vertical direction,Wherein,Two electrodes on each cell piece 100 extend in left-right direction,And distribution is spaced apart in the vertical direction,Respectively there is an electrode so as to the upper and lower part of each cell piece 100,Thus,The upper electrode (such as electrode B 1) of remaining cell piece 100 (such as cell piece B) in addition to the cell piece 100 (such as cell piece A) of the top is close to each other with the lower electrode (such as electrode A 2) of the cell piece 100 (such as cell piece A) above it and can be turned on by conductive strips 1001,That is,The lower electrode (such as electrode A 2) of remaining cell piece 100 (such as cell piece A) in addition to the cell piece 100 (such as cell piece B) of bottom is close to each other with the upper electrode (such as electrode B 1) of cell piece 100 (such as cell piece B) below and can be turned on by conductive strips 1001.

Thus, it cell piece component 100A according to embodiments of the present invention, can effectively reduce the gross area of conductive strips 1001, reduce the fuel factor that conductive strips 1001 trigger, reduce the usage amount of conductive strips 1001, improve cell piece component 100A overall power.Wherein, conductive strips 1001 can be welding.

Below, refer to the attached drawing 3 and Fig. 4 describe the cell piece matrix 10000 of embodiment according to a second aspect of the present invention.

Specifically, when multiple cell pieces 100 in cell piece component 100A are sequentially connected in series by conductive strips 1001, cell piece component 100A is cell piece series component 1000.Cell piece matrix 10000 is made up of the multiple cell piece parallel components 2000 connected, wherein each cell piece parallel component 2000 is formed in parallel by multiple cell piece series components 1000.Multiple cell piece parallel components 2000 that is, multiple cell piece series components 1000 are formed in parallel first, multiple cell piece parallel components 2000 are in series cell piece matrix 10000 again.Thus; effectively increase the power of cell piece matrix 10000; and diode need not be added and carry out bypass protection; reduce the cost of battery; in addition; positive and negative terminal box can be distributed in the both sides of cell piece matrix 10000, so as to reduce the dosage of connecting cable between adjacent component, reduce power station cost.

Such as in a preferred embodiment of the invention, cell piece parallel component 2000 is two, and each cell piece parallel component 2000 is formed in parallel by three cell piece series components 1000.That is, six cell piece series components 1000 are formed into cell piece matrix 10000 by the way of " first three and again two going here and there ", first by six cell piece series components 1,000 33 and two cell piece parallel components 2000 are unified into, two cell piece parallel components 2000 are then connected into cell piece matrix 10000.

Here, it is necessary to illustrate, the cell piece matrix in correlation technique generally includes 60 cell pieces being sequentially connected in series, wherein, every 10 cell pieces are first connected into a cell piece string, and 6 cell piece strings are sequentially connected in series again, so as to which 60 cell pieces can be all sequentially connected in series.When the voltage of each cell piece is 0.5V, the voltage for 60 cell pieces being cascaded is exactly 30V, now, if a cell piece string is out of joint, then whole cell piece matrix just can not normal work, so just needing three diodes in parallel, accordingly even when there is a cell piece string out of joint, so circuit still can by parallel connection diode formed loop, cell piece matrix still can continue normal work, be unlikely to scrap, simply power is smaller.But, the production cost of one side diode is higher, and on the other hand because diode need to be arranged in terminal box, terminal box is arranged at the edge that width is leaned among cell panel, both positive and negative polarity is drawn by terminal box, and the integrated junction box used in component also improves production cost.Further, since terminal box is in component center, when component is connected with component, connecting cable dosage is big, waste of materials, also increases power station cost.

Mutually than, this paper cell piece 100, can be using the 1/4 of conventional batteries piece, now, the total voltage for the cell piece series component 1000 being connected into by 10 cell pieces 100 is exactly 20V (i.e. 40 × 0.5V=20V), so, two such cell piece series components 1000 can that is together in series is reached into 40V voltage, voltage is used so as to effectively achieve.In addition; when forming cell piece matrix 10000 by the way of " first three and again two going here and there " described above; because parallel-connection structure can inherently be protected to the bypass of parallel connection, bypass protection is carried out so as to avoid the need for adding diode in addition, reduces production cost.Further, since positive and negative terminal box can be distributed in the both sides of cell piece matrix 10000, so as to reduce the dosage of component and component connecting cable, power station cost reduce further.

The solar cell module of embodiment according to a third aspect of the present invention is described below.

Specifically, solar cell module includes：First panel, the first tack coat, battery, the second tack coat and the second panel set gradually from sensitive side to backlight side.Wherein, battery can be the cell piece component 100A of above-mentioned first aspect embodiment, or the cell piece matrix 10000 of above-mentioned second aspect embodiment.Thus, the power of solar cell module is more preferable, efficiency is more preferable, processing is easier, cost is lower.

The preparation method of the solar cell module of embodiment according to a fourth aspect of the present invention is described below.

First, battery is prepared.

Specifically, when battery is cell piece component 100A, conductive strips 1001 can be used, to obtain cell piece component 100A, then again will to be picked out cell piece component 100A positive electrode and negative electrode respectively using busbar 1002 per two adjacent serial or parallel connections of cell piece 100 first.

Specifically, when battery is cell piece matrix 10000, conductive strips 1001 can be used to be connected per two adjacent cell pieces 100 to obtain multiple cell piece series components 1000 first, then busbar 1002 is used by multiple parallel connections of cell piece series components 1000 to obtain multiple cell piece parallel components 2000, then use busbar 1002 that multiple cell piece parallel components 2000 are connected to obtain cell piece matrix 10000, finally picked out the positive electrode of cell piece matrix 10000 and negative electrode respectively using busbar 1002.

Then, first panel, the first tack coat, battery, the second tack coat and second panel are sequentially laid in the vertical direction to obtain laminar structure, and then laminar structure is laminated and encapsulated.Such as, can be first according to order from top to bottom, first panel (such as glass), the first tack coat (such as EVA), battery, the second tack coat (such as EVA) and second panel (such as battery back-sheet or glass) are laid successively to obtain laminar structure, then, laminar structure in previous step is put into laminating machine laminating, terminal box and frame are installed, so as to realize the encapsulation of solar cell module and making.

1 and Fig. 2 and combination Fig. 5-Figure 45 describe the cell piece 100 according to the multiple embodiments of the present invention below with reference to the accompanying drawings.

In one embodiment of the invention, on the bearing of trend of conductive strips 1001, the development length of conductive strips 1001 is more than or equal to the development length of each electrode turned on by conductive strips 1001, and the both ends of conductive strips 1001 exceed or flushed in respectively the respective end of each electrode turned on by conductive strips 1001.It is to be noted that, when the both ends of conductive strips 1001 exceed the respective end of each electrode turned on by conductive strips 1001 respectively, conductive strips 1001 need with each silicon chip 1 with the electrode that is turned on by the conductive strips 1001 entrained by the conducting medium of opposite charge keep certain safe distance, to avoid two electric pole short circuits on same silicon chip 1.

Such as in the example shown in Fig. 1 and Fig. 2,Electrode A 2 and electrode B 1 are horizontally extending,Conductive strips 1001 are also horizontally extending,The length of conductive strips 1001 in the horizontal direction is more than or equal to the length of electrode A 2 in the horizontal direction,Simultaneously also greater than the length equal to electrode B 1 in the horizontal direction,The both ends in the horizontal direction of conductive strips 1001 are respectively left and right ends,The left end of conductive strips 1001 exceeds or flushed in the left the left end of electrode A 2,Simultaneously,The left end of conductive strips 1001 also exceeds or flushed in the left the left end of electrode B 1,The right-hand member of conductive strips 1001 exceeds or flushed in the right the right-hand member of electrode A 2,Simultaneously,The right-hand member of conductive strips 1001 also exceeds or flushed in the right the right-hand member of electrode B 1,Simultaneously conductive strips 1001 left and right ends also will respectively with electrode A 1,The conducting medium electrically connected with electrode A 1,Electrode B 2,And the conducting medium electrically connected with electrode B 2 keeps certain safe distance,To avoid electrode A 1 and the short circuit connection of electrode A 2,Electrode B 1 and the short circuit connection of electrode B 2 are avoided simultaneously.Thus, it is possible to ensure that conductive strips 1001 are fully connected with electrode, reduce the gross area of conductive strips 1001, reduce the fuel factor that conductive strips 1001 trigger, reduce the usage amount of conductive strips 1001, improve cell piece component 100A overall power.

In one embodiment of the invention, on the direction of the bearing of trend of conductive strips 1001, the span of conductive strips 1001 is more than or equal to the span sum of two electrodes turned on by conductive strips 1001, and two sides of conductive strips 1001 exceed or flushed in respectively two sides of two electrodes turned on by conductive strips 1001 away from each other.It is to be noted that, when two sides of conductive strips 1001 exceed two side of two electrodes being turned on by conductive strips 1001 away from each other respectively, conductive strips 1001 need with each silicon chip 1 with the electrode that is turned on by the conductive strips 1001 entrained by the conducting medium of opposite charge keep certain safe distance, to avoid two electric pole short circuits on same silicon chip 1.

Such as in the example shown in Fig. 1 and Fig. 2,Electrode A 2 and electrode B 1 are horizontally extending,Conductive strips 1001 are also horizontally extending,The width of the in the vertical direction of conductive strips 1001 is more than or equal to the width of the in the vertical direction of electrode A 2 and the width sum of the in the vertical direction of electrode B 1,Two sides of the in the vertical direction of conductive strips 1001 are respectively upper and lower side,The upper side edge of conductive strips 1001 exceeds or flushed in upwards the upper side edge of electrode A 2,The lower side of conductive strips 1001 exceeds or flushed in downwards the lower side of electrode B 1,Simultaneously conductive strips 1001 side up and down also will respectively with electrode A 1,The conducting medium electrically connected with electrode A 1,Electrode B 2,And the conducting medium electrically connected with electrode B 2 keeps certain safe distance,To avoid electrode A 1 and the short circuit connection of electrode A 2,Electrode B 1 and the short circuit connection of electrode B 2 are avoided simultaneously.Thus, it is possible to ensure that conductive strips 1001 are fully connected with electrode, reduce the gross area of conductive strips 1001, reduce the fuel factor that conductive strips 1001 trigger, reduce the usage amount of conductive strips 1001, improve cell piece component 100A overall power.

In an alternate embodiment of the present invention where, conductive strips 1001 are identical including structure and in the two half-unit being sequentially arranged on the bearing of trend of conductive strips 1001, and each half portion is covered each by two electrodes turned on by conductive strips 1001 just.Such as in the example shown in Fig. 1 and Fig. 2, conductive strips 1001 are horizontally extending and the first half being sequentially arranged including in the vertical direction and lower half, wherein, the first half covers electrode A 2 just, that is, the outer contour of the first half overlaps with the outer contour of electrode A 2, lower half covers electrode B 1 just, that is, the outer contour of lower half overlaps with the outer contour of electrode B 1.Thus, it is possible to ensure that conductive strips 1001 are fully connected with electrode, reduce the gross area of conductive strips 1001, reduce the fuel factor that conductive strips 1001 trigger, reduce the usage amount of conductive strips 1001, improve cell piece component 100A overall power.

Preferably, on the direction of the bearing of trend of conductive strips 1001, the gap between every two adjacent cell pieces 100 is less than or equal to 0.1mm.That is, the gap between per two adjacent cell pieces 100 is 0mm~0.1mm.Such as in the example shown in Fig. 1 and Fig. 2, conductive strips 1001 are horizontally extending, cell piece A and cell piece B in the vertical directions are sequentially arranged, now, the gap of the distance between cell piece A lower edge and cell piece B top edge between cell piece A and cell piece B.Thus, when being limited to less than being equal to 0.1mm in the gap on the bearing of trend of conductive strips 1001 by two neighboring cell piece 100, the gross area of conductive strips 1001 can further be reduced, reduce the fuel factor that conductive strips 1001 trigger, reduce the usage amount of conductive strips 1001, improve cell piece component 100A overall power, in addition, when having certain small gap between two cell pieces 100, the adjacent cell piece 100 caused by the in irregular shape or operating error of cell piece 100 can be avoided to be stacked problem.

In some embodiments of the invention, silicon chip 1 is 20mm-60mm in the span in the place side face directions of lateral conduction part 3.That is, silicon chip 1 includes one group (two) side surface for being oppositely arranged, one of side surface is provided with lateral conduction part 3, and the distance between this group of side surface is 20mm~60mm.Such as in the example shown in Fig. 1 and Fig. 2, when silicon chip 1 is that rectangle lamellar body, such as rectangle lamellar body and lateral conduction part 3 are located on a long side side surface of silicon chip 1, the width of silicon chip 1 is 20mm~60mm.Such as in another example of the present invention (the not shown example), when silicon chip 1 is rectangle lamellar body and lateral conduction part 3 is located on a broadside side surface of silicon chip 1, the length of silicon chip 1 is 20mm~60mm.

Thus, it is possible to shorten the path that electric charge transmits from the smooth surface of silicon chip 1 to shady face, so as to improve the transfer rate of electric charge, and then the power of cell piece 100 is improved.Here, it is necessary to which explanation, " rectangle lamellar body " is not limited to proper rectangle lamellar body, such as general rectangular lamellar body, the rectangle lamellar body that such as four vertex have fillet or chamfering are also fallen within protection scope of the present invention as broad understanding.Thus, facilitate the processing of cell piece 100, and facilitate the connection between battery and cell piece 100.

Preferably, silicon chip 1 is rectangle lamellar body, and is formed by square conventional silicon wafers body according to the constant rule segmentation (only refer to " separating " rather than refer in particular to " taking cutting technique ") of length.That is, the silicon chip 1 of multiple rectangle demihull shapes can be divided into according to the constant mode of length by square specification silicon chip body, now, the length of each silicon chip 1 with the equal length of square specification silicon chip body and the width sum of multiple silicon chips 1 it is equal with the width of square specification silicon chip body.

Silicon chip 1 is rectangle lamellar body, two electrodes recline respectively silicon chip 1 two long sides set, with the width of silicon chip 1 be spaced apart, and extend along the length direction of silicon chip 1, lateral conduction part 3 is located on a long side side surface of silicon chip 1, on the side side surface that is located on the width of silicon chip 1.Thus, the transmission path of electric charge is shorter, and the power of cell piece 100 is higher, and the processing of cell piece 100 is easier, easily facilitates the connection between cell piece 100 and cell piece 100.

Preferably, two electrodes can be rectangular sheet body and length and the equal length of silicon chip 1, so as to which two broadsides of two electrodes and a long side can align with two broadsides of silicon chip 1 and a long side respectively, and then can fully utilization space, the power of cell piece 100 is improved, and facilitates the connection of further battery piece 100 and cell piece 100.In addition, lateral conduction part 3 can also be configured to demihull shape and take on the side side surface on the width of silicon chip 1, so as to improve the power of cell piece 100.Certainly, the concrete structure not limited to this of lateral conduction part 3 and electrode, for example, lateral conduction part 3 and electrode can also be made up of the electrode of discrete type the multiple sub-electrodes for being spaced apart distribution respectively.

With reference to Examples below 1- embodiments 7, first electrode 4 and the non-second electrode 5 electrically connected with lateral conduction part 3, silicon chip 1 that two electrodes on each cell piece 100 respectively electrically connect with lateral conduction part 3 include：Silicon chip 11, positive first kind diffusion layer 12 and back side interlayer 14, wherein, the shady face of silicon chip 11 includes first area and second area, positive first kind diffusion layer 12 is located on the smooth surface of silicon chip 11, front side conductive part is located on positive first kind diffusion layer 12, back side interlayer 14 is only defined and is covered with the first region, first electrode 4 is located on back side interlayer 14, second electrode 5 sets on the second region and not contacted with first electrode 4, wherein, at least partially insulating barrier of back side interlayer 14 or with the positive type identical diffusion layer of first kind diffusion layer 12.Thus, the structure of cell piece 100 is simple, is easy to process and realizes.

With reference to Examples below 1- embodiments 7, silicon chip 1 also includes：Side interlayer 13, side interlayer 13 are located on the side surface of silicon chip 11, and lateral conduction part 3 is located on side interlayer 13, at least partially insulating barrier of side interlayer 13 or with the positive type identical diffusion layer of first kind diffusion layer 12.With reference to Examples below 1, each institute's cell piece 100 also includes：Electric layer 60 is carried on the back, back of the body electric layer 60 is set on the second region, and second electrode 5 is located in back of the body electric layer 60 and electrically connected with back of the body electric layer 60.

With reference to Examples below 2- embodiments 7, each institute's cell piece 100 also includes：The second grid line layer of the back side 6, the second grid line layer of the back side 6 and second electrode 5 are all provided with the second region, and second electrode 5 is electrically connected with the second grid line layer of the back side 6 and is not stacked mutually.Further, with reference to Examples below 2- embodiments 6, silicon chip 1 also includes and different types of the second class of the back side diffusion layer 15 of positive first kind diffusion layer 12, the back side the second class diffusion layer 15 is only defined and is covered with the second region, and the second grid line layer of the back side 6 and second electrode 5 are all provided with overleaf on the second class diffusion layer 15.

With reference to Examples below 5- embodiments 7, each institute's cell piece 100 also includes：The first grid line layer of the back side 7, the first grid line layer of the back side 7 and first electrode 4 are all provided with overleaf on interlayer 14, and first electrode 4 is electrically connected with the first grid line layer of the back side 7 and is not stacked mutually.Further, with reference to Examples below 5- embodiments 7, back side interlayer 14 be and the positive type identical back side first kind diffusion layer of first kind diffusion layer 12, back side first kind diffusion layer is only defined and is covered with the first region, and the first grid line layer of the back side 7 and first electrode 4 are all provided with overleaf on first kind diffusion layer.

With reference to Examples below 1- embodiments 7, first area and second area are non-discrete region.That is, when first area arbitrarily is divided into more sub-regions, more sub-regions can connect into a continuous first area.When random layer is only defined and is covered with the first region, the random layer is also non-discrete layer, i.e. pantostrat；When second area arbitrarily is divided into more sub-regions, more sub-regions can connect into a continuous second area.When random layer is only defined and is covered with the second region, the random layer is also non-discrete layer, i.e. pantostrat.

With reference to Examples below 1- embodiments 4, first area is that rectangular area is processed with facilitating with second area.With reference to Examples below 5- embodiments 7, first area is distributed with second area in X-shape is referred to, now, first area includes the first connected region and multiple first discrete areas, multiple first discrete areas are spaced apart on the length direction of the first connected region and connected with the first connected region, second area includes the second connected region and multiple second discrete areas, multiple second discrete areas are spaced apart on the length direction of the second connected region and connected with the second connected region, wherein, first connected region be arranged in parallel with the second connected region, multiple first discrete areas and multiple second discrete areas replace one by one between the first connected region and the second connected region.

Embodiment 1,

Reference picture 5- Fig. 9, cell piece 100 include：Silicon chip 1, front side conductive part, lateral conduction part 3, first electrode 4, back of the body electric layer 60 and second electrode 5, wherein, front side conductive part is front gate line layer 2, and silicon chip 1 can include silicon chip 11, positive first kind diffusion layer 12, side interlayer 13 and back side interlayer 14.

Silicon chip 11 is demihull shape, and two surfaces on the thickness direction of silicon chip 11 are respectively smooth surface and shady face, and smooth surface is connected with shady face by side surface.Wherein, positive first kind diffusion layer 12 is located on the smooth surface of silicon chip 11, such as in a preferred embodiment of the invention, positive first kind diffusion layer 12 is covered with the smooth surface of silicon chip 11, so as to reduce the difficulty of processing of positive first kind diffusion layer 12, processing efficiency is improved, reduces processing cost.

Side interlayer 13 is located on the side surface of silicon chip 11, for example, side interlayer 13 can be only defined on a side surface of silicon chip 11, can also be located on multiple side surfaces simultaneously.Preferably, side interlayer 13 is only defined on a side surface of silicon chip 11 and is covered with the side surface.Thus, the processing and manufacture of side interlayer 13 are facilitated.

Lateral conduction part 3 is located on side interlayer 13, that is, lateral conduction part 3 can be directly or indirectly located on side interlayer 13, now, lateral conduction part 3 is located on the side surface of silicon chip 1 and relative with side interlayer 13, that is, along perpendicular to the place side face directions projection of side interlayer 13, contour line of the lateral conduction part 3 without departing from side interlayer 13.

It is located at due to lateral conduction part 3 on the side surface of silicon chip 1, and is not to be embedded in the inside of silicon chip 1, so as to reduces the overall difficulty of processing of cell piece 100, simplifies processing technology, raising processing efficiency, reduction processing cost.

The shady face of silicon chip 11 includes first area and second area, and first area and second area are without common factor.Wherein, first area can contact with each other or be not in contact with each other with second area, that is to say, that the contour line of first area and the contour line of second area can contact with each other or be not in contact with each other.Such as, when the part being in contact with back of the body electric layer 60 of back side interlayer 14 is insulating barrier, first area and second area can contact with each other, and when the part being in contact with back of the body electric layer 60 of back side interlayer 14 is with positive 12 type identical diffusion layer of first kind diffusion layer, first area can be not in contact with each other with second area.Wherein, first area and second area are non-discrete type region.

Back side interlayer 14 is only defined on first area, all do not have back side interlayer 14 in the remaining surface in addition to first area i.e. on the shady face of silicon chip 11, further, back side interlayer 14 is covered with the first region, so, when first area is non-discrete continuum, back side interlayer 14 can with it is non-discrete, be continuously arranged on silicon chip 11.Thus, continuously, i.e. non-discretely it is arranged in due to back side interlayer 14 on silicon chip 11, and it is not discretely, i.e. discontinuously, such as the discrete forms such as scatterplot shape, zebra strip are presented and are dispersed on silicon chip 11, so as to significantly reduce the difficulty of processing of back side interlayer 14, processing efficiency is improved, reduces processing cost, and the power of cell piece 100 can be effectively improved.

Front gate line layer 2 is located on positive first kind diffusion layer 12, that is, front gate line layer 2 can be directly or indirectly located on positive first kind diffusion layer 12, now, front gate line layer 2 is located on the smooth surface of silicon chip 1 and relative with positive first kind diffusion layer 12, in other words, projected along the thickness direction of silicon chip 1, contour line of the front gate line layer 2 without departing from positive first kind diffusion layer 12.

For example, in some embodiments of the invention, silicon chip 1 can also include anti-reflection layer 101, and anti-reflection layer 101 can be located on positive first kind diffusion layer 12.So, when silicon chip 1 includes anti-reflection layer 101, front gate line layer 2 can be directly arranged on anti-reflection layer 101.And when silicon chip 1 does not include anti-reflection layer 101, front gate line layer 2 can be directly arranged on positive first kind diffusion layer 12.

First electrode 4 is located on back side interlayer 14, that is to say, that first electrode 4 can be directly or indirectly located on back side interlayer 14, now, first electrode 4 is located on the shady face of silicon chip 1 and relative with first area, in other words, projected along the thickness direction of silicon chip 1, first electrode 4 is without departing from first area.For example, first electrode 4 can be by being connected on back side interlayer 14 between passivation layer 102.

Back of the body electric layer 60 and second electrode 5 are all provided with the second region, that is, back of the body electric layer 60 and second electrode 5 can be directly or indirectly located on the second area on the shady face of silicon chip 11, now, back of the body electric layer 60 and second electrode 5 are located on the shady face of silicon chip 1 and relative with second area, that is, being projected along the thickness direction of silicon chip 1, electric layer 60 and second electrode 5 are carried on the back without departing from second area.For example, back of the body electric layer 60 and second electrode 5 can be by being connected on the shady face of silicon chip 11 between passivation layer 102.Wherein, first electrode 4 is neither contacted with back of the body electric layer 60 nor contacted with second electrode 5.

In addition, it should be noted that, in some embodiments of the invention, back of the body electric layer 60 mutually can be connected in not stacked and contact with second electrode 5, now, back of the body electric layer 60 and second electrode 5 are entirely disposed in respectively on the shady face of silicon chip 1 and directly contact electrical connection, so as to fully utilization space, the power of raising cell piece 100；In the other embodiment of the present invention, carry on the back electric layer 60 and second electrode 5 can carry on the back electric layer 60 and second electrode 5 and be located at union surface of the both after stacked on the shady face of silicon chip 1 with superposed, now.

Here, it should be noted that, when conducting medium (indirect directly or by anti-reflection layer 101, passivation layer 102) being located on positive first kind diffusion layer 12 or (indirect directly or by anti-reflection layer 101, passivation layer 102) is located on diffusion layer (side first kind diffusion layer and back side first kind diffusion layer 14 as described below) identical with the positive type of first kind diffusion layer 12, the electric charge of a species can be collected；And when the electric charge that another species on the surface without positive first kind diffusion layer 12 that conducting medium (indirect directly or by passivation layer 102) is located on silicon chip 11 or when (indirect directly or by passivation layer 102) is located at diffusion layer (such as the described below back side second class diffusion layer 15) opposite with 12 types of positive first kind diffusion, can be collected.Here, it is necessary to which explanation, the principle that conducting medium collects electric charge on silicon chip should be as it is known to those skilled in the art that I will not elaborate.

In addition, it should be noted that, anti-reflection layer 101 can be respectively provided with the whole smooth surface of silicon chip 1 in embodiment hereof 1-7 and the outermost surface of a side surface, passivation layer 102 can also be respectively provided with the outermost surface of the whole shady face of silicon chip 1 in embodiment hereof 2-7, so as to convenient processing and manufacture.Furthermore, it is necessary to explanation, the concept of anti-reflection layer 101 and passivation layer 102 as described herein should be as it is known to those skilled in the art that it mainly plays a part of to reduce reflection, strengthens charge-trapping.For example, the material of anti-reflection layer 101 and passivation layer 102 can include but is not limited to TiO₂、Al₂O₃、SiNxOy、SiNxCy。

For example, when silicon chip 11 is P-type silicon, positive first kind diffusion layer 12 can be phosphorus-diffused layer, and the conducting medium being now arranged in phosphorus-diffused layer can collect negative electrical charge, and the conducting medium being located in non-phosphorus-diffused layer can collect positive charge.So, due on front gate line layer 2 is located at (such as be directly arranged in or by being connected between anti-reflection layer 101) positive first kind diffusion layer 12, so as to which front gate line layer 2 can collect the electric charge (such as negative electrical charge) of the first species.And carry on the back electric layer 60 and be located on the shady face of (such as be directly arranged in or by being connected between passivation layer 102) silicon chip 11, it can collect the electric charge (such as positive charge) of second species so as to just carry on the back electric layer 60.

Specifically, first electrode 4 is electrically connected to front gate line layer 2 by lateral conduction part 3, so as to which the first species electric charge (such as negative electrical charge) that front gate line layer 2 is collected can pass to first electrode 4 (such as negative electrode)；Second electrode 5 is electrically connected to back of the body electric layer 60, and second electrode 5 (such as positive electrode) can be passed to so as to carry on the back the second species electric charge (such as positive charge) of the collection of electric layer 60.Thus, first electrode 4 and second electrode 5 can export electric energy as the positive and negative polarities of cell piece 100.Further, since lateral conduction part 3 is located at the side of silicon chip 1, so as to which simply and easily front gate line layer 2 and first electrode 4 are effectively electrically connected by lateral conduction part 3, it is ensured that the reliability that cell piece 100 works.

It will be understood by those skilled in the art that, first electrode 4 is needed for opposite polarity electrode with second electrode 5, need to insulate, i.e., be mutually not turned on, do not form electrical connection between each other, now, all parts that first electrode 4 and all parts electrically connected with first electrode 4 electrically connect with second electrode 5 and with second electrode 5 can not directly be turned on, can not turned on indirectly by any extraneous conducting medium, such as can not contact or be kept apart by insulating materials, so as to avoid first electrode 4 from being connected with the short circuit of second electrode 5.

Wherein, back side interlayer 14 is configured to avoid first electrode 4 from being connected with the short circuit of second electrode 5 by silicon chip 11, that is, avoid first electrode 4 from directly being contacted with silicon chip 11 and cause short circuit, such as, back side interlayer 14 can be and front side diffusion layer type identical diffusion layer and/or insulating barrier, i.e. back side interlayer 14 can be with all and front side diffusion layer type identical diffusion layer, can also all insulating barriers, can also a part be with front side diffusion layer type identical diffusion layer, remaining part be insulating barrier.

Thus, on the one hand, when first electrode 4 is located on silicon chip 11 by insulating barrier, first electrode 4 directly can insulate with silicon chip 11, first electrode 4 is avoided to collect the charge type identical electric charge collected with second electrode 5 from silicon chip 11, the problem of short circuit is connected is turned on second electrode 5 by silicon chip 11 so as to be effectively prevented from first electrode 4, that is, avoids first electrode 4 from directly being contacted with silicon chip 11 and causes short circuit.

On the other hand, when by first electrode 4 by being located at front side diffusion layer type identical diffusion layer on silicon chip 11, first electrode 4 can collect and the charge type identical electric charge of the collection of front gate line layer 2, electric charge i.e. opposite with the charge type that second electrode 5 is collected from the silicon chip 11 after diffusion, so as to which first electrode 4 can also be avoided to be connected with the short circuit of second electrode 5, and the power of cell piece 100 can be improved.

Wherein, side interlayer 13 is configured to avoid lateral conduction part 3 from being connected with the short circuit of second electrode 5 by silicon chip 11, so as to avoid first electrode 4 from being connected with the short circuit of second electrode 5, that is, avoids lateral conduction part 3 from directly being contacted with silicon chip 11 and causes short circuit.Such as, side interlayer 13 can be and front side diffusion layer type identical diffusion layer and/or insulating barrier, i.e. side interlayer 13 can be with all and front side diffusion layer type identical diffusion layer, can also all insulating barriers, can also a part be with front side diffusion layer type identical diffusion layer, remaining part be insulating barrier.

Thus, on the one hand, when lateral conduction part 3 is located on silicon chip 11 by insulating barrier, lateral conduction part 3 directly can insulate with silicon chip 11, lateral conduction part 3 is avoided to collect the charge type identical electric charge collected with second electrode 5 from silicon chip 11, the problem of short circuit is connected is turned on second electrode 5 by silicon chip 11 so as to be effectively prevented from lateral conduction part 3, that is, avoids lateral conduction part 3 from directly being contacted with silicon chip 11 and causes short circuit.

On the other hand, when by lateral conduction part 3 by being located at front side diffusion layer type identical diffusion layer on silicon chip 11, lateral conduction part 3 can be collected and the charge type identical electric charge of the collection of front gate line layer 2, electric charge i.e. opposite with the charge type that second electrode 5 is collected from the silicon chip 11 after diffusion, so as to which lateral conduction part 3 can also be avoided to be connected with the short circuit of second electrode 5, avoid lateral conduction part 3 from directly being contacted with silicon chip 11 and cause short circuit, and the power of cell piece 100 can be improved.

Specifically, in an embodiment of the present invention, in side interlayer 13 and back side interlayer 14 it is at least one at least partially with the positive type identical diffusion layer of first kind diffusion layer 12, that is, side interlayer 13 at least partially with the positive type identical diffusion layer of first kind diffusion layer 12, back side interlayer 14 at least partially with the positive type identical diffusion layer of first kind diffusion layer 12, so as to not only may insure the insulation effect of first electrode 4 and second electrode 5, the power of cell piece 100 can also be improved.

Preferably, back side interlayer 14 is all with the positive type identical diffusion layer of first kind diffusion layer 12, i.e., back side interlayer 14 is to be covered with the diffusion layer of the back side first on the first region.Thus, conveniently process and insulating reliability is good.Preferably, side interlayer 13 is all with the positive type identical diffusion layer of first kind diffusion layer 12, i.e. side interlayer 13 is is covered with the side diffusion layer on the side surface of silicon chip 11.Thus, conveniently process and insulating reliability is good.

Here, it is necessary to which the principle that the concept such as explanation, silicon chip 11, diffusion layer, anti-reflection layer 101, passivation layer 102 and conducting medium collect electric charge from silicon chip 1 is well known to the skilled person, I will not elaborate.

In addition, in a preferred embodiment of the invention, front gate line layer 2 and the second grid line layer of the back side 6 described hereinafter, the first grid line layer of the back side 7 can be the conducting medium layer being made up of the electrically conductive thin grid line of a plurality of setting spaced apart, wherein, thin grid line can be made up of silver-colored material, so as to which on the one hand conduction rate can be improved, shading-area on the other hand can be reduced, so as in a disguised form increase the power of cell piece 100.Back of the body electric layer 60 can be aluminum layer, i.e. Al-BSF, so as on the one hand improve conduction rate, on the other hand can reduce cost.

To sum up, cell piece 100 according to embodiments of the present invention, due in back side interlayer 14 and side interlayer 13 it is at least one at least partially with the positive type identical diffusion layer of first kind diffusion layer 12, so as to not only may insure the insulation of first electrode 4 and second electrode 5, the power of cell piece 100 can also be effectively improved.

And, by setting lateral conduction part 3 in the side of silicon chip 11, first electrode 4 on the existing smooth surface of cell piece 100 can be migrated to backlight side by the sensitive side of silicon chip 1, to prevent sensitive side shading of the first electrode 4 to silicon chip 1, improve the power of cell piece 100, and it may insure that first electrode 4 and second electrode 5 are respectively positioned on the same side of silicon chip 1, consequently facilitating the electrical connection between multiple cell pieces 100, reduce welding difficulty, the damaged probability of cell piece 100 when reducing solder usage amount, while reducing welding and in follow-up laminating technology.

In addition, by the way that lateral conduction part 3 is located on the side surface of silicon chip 1, so as to significantly reduce the difficulty of processing of cell piece 100 (such as without processing perforate on silicon chip 1 and the manufacturing procedures such as conducting medium being injected into perforate), and then processing speed is improved, reduce processing mortality and processing cost.In addition, when on the side side surface being located at lateral conduction part 3 on the width of silicon chip 11, the path that electric charge is transmitted from the sensitive side of silicon chip 1 to backlight side can effectively be shortened, improve charge transfer rate, so as in a disguised form improve the power of cell piece 100.

Preferably, when first area and second area are non-discrete region and during without occuring simultaneously, being not in contact with each other.Preferably, when silicon chip 1 is rectangle lamellar body, first area and second area can be rectangular area and arranged spaced apart successively on the width of silicon chip 1.Can be with the larger first electrode 4 of working (finishing) area and back of the body electric layer 60, it is preferable that the outward flange along the thickness direction projection of silicon chip 1, first electrode 4 falls on the contour line of first area, and back of the body electric layer 60 is covered with the second region, and second electrode 5 is located in back of the body electric layer 60.Thus, it is possible to maximumlly utilize first area and second area, the power of cell piece 100 is improved.Here, it should be noted that, for face shape part (such as first electrode 4 and second electrode 5 of rectangle demihull shape as described herein), " outward flange " refers to its contour line, for linear element (such as thin grid line as described herein), " outward flange " refers to its both ends end points.

In a preferred embodiment of the invention, front gate line layer 2 is included along a plurality of positive face grid line layer 21 perpendicular to the extension of the length direction of lateral conduction part 3, that is to say, that each positive face grid line layer 21 is each perpendicular to the length direction of lateral conduction part 3.Thus, it is possible to shorten the charge transfer path of positive face grid line layer 21, charge transfer efficiency is improved, improves the power of cell piece 100.

Below, the preparation method of the cell piece 100 of the present embodiment 1 is briefly introduced.

Step a1, the silicon chip 11 (such as length is 156mm) of the constant rectangle demihull shape of 3-15 parts (preferably 5-10 parts) length by the conventional silicon chip body of square (such as conventional silicon chip that specification is 156mm*156mm) decile and is cut into by laser, then carries out the follow-up production process of cell piece 100 again.Certainly, the invention is not restricted to this, other modes or technique can also be used to obtain the silicon chip 11 of rectangle demihull shape.Here, it should be noted that the conventional silicon chip body of square is preferably divided into three parts and more than three parts, so as to shorten the distance that electric charge migrates from smooth surface to shady face, make the collection of electric charge efficiently easy, so as to improve the power of cell piece 100, moreover, when the conventional silicon chip body of square is divided into 15 parts and less than 15 parts, easy cutting processing, and the solder of the follow-up consumption of connection in series-parallel cell piece 100 is less, so as to improve the overall power after the connection in series-parallel of cell piece 100, reduces cost.

Step a2, cleaning and texturing：Cleaning removes the dirt on 11 each surface of silicon chip, and making herbs into wool reduces the reflectivity on 11 each surface of silicon chip；

Step a3, diffusion：Double side diffusion is carried out to silicon chip 11 by diffusion furnace and prepares P-N junction, makes each surface of silicon chip 11 all there is same type of diffusion layer；

Step a4, mask protection：With the diffusion layer (being used as reverse diffusion layer 14) on paraffin-protected first area and the diffusion layer (being used as side diffusion layer 13) on the side surface adjacent with first area.

Step a5, etch：Remove on the side surface of silicon chip 11 and shady face not by paraffin-protected back of the body knot；

Step a6, remove it is paraffin-protected, remove phosphorosilicate glass, so as to obtain it is paraffin-protected under reverse diffusion layer 14 and side diffusion layer 13；

Step a7, anti-reflection layer 101 is deposited in front side diffusion layer 12, the material of anti-reflection layer 101 includes but is not limited to TiO2, Al2O3, SiNxOy, SiNxCy；

Step a8, second area silk-screen printing along its length carry on the back electric layer 60, in back of the body electric layer 60 along its length silk-screen printing second electrode 5, overleaf silk-screen printing first electrode 4 and dried along its length on diffusion layer 14, wherein, first electrode 4 just overlaps with reverse diffusion layer 14, certain safe distance be present between back of the body electric layer 60 and first electrode 4, be not connected to short circuit；

Step a9, in front side diffusion layer 12 in the width direction silk-screen printing grid line layer 2 so that every strip grid line 21 in grid line layer 2 is each perpendicular to second electrode 5, and dries；

Step a10, the silk-screen printing lateral conduction part 3, and drying along its length on side diffusion layer 13.

Embodiment 2,

Reference picture 10- Figure 14, the present embodiment 2 is roughly the same with the structure of embodiment 1, and wherein identical part uses identical reference, the difference is that only：Second area in embodiment 1 is provided with back of the body electric layer 60, and back of the body electric layer 60 is provided with second electrode 5, and second area is provided with the back side the second class diffusion layer 15 in the present embodiment 2, the back side the second class diffusion layer 15 is provided with the second grid line layer of the back side 6 and second electrode 5.

Cell piece 100 includes：Silicon chip 1, front side conductive part, lateral conduction part 3, first electrode 4, the second grid line layer of the back side 6 and second electrode 5, wherein, front side conductive part is front gate line layer 2, silicon chip 1 can include silicon chip 11, positive first kind diffusion layer 12, the back side the second class diffusion layer 15, side interlayer 13 and back side interlayer 14, wherein, side interlayer 13 can be that can be and the positive type identical back side first kind diffusion layer of first kind diffusion layer 12 with the positive type identical side diffusion layer of first kind diffusion layer 12, back side interlayer 14.Wherein, the second class of back side diffusion layer 15 is included along the sub- grid line layer 61 in a plurality of back side second perpendicular to the extension of the length direction of second electrode 5, that is to say, that the sub- grid line layer 61 in each back side second is each perpendicular to the length direction of second electrode 5.Thus, it is possible to shorten the charge transfer path of the sub- grid line layer 61 in the back side second, charge transfer efficiency is improved, improves the power of cell piece 100.

Specifically, the shady face of silicon chip 11 includes first area and second area, and first area and second area are without occuring simultaneously and be not in contact with each other, that is to say, that the contour line of first area does not contact with the contour line of second area.

Back side first kind diffusion layer is only defined on first area, all do not have back side first kind diffusion layer in the remaining surface in addition to first area i.e. on the shady face of silicon chip 11, further, back side first kind diffusion layer is covered with the first region, so, when first area is non-discrete continuum, back side first kind diffusion layer can with it is non-discrete, be continuously arranged on silicon chip 11.Thus, continuously, i.e. non-discretely it is arranged in due to back side first kind diffusion layer on silicon chip 11, and it is not discretely, i.e. discontinuously, such as the discrete forms such as scatterplot shape, zebra strip are presented and are dispersed on silicon chip 11, so as to significantly reduce the difficulty of processing of back side first kind diffusion layer, processing efficiency is improved, reduces processing cost, and the power of cell piece 100 can be effectively improved.

The back side the second class diffusion layer 15 is only defined on second area, i.e., does not all have the back side the second class diffusion layer 15 in the remaining surface in addition to second area on the shady face of silicon chip 11.Further, the second class of back side diffusion layer 15 is covered with the second region, so, when second area is non-discrete continuum, the back side the second class diffusion layer 15 can with it is non-discrete, be continuously arranged on silicon chip 11.Thus, continuously, i.e. non-discretely it is arranged in due to the back side the second class diffusion layer 15 on silicon chip 11, and it is not discretely, i.e. discontinuously, such as the discrete forms such as scatterplot shape, zebra strip are presented and are dispersed on silicon chip 11, so as to significantly reduce the difficulty of processing of the back side the second class diffusion layer 15, processing efficiency is improved, reduces processing cost, and the power of cell piece 100 can be effectively improved.

First electrode 4 is located on the first kind diffusion layer of the back side, that is, first electrode 4 can be directly or indirectly located on the first kind diffusion layer of the back side, now, first electrode 4 is located on the shady face of silicon chip 1 and relative with first area, that is, being projected along the thickness direction of silicon chip 1, first electrode 4 is without departing from first area.For example, in some embodiments of the invention, silicon chip 1 can also include passivation layer 102, and passivation layer 102 can be located on the first kind diffusion layer of the back side.So, when silicon chip 1 includes passivation layer 102, first electrode 4 can be directly arranged on passivation layer 102.And when silicon chip 1 does not include passivation layer 102, first electrode 4 can be directly arranged on the first kind diffusion layer of the back side.

The back side the second class diffusion layer 15 and second electrode 5 are all provided with overleaf on the second class diffusion layer 15, that is, the back side the second class diffusion layer 15 and second electrode 5 can be directly or indirectly located on the back side the second class diffusion layer 15, now, the back side the second class diffusion layer 15 and second electrode 5 are located on the shady face of silicon chip 1 and relative with second area, that is, being projected along the thickness direction of silicon chip 1, the back side the second class diffusion layer 15 and second electrode 5 are without departing from second area.Wherein, first electrode 4 is neither contacted with the back side the second class diffusion layer 15 nor contacted with second electrode 5.

For example, in some embodiments of the invention, silicon chip 1 can also include passivation layer 102, and passivation layer 102 can be located on the back side the second class diffusion layer 15.So, when silicon chip 1 includes passivation layer 102, the back side the second class diffusion layer 15 and second electrode 5 can be directly arranged on passivation layer 102.And when silicon chip 1 does not include passivation layer 102, the back side the second class diffusion layer 15 and second electrode 5 can be directly arranged on the back side the second class diffusion layer 15.

In addition, it should be noted that, in some embodiments of the invention, the back side the second class diffusion layer 15 mutually can be connected in not stacked and contact with second electrode 5, now, the back side the second class diffusion layer 15 and second electrode 5 are entirely disposed in respectively on the shady face of silicon chip 1 and edge directly contacts electrical connection, so as to fully utilization space, the power of raising cell piece 100；In the other embodiment of the present invention, the back side the second class diffusion layer 15 and second electrode 5 can be with superposed, now, and the back side the second class diffusion layer 15 and second electrode 5 are located on the shady face of silicon chip 1 with union surface of the both after stacked.

Wherein, because first area and second area are without occuring simultaneously and be not in contact with each other, so as to the larger first electrode 4 of working (finishing) area, so as to the larger back side the second class diffusion layer 15 of working (finishing) area and second electrode 5, preferably, along the outward flange of the thickness direction projection of silicon chip 1, first electrode 4 falls on the contour line of first area, the outward flange that the back side the second class diffusion layer 15 and second electrode 5 are overall is all fallen within the contour line of second area.Thus, it is possible to maximumlly utilize first area and second area, the power of cell piece 100 is improved.

Here, it should be noted that, " first kind diffusion layer " and " the second class diffusion layer " specifically described herein is two different types of diffusion layers, and different types of electric charge can be collected when being located at conducting medium on (such as be directly arranged in or by being connected between anti-reflection layer 101 as described herein or passivation layer 102) first kind diffusion layer and the second class diffusion layer.In addition, it is necessary to which explanation, the concept of anti-reflection layer 101 and passivation layer 102 as described herein are well known to those skilled in the art, both mainly plays a part of to reduce reflection, strengthens charge-trapping.

Thus, positive first kind diffusion layer 12, back side first kind diffusion layer and first kind diffusion layer in side as described herein in " first kind diffusion layer " are same kind of diffusion layer, when conducting medium is located on first kind diffusion layer, the electric charge of the first species can be collected；And the back side the second class diffusion layer 15 in " the second class diffusion layer " is the diffusion layer of another species, when conducting medium being located on the second class diffusion layer, can collect the electric charge of second species.Here, it is necessary to which explanation, the principle that conducting medium collects electric charge on silicon chip 1 should be as it is known to those skilled in the art that I will not elaborate.

Such as, when silicon chip 11 is P-type silicon, first kind diffusion layer can be phosphorus-diffused layer, and the conducting medium being now arranged in phosphorus-diffused layer can collect negative electrical charge, and the second class diffusion layer can be diffused layer of boron, the conducting medium being arranged on diffused layer of boron can collect positive charge.In another example when silicon chip 11 is N-type silicon, " first kind diffusion layer " can be diffused layer of boron, and " the second class diffusion layer " can be phosphorus-diffused layer, repeat no more here.

So, due on front gate line layer 2 is located at (such as be directly arranged in or by being connected between anti-reflection layer 101) first kind diffusion layer, so as to which front gate line layer 2 can collect the electric charge (such as negative electrical charge) of the first species.And the back side the second class diffusion layer 15 is located on (such as be directly arranged in or by being connected between passivation layer 102) second class diffusion layer, so as to which positive the second class of back side diffusion layer 15 can collect the electric charge (such as positive charge) of second species.

Specifically, first electrode 4 is electrically connected to front gate line layer 2 by lateral conduction part 3, so as to which the first species electric charge (such as negative electrical charge) that front gate line layer 2 is collected can pass to first electrode 4 (such as negative electrode)；Second electrode 5 is electrically connected to the back side the second class diffusion layer 15, so as to which the second species electric charge (such as positive charge) that the back side the second class diffusion layer 15 is collected can pass to second electrode 5 (such as positive electrode).Thus, first electrode 4 and second electrode 5 can export electric energy as the positive and negative polarities of cell piece 100.

So, because first electrode 4 can collect the first species electric charge by the front gate line layer 2 positioned at the sensitive side of silicon chip 1, second electrode 5 can be by collecting second species electric charge for the back side the second class diffusion layer 15 of the backlight side of silicon chip 1, so as to be effectively improved space availability ratio, further improve the power of cell piece 100 so that cell piece 100 can turn into attractive in appearance, efficient double-side cell.

Specifically,The preparation method of cell piece 100 in the present embodiment 2 and the preparation method of the cell piece 1 in embodiment 1 are substantially the same,Difference is,In the silicon chip 1 in preparing the present embodiment 2,Two-sided different types of diffusion is carried out to silicon chip 11,Even if the smooth surface and shady face of silicon chip 11 diffuse out different types of diffusion layer respectively,And the diffusion layer on smooth surface is set to be extended to by a side surface of silicon chip 11 on the shady face of silicon chip 11,To obtain positive first kind diffusion layer 12,Side first kind diffusion layer 13 and back side first kind diffusion layer 14,Then overleaf it is deposited and the material identical passivation layer 102 of anti-reflection layer 101 on first kind diffusion layer 14 and the back side the second class diffusion layer 15 and silicon chip 11 again,Then the second grid line layer of the silk-screen printing back side 6 on passivation layer 102 again.

Embodiment 3,

Reference picture 15- Figure 19, the present embodiment 3 is roughly the same with the structure of embodiment 2, and wherein identical part uses identical reference, the difference is that only：First area and second area in embodiment 2 are without occuring simultaneously and be not in contact with each other, and first area and second area are without occuring simultaneously and contact with each other in the present embodiment 3, that is to say, that the contour line of first area and the profile linear contact lay of second area.

Specifically, first area and second area are without occuring simultaneously and contact with each other, first electrode 4 is set on the first region, that is, first electrode 4 can directly or indirectly be set on the first region, now, first electrode 4 is located on the shady face of silicon chip 1 and relative with first area, that is, being projected along the thickness direction of silicon chip 1, first electrode 4 is without departing from first area and outside second area.Back side grid line layer and second electrode 5 are all provided with not contacting with first electrode 4 on the second region and, that is, back side grid line layer and second electrode 5 can directly or indirectly be set on the second region, and back side grid line layer does not contact with first electrode 4, second electrode 5 does not also contact with first electrode 4, now, back side grid line layer and second electrode 5 are located on the shady face of silicon chip 1 and relative with second area, that is, projected along the thickness direction of silicon chip 1, back side grid line layer and second electrode 5 are without departing from second area and outside first area.Thus, it is possible to it is effectively prevented from first electrode 4 and the contact short circuit of second electrode 5.

Embodiment 4,

Reference picture 20- Figure 24, the present embodiment 4 is roughly the same with the structure of embodiment 3, and wherein identical part uses identical reference, the difference is that only：Side interlayer 13 in embodiment 3 is side first kind diffusion layer, back side interlayer 14 is back side first kind diffusion layer, and the side interlayer 13 and back side interlayer 14 in the present embodiment 4 are insulating barrier.

Specifically, the preparation method of cell piece 100 in the present embodiment 4 and the preparation method of the cell piece 1 in embodiment 2 are substantially the same, difference is, in the silicon chip 1 in preparing the present embodiment 4, even if two-sided different types of diffusion, the smooth surface of silicon chip 11 and shady face are carried out to silicon chip 11 diffuses out different types of diffusion layer respectively, with obtain positive first kind diffusion layer 12 and the back side the second class diffusion layer 15 and silicon chip 11 shady face side and the side surface adjacent with making on process insulating barrier, to obtain back side interlayer 14 and side interlayer 13.

Embodiment 5,

Reference picture 25- Figure 31, the present embodiment 5 is roughly the same with the structure of embodiment 3, and wherein identical part uses identical reference, the difference is that only：Firstth, first electrode 4 is provided only with the back side first kind diffusion layer (i.e. back side interlayer 14) in embodiment 3, and the first grid line layer of the back side 7 electrically connected with first electrode 4 is additionally provided with the back side first kind diffusion layer (i.e. back side interlayer 14) in the present embodiment 5.Secondth, the first area in the present embodiment 5 refers to cross-distribution with second area into contact.

The first grid line layer of the back side 7 and first electrode 4 are located on the first kind diffusion layer of the back side, that is, the grid line layer of face first and first electrode 4 can be directly or indirectly located on the first kind diffusion layer of the back side, now, the first grid line layer of the back side 7 and first electrode 4 are located on the shady face of silicon chip 1 and relative with first area, that is, being projected along the thickness direction of silicon chip 1, the first grid line layer of the back side 7 and first electrode 4 are without departing from first area and outside second area.

For example, in some embodiments of the invention, silicon chip 1 can also include passivation layer 102, and passivation layer 102 can be located on the first kind diffusion layer of the back side.So, when silicon chip 1 includes passivation layer 102, the first grid line layer of the back side 7 and first electrode 4 can be directly arranged on passivation layer 102.And when silicon chip 1 does not include passivation layer 102, the first grid line layer of the back side 7 and first electrode 4 can be directly arranged on the first kind diffusion layer of the back side.

In addition, it should be noted that, in some embodiments of the invention, the first grid line layer of the back side 7 mutually can be connected in not stacked and contact with first electrode 4, now, the first grid line layer of the back side 7 and first electrode 4 are entirely disposed on the shady face of silicon chip 1 respectively and edge directly contacts electrical connection, so as to fully utilization space, the power of raising cell piece 100；In the other embodiment of the present invention, the first grid line layer of the back side 7 and first electrode 4 can be with superposed, now, and the first grid line layer of the back side 7 and first electrode 4 are located on the shady face of silicon chip 1 with union surface of the both after stacked.

Thus, according to the cell piece 100 of the present embodiment, by processing the front gate line layer 2 being connected with first electrode 4 and the first grid line layer of the back side 7 respectively in the smooth surface and shady face of silicon chip 1, and the second grid line layer of the back side 6 by being connected in the shady face processing of silicon chip 1 with second electrode 5, so that cell piece 100 can be double-side cell, power is higher.

In one embodiment of the invention, first area and second area are distributed in abutment formula X-shape, that is, the contour line of first area and the profile linear contact lay of second area, such as, first area and second area can be completely seamless to inserting, and form a continuous, complete, non-porous non-discrete region.For instance, it is preferred that first area and second area can be covered with the shady face of silicon chip 11.Thus, it is possible to fully utilization space, improve cell piece 100 power.Here, it is necessary to which explanation, " referring to X-shape " refers to intersecting similar to two hand fingers of left and right and non-overlapping shape.

Specifically, first area includes the first connected region and multiple first discrete areas, multiple first discrete areas are spaced apart on the length direction of the first connected region and connected with the first connected region, second area includes the second connected region and multiple second discrete areas, and multiple second discrete areas are spaced apart on the length direction of the second connected region and connected with the second connected region.

Wherein, the quantity of first discrete areas and the second discrete areas is unlimited, and, first connected region, the first discrete areas, the second connected region, the shape of the second discrete areas are unlimited, such as first discrete areas and the second discrete areas can be formed as triangle, semicircle, rectangle etc., the first discrete areas and the second discrete areas can be formed as rectangle, wave band shape etc..

Wherein, first connected region is oppositely arranged with the second connected region, such as, first connected region is parallel with the second connected region or general parallel orientation (having a smaller angle) is set, multiple first discrete areas and multiple second discrete areas replace one by one between the first connected region and the second connected region, that is, along the first connected region, i.e. along the length direction of the second connected region, one the first discrete areas of be set with successively, one the second discrete areas, another first discrete areas, another second discrete areas, the rest may be inferred, multiple first discrete areas and multiple second discrete areas alternate turns cross-distribution one by one.

Wherein, the contour line of the first connected region contacts respectively with the contour line of the second connected region and the contour line of the second discrete areas, and the contour line of the second connected region contacts respectively with the contour line of the first connected region and the contour line of the first discrete areas.Thus, it is possible to ensure that first area and second area refer to cross arrangement in contact.

Further, first electrode 4 is located in the first connected region, and the first grid line layer of the back side 7 is located in multiple first discrete areas.In other words, first electrode 4 is oppositely arranged with the first connected region, and the first grid line layer of the back side 7 is oppositely arranged with multiple first discrete areas.That is, along silicon chip 1 thickness direction project, first electrode 4 without departing from the first connected region contour line, the first grid line layer of the back side 7 without departing from multiple first discrete areas contour line and positioned at second area contour line outside.Thus, first electrode 4 and the first grid line layer of the back side 7 is rationally distributed simple, is easy to overleaf process on first kind diffusion layer.

Preferably, the first grid line layer of the back side 7 is included along the sub- grid line layer 71 in multiple back sides first for extending perpendicular to the first connected region length direction and being spaced apart on the first connected region length direction.Thus, the first grid line layer of the back side 7 can with shorter path by the charge transfer of collection to first electrode 4, so as to improve charge transfer efficiency, improve the power of cell piece 100.

Further, second electrode 5 is located in the second connected region, and the second grid line layer of the back side 6 is located in multiple second discrete areas.In other words, second electrode 5 is oppositely arranged with the second connected region, and the second grid line layer of the back side 6 is oppositely arranged with multiple second discrete areas.That is, along silicon chip 1 thickness direction project, second electrode 5 without departing from the second connected region contour line, the second grid line layer of the back side 6 without departing from multiple second discrete areas contour line and positioned at first area contour line outside.Thus, second electrode 5 and the second grid line layer of the back side 6 is rationally distributed simple, is easy to overleaf process on the second class diffusion layer 15.

Preferably, the second grid line layer of the back side 6 is included along the sub- grid line layer 61 in multiple back sides second for extending perpendicular to the second connected region length direction and being spaced apart on the second connected region length direction.Thus, the second grid line layer of the back side 6 can with shorter path by the charge transfer of collection to second electrode 5, so as to improve charge transfer efficiency, improve the power of cell piece 100.

Wherein, the contour line of the sub- grid line layer 71 in each back side first does not contact with the second connected region and the second discrete areas, that is to say, that the sub- grid line layer 71 in each back side first grid line layer 61 sub- with the back side second and second electrode 5 do not contact.Wherein, the contour line of the sub- grid line layer 61 in each back side second does not contact with the first connected region and the first discrete areas, that is to say, that the sub- grid line layer 61 in each back side second grid line layer 71 sub- with the back side first and first electrode 4 do not contact.

Specifically, the preparation method of the cell piece 100 in the present embodiment 5 and the preparation method of the cell piece 1 in embodiment 2 are substantially the same, and difference is, after silicon chip 1 has been prepared, then the sub- grid line layer 61 in the back side second are overleaf processed on the second class diffusion layer 15.

Embodiment 6,

Reference picture 32- Figure 38, the present embodiment 6 is roughly the same with the structure of embodiment 5, and wherein identical part uses identical reference, the difference is that only：First area in embodiment 5 and second area refer to cross-distribution into contact, and the first area in the present embodiment 6 and second area into contactless finger cross-distribution.

The contour line of first connected region does not contact with the contour line of the second connected region and the contour line of the second discrete areas, and the contour line of the second connected region does not contact with the contour line of the first connected region and the contour line of the first discrete areas.Thus, it is possible to ensure first area and second area is non-refers to cross arrangement in contact.Wherein, the contour line of the sub- grid line layer 71 in each back side first does not contact with the second connected region and the second discrete areas, that is to say, that the sub- grid line layer 71 in each back side first grid line layer 61 sub- with the back side second and second electrode 5 do not contact.Wherein, the contour line of the sub- grid line layer 61 in each back side second does not contact with the first connected region and the first discrete areas, that is to say, that the sub- grid line layer 61 in each back side second grid line layer 71 sub- with the back side first and first electrode 4 do not contact.

Embodiment 7,

Reference picture 39- Figure 45, the present embodiment 7 is roughly the same with the structure of embodiment 5, and wherein identical part uses identical reference, the difference is that only：It is covered with the back side the second class diffusion layer 15 on second area in embodiment 5, and the second class diffusion layer is not provided with the second area in the present embodiment 7.

Second electrode 5 and the second grid line layer of the back side 6 can directly or indirectly be set on the second region.Such as in the optional example of the present invention, passivation layer 102 can be covered with second area, the second grid line layer of the back side 6 and second electrode 5 can be directly arranged on passivation layer 102.And when silicon chip 1 does not include passivation layer 102, the second grid line layer of the back side 6 and second electrode 5 can be directly arranged on second area.

In the description of the invention, it will be appreciated that, the orientation or position relationship of the instructions such as term " on ", " under ", "front", "rear" are based on orientation shown in the drawings or position relationship, it is for only for ease of the description present invention and simplifies description, rather than the device or element of instruction or hint meaning there must be specific orientation, with specific azimuth configuration and operation, therefore it is not considered as limiting the invention.

In the present invention, unless otherwise clearly defined and limited, the term such as term " installation ", " connected ", " connection ", " fixation " should be interpreted broadly, such as, can be joined directly together, it can also be indirectly connected by intermediary, can be connection or the interaction relationship of two elements of two element internals.For the ordinary skill in the art, the concrete meaning of above-mentioned term in the present invention can be understood as the case may be.In the present invention, unless otherwise clearly defined and limited, fisrt feature can be that the first and second features directly contact "above" or "below" second feature, or the first and second features pass through intermediary mediate contact.

In the description of this specification, the description of reference term " one embodiment ", " some embodiments ", " example ", " specific example " or " some examples " etc. means that combining specific features, structure, material or feature that the embodiment or example describe is contained at least one embodiment or example of the present invention.In this manual, identical embodiment or example are necessarily directed to the schematic representation of above-mentioned term.Moreover, specific features, structure, material or the feature of description can combine in an appropriate manner in any one or more embodiments or example.In addition, in the case of not conflicting, the different embodiments or example and the feature of different embodiments or example described in this specification can be combined and combined by those skilled in the art.

Although an embodiment of the present invention has been shown and described, it will be understood by those skilled in the art that：A variety of change, modification, replacement and modification can be carried out to these embodiments, the scope of the present invention is limited by claim and its equivalent in the case where not departing from the principle and objective of the present invention.

Claims

A kind of 1. cell piece component, it is characterised in that including：

The multiple cell pieces arranged successively along longitudinal direction, each cell piece include silicon chip, are located on the silicon chip smooth surface Front side conductive part, two electrodes being located on the silicon chip shady face and be located on the silicon chip side surface and electrically connect Lateral conduction part between the front side conductive part and an electrode, wherein, two electrodes extend transversely And distribution is spaced apart on the longitudinal direction；

Conductive strips, the conductive strips it is identical with the bearing of trend of the electrode and with it is close to each other and respectively positioned at two neighboring Two electrodes on the cell piece electrically connect two cell piece serial or parallel connections so that adjacent.
2. cell piece component according to claim 1, it is characterised in that on the bearing of trend of the conductive strips, institute The development length for stating conductive strips is more than or equal to the development length of each electrode turned on by the conductive strips, and the conduction The both ends of band exceed or flushed in respectively the respective end of each electrode turned on by the conductive strips.
3. cell piece component according to claim 1, it is characterised in that perpendicular to the conductive strips bearing of trend On direction, the span of the conductive strips is more than or equal to the span sum of two electrodes turned on by the conductive strips, and institute Two sides for stating conductive strips exceed or flushed in respectively the both sides of two electrodes turned on by the conductive strips away from each other Side.
4. cell piece component according to claim 1, it is characterised in that the conductive strips are identical including structure and hanging down Directly it is covered each by just by the conduction in the two half-unit being sequentially arranged on the conductive strips bearing of trend, each half portion Two electrodes with conducting.
5. cell piece component according to claim 1, it is characterised in that perpendicular to the conductive strips bearing of trend On direction, the gap between every two adjacent cell pieces is less than or equal to 0.1mm.
6. cell piece component according to claim 1, it is characterised in that the silicon chip is perpendicular to the lateral conduction Span where part in side face directions is 20mm-60mm.
7. cell piece component according to claim 6, it is characterised in that the silicon chip is for rectangle lamellar body and by pros Shape conventional silicon wafers body is split to form according to the constant rule of length.
8. cell piece component according to claim 6, it is characterised in that the silicon chip is rectangle lamellar body, two institutes State electrode recline respectively the silicon chip two long sides set and along the silicon chip length direction extend, the lateral conduction Part is located on a long side side surface of the silicon chip.
9. cell piece component according to claim 1, it is characterised in that two electricity on each cell piece Pole is respectively the first electrode and the non-second electrode electrically connected with the lateral conduction part electrically connected with the lateral conduction part,

The silicon chip includes：Silicon chip, positive first kind diffusion layer and back side interlayer, wherein, the backlight of the silicon chip Face includes first area and second area, and the positive first kind diffusion layer is located on the smooth surface of the silicon chip, it is described just Face electric-conductor is located on the positive first kind diffusion layer, and the back side interlayer is only defined and is covered with the first area, The first electrode is located on the back side interlayer, the second electrode be located on the second area and with the first electrode Do not contact, wherein, at least partially insulating barrier of the back side interlayer or with the positive first kind diffusion channel type identical Diffusion layer.
10. cell piece component according to claim 9, it is characterised in that the silicon chip also includes：Side interlayer, The side interlayer is located on the side surface of the silicon chip, and the lateral conduction part is located on the side interlayer, the side At least partially insulating barrier of face interlayer spreads channel type identical diffusion layer with the positive first kind.
11. cell piece component according to claim 9, it is characterised in that each cell piece also includes：

Carry on the back electric layer, it is described the back of the body electric layer be located on the second area, the second electrode be located at it is described the back of the body electric layer on and with it is described Carry on the back electric layer electrical connection.
12. cell piece component according to claim 9, it is characterised in that each cell piece also includes：

The grid line layer of the back side second, the grid line layer of the back side second and the second electrode are each provided on the second area, and institute Second electrode is stated to electrically connect with the grid line layer of the back side second and be not stacked mutually.
13. cell piece component according to claim 12, it is characterised in that the silicon chip also includes and described positive the A kind of different types of the second class of back side diffusion layer of diffusion layer, the second class of back side diffusion layer are only defined and are covered with described On two regions, the grid line layer of the back side second and the second electrode are each provided on the second class of back side diffusion layer.
14. cell piece component according to claim 9, it is characterised in that each cell piece also includes：

The grid line layer of the back side first, the grid line layer of the back side first and the first electrode are each provided on the back side interlayer, and institute First electrode is stated to electrically connect with the grid line layer of the back side first and be not stacked mutually.
15. cell piece component according to claim 14, it is characterised in that the back side interlayer is and described positive the One kind diffusion channel type identical back side first kind diffusion layer, the back side first kind diffusion layer are only defined and are covered with described the On one region, the grid line layer of the back side first and the first electrode are each provided on the back side first kind diffusion layer.
16. cell piece component according to claim 9, it is characterised in that the first area and the second area It is non-discrete region.
17. cell piece component according to claim 16, it is characterised in that the first area and the second area It is distributed in X-shape is referred to, wherein, the first area includes the first connected region and multiple first discrete areas, multiple described First discrete areas is spaced apart on the length direction of first connected region and connected with first connected region, institute Stating second area includes the second connected region and multiple second discrete areas, and multiple second discrete areas connect described second It is spaced apart on the length direction in logical region and is connected with second connected region, wherein, first connected region and institute State the second connected region to be arranged in parallel, multiple first discrete areas and multiple second discrete areas connect described first It is logical to replace one by one between region and second connected region.
A kind of 18. cell piece matrix, it is characterised in that

It is in series by multiple cell piece parallel components,

Wherein, each cell piece parallel component is formed in parallel by multiple cell piece series components,

Wherein, each cell piece series component is the cell piece component according to any one of claim 1-17, often Multiple cell pieces in the individual cell piece component are sequentially connected in series by the conductive strips.
19. cell piece matrix according to claim 18, it is characterised in that the cell piece parallel component is two, Each cell piece parallel component includes three cell piece series components.
A kind of 20. solar cell module, it is characterised in that including：The first face set gradually from sensitive side to backlight side Plate, the first tack coat, battery, the second tack coat and second panel, wherein, the battery is according to claim 1-17 Any one of cell piece component or the cell piece matrix according to any one of claim 18-19.