CN107423206A - A kind of method and device for weighing the system management interrupt time - Google Patents
A kind of method and device for weighing the system management interrupt time Download PDFInfo
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- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
- G06F11/3409—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment
- G06F11/3419—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment by assessing time
- G06F11/3423—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment by assessing time where the assessed time is active or idle time
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- G—PHYSICS
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- G06F11/00—Error detection; Error correction; Monitoring
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- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
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Abstract
The invention discloses a kind of method and device for weighing the system management interrupt time, this method includes：After triggering SMI interrupt, the counting of the first TSC clocks is read into SMM processor at first, as very first time stamp storage to the predeterminated position in internal memory；After primary processor has performed SMI handler corresponding to SMI interrupt, the counting of the 2nd TSC clocks is read as the second timestamp；Judge to perform whether the time is more than SMI maximum times corresponding to SMI interrupt；If so, then updating SMI maximum times, SMI cumulative times and the SMI triggering times in OEMACPI tables, and exit SMM；The present invention obtains the SMI execution time using TSC clocks, it is possible to reduce accesses delay, improves the accuracy of the SMI of acquisition execution time so that the parameter that operating system can store to OEMACPI tables parses, for weighing systematic function.
Description
Technical field
The present invention relates to Computer Applied Technology field, more particularly to a kind of method for weighing the system management interrupt time and
Device.
Background technology
X86 handled interrupt routine using INT x mode in the past, and interruption to be processed was more and more later, in order to allow
Design of hardware and software person is easier to design the interrupt routine for meeting demand, and CPU provides SMI (System Manager more
Interrupt, system management interrupt) and SMM (System Management Mode, SMM).In intel
A kind of 386, the intel 486 special operator schemes introduced, in such a mode, can perform APM, hardware
Control and operation OEM codes.It is fully transparent for operating system, that is to say, that operating system is not aware that CPU
When can enter and exit SMM.SMI is the unique channel into SMM, and SMI can be effective by the SMI# pins of processor
Or APIC (Advanced Program Interface Controller, Advanced Programmable Interrupt Controllers APICs) bus
SMI information.It is non-maskable interruption, independently of the interruption of other forms.It is designed to only use to system firmware, no
It is to application software or the use of in general system software.In SMM, CPU needs one piece of region of memory SMRAM (System
Management RAM, system management ram), CPU can store the value of register into SMRAM, then before SMM is entered
CPU can jump to system firmware SMI handler entrance and go to perform processing routine, and in general, system has multiple CPU, enters
After entering SMM, system firmware can choose a host CPU to perform main processing routine, and other CPU mosts of the time can all be in
Etc. the state of pending task, only host CPU notifies that other CPU can just be activated when performing task, is used after the completion of SMI processing
RSM instructions jump back to the old place and continued executing with, while recover the value of CPU registers.SMI points are in software interrupt and hardware
It is disconnected, i.e., produced to interrupt to produce to interrupt with external hardware with program setting and interrupted as CPU fault pins produce.
Because computer system hardware development is very fast, a system possesses increasing CPU so as at complete machine multitask
Rationality can be increased dramatically, but system firmware becomes more complicated using the SMI each CPU handled event, cost
Time is more, is so necessary to test SMI interrupt processing time so that whether measurement meets in hardware system development
System constraints and be unlikely to influence systematic function, for example, whether processing routine overtime, SMI interrupt frequency of use whether mistake
It is high.
In the prior art, it is to read to perform the first of SMI handler by ACPI timers to SMM diagnostic method
Time value, the second time value is read by ACPI timers again after SMI handler terminates, will recorded in internal memory the time difference
Method obtain system SMM time, but it is by I O read time counting, I O access to obtain the time by ACPI timers
There is certain time-delay, and ACPI timers are fixed frequency 3.579545MHz, it is not high enough to the precision of the data of acquisition, and
SMI time and frequency may influence operating system performance, and operating system of the prior art can not obtain corresponding data
It is subject to analyzing and diagnosing, therefore, how reduces access delay, improve the accuracy of the data of acquisition, obtain operating system
Corresponding data are subject to analyzing and diagnosing, are urgent problems now.
The content of the invention
It is an object of the invention to provide a kind of method and device for weighing the system management interrupt time, prolonged with reducing access
When, the accuracy of the data of acquisition is improved, operating system is obtained corresponding data and is subject to analyzing and diagnosing.
In order to solve the above technical problems, the present invention provides a kind of method for weighing the system management interrupt time, including：
After triggering SMI interrupt, the counting of the first TSC clocks is read into SMM processor at first, is stabbed as the very first time
Store the predeterminated position in internal memory；Wherein, when the first TSC clocks is enter the TSC in the processor of the SMM at first
Clock；
After primary processor has performed SMI handler corresponding to the SMI interrupt, the counting for reading the 2nd TSC clocks is made
For the second timestamp；Wherein, the primary processor is the processor chosen from the processor for entering the SMM, described
2nd TSC clocks are the TSC clocks in the primary processor；
The primary processor judges to perform whether the time is more than SMI maximum times corresponding to the SMI interrupt；Wherein, institute
It is that second timestamp subtracts the very first time stamp to state the execution time, and the SMI maximum times pre-set
Parameter in OEMACPI tables；
If it is not, then the SMI cumulative times in OEMACPI tables described in the main processor updates and SMI triggering times, and move back
Go out the SMM；
If so, when then the SMI maximum times in OEMACPI tables described in the main processor updates, the SMI are accumulative
Between and the SMI triggering times, and exit the SMM.
Optionally, trigger SMI interrupt after, at first into SMM processor read the first TSC clocks counting before, also
Including：
The OEMACPI tables are initialized in system starting process, and each parameter in the OEMACPI tables is each self-corresponding
Argument address informs that processor enters the SMI processing functions that the SMM is performed.
Optionally, when the SMI maximum times in OEMACPI tables described in the main processor updates, the SMI are accumulative
Between and the SMI triggering times, including：
The primary processor performs the SMI processing function, reads SMI maximum times, institute described in the OEMACPI tables
SMI cumulative times and each self-corresponding argument address of the SMI triggering times are stated, the SMI maximum times are updated to described
The time is performed, the SMI cumulative times are updated into the SMI cumulative times adds the execution time, and the SMI is triggered time
Number is updated to the SMI triggering times and adds 1.
Optionally, this method also includes：
Operating system software reads the OEMACPI tables, by the SMI maximum times and the SMI cumulative times when
Between unit conversion into the time；Wherein, the chronomere is specially tick, and the time is specially ms.
In addition, present invention also offers a kind of device for weighing the system management interrupt time, including：
Memory module, after triggering SMI interrupt, the counting of the first TSC clocks is read into SMM processor at first,
As very first time stamp storage to the predeterminated position in internal memory；Wherein, the first TSC clocks is at first into the SMM's
TSC clocks in processor；
Read module, after having performed SMI handler corresponding to the SMI interrupt for primary processor, read the 2nd TSC
The counting of clock is as the second timestamp；Wherein, the primary processor is one chosen from the processor for entering the SMM
Processor, the 2nd TSC clocks are the TSC clocks in the primary processor；
Judge module, judge to perform whether the time is more than SMI maximums corresponding to the SMI interrupt for the primary processor
Time；Wherein, the execution time is that second timestamp subtracts the very first time stamp, and the SMI maximum times are pre-
Parameter in the OEMACPI tables first set；
First update module, if being less than or equal to the SMI maximum times, the main process task for the execution time
Device updates SMI cumulative times and SMI triggering times in the OEMACPI tables, and exits the SMM；
Second update module, if being more than the SMI maximum times, the main processor updates for the execution time
The SMI maximum times, the SMI cumulative times and the SMI triggering times in the OEMACPI tables, and exit described
SMM。
Optionally, the device also includes：
Module is informed, for initializing the OEMACPI tables in system starting process, and will be each in the OEMACPI tables
Each self-corresponding argument address of parameter informs that processor enters the SMI processing functions that the SMM is performed.
Optionally, second update module, including：
Submodule is updated, the SMI processing function is performed for the primary processor, reads institute in the OEMACPI tables
SMI maximum times, the SMI cumulative times and each self-corresponding argument address of the SMI triggering times are stated, by the SMI most
The big time is updated to the execution time, when the SMI cumulative times being updated into the SMI cumulative times adding the execution
Between, the SMI triggering times are updated to the SMI triggering times and add 1.
Optionally, the device also includes：
Modular converter, the OEMACPI tables are read for operating system software, by the SMI maximum times and the SMI
The chronomere of cumulative time is converted into the time；Wherein, the chronomere is specially tick, and the time is specially ms.
A kind of method for weighing the system management interrupt time provided by the present invention, including：After triggering SMI interrupt, at first
Processor into SMM reads the counting of the first TSC clocks, as very first time stamp storage to the predeterminated position in internal memory；Its
In, the first TSC clocks is at first into the TSC clocks in SMM processor；Primary processor has performed SMI corresponding to SMI interrupt
After processing routine, the counting of the 2nd TSC clocks is read as the second timestamp；Wherein, primary processor is from the processing for entering SMM
The processor chosen in device, the 2nd TSC clocks are the TSC clocks in primary processor；Primary processor judges that SMI interrupt is corresponding
The execution time whether be more than SMI maximum times；Wherein, it is that the second timestamp subtracts very first time stamp to perform the time, and SMI is maximum
Time is the parameter in the OEMACPI tables pre-set；If it is not, then SMI cumulative times in main processor updates OEMACPI tables
With SMI triggering times, and SMM is exited；If so, when then the SMI maximum times in main processor updates OEMACPI tables, SMI are accumulative
Between and SMI triggering times, and exit SMM；
It can be seen that the present invention reads the meter of respective TSC clocks respectively by entering SMM processor and primary processor at first
Number, TSC clocks can be used to obtain the SMI execution time, because the frequency of TSC clocks is more than 2GHz, precision is higher, Er Qiefang
Ask that delay is small, it is possible to reduce access delay, improve the accuracy of the SMI of acquisition execution time；During by according to SMI execution
Between comparison with SMI maximum times, the parameter in OEMACPI tables can be updated so that operating system can pass through
OEMACPI tables obtain the parameter needed and analysis result is used for weighing systematic function.To be weighed in addition, present invention also offers one kind
The device of system management interrupt time, equally with above-mentioned beneficial effect.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
There is the required accompanying drawing used in technology description to be briefly described, it should be apparent that, drawings in the following description are only this
The embodiment of invention, for those of ordinary skill in the art, on the premise of not paying creative work, can also basis
The accompanying drawing of offer obtains other accompanying drawings.
A kind of flow chart of the method for measurement system management interrupt time that Fig. 1 is provided by the embodiment of the present invention；
A kind of OEMACPI tables of the method for measurement system management interrupt time that Fig. 2 is provided by the embodiment of the present invention
Schematic diagram；
A kind of structure chart of the device for measurement system management interrupt time that Fig. 3 is provided by the embodiment of the present invention.
Embodiment
To make the purpose, technical scheme and advantage of the embodiment of the present invention clearer, below in conjunction with the embodiment of the present invention
In accompanying drawing, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is
Part of the embodiment of the present invention, rather than whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art
The every other embodiment obtained under the premise of creative work is not made, belongs to the scope of protection of the invention.
It refer to Fig. 1, a kind of stream of the method for measurement system management interrupt time that Fig. 1 is provided by the embodiment of the present invention
Cheng Tu.This method can include：
Step 101：After triggering SMI interrupt, the counting of the first TSC clocks is read into SMM processor at first, is used as the
One timestamp is stored to the predeterminated position in internal memory；Wherein, when the first TSC clocks is enter the TSC in SMM processor at first
Clock.
It is understood that after triggering SMI interrupt, all processors (CPU) in system can go to SMI processing codes
Entrance performs SMI processing functions, that is, all processors can enter SMM, and performs SMI processing functions.This step can be with
Function is handled to enter SMI corresponding to SMM computing device at first, reads the countings of the TSC clocks of itself, during as first
Between stamp storage to the predeterminated position in internal memory, then can be without this step into SMM processor.
It should be noted that the predeterminated position in this step in the internal memory of very first time stamp storage, can be by designer
Voluntarily set according to practical scene and user's request, such as can be that SMI handles function in system starting process or system starts
A position in the internal memory voluntarily set afterwards, the present embodiment are unrestricted to this.
Specifically, due to very first time stamp is stored to the predeterminated position in internal memory, it is possible to reduce main process task in step 103
Device obtains the time of very first time stamp, so as to reduce the execution time of SMI processing functions, will stab storage the very first time and arrive such as hard disk
Other positions, the purpose of the present embodiment can also be reached, the present embodiment is unrestricted to this.
Step 102：After primary processor has performed SMI handler corresponding to SMI interrupt, the meter of the 2nd TSC clocks is read
Number is used as the second timestamp；Wherein, primary processor is a processor choosing from the processor for entering SMM, during two TSC
Clock is the TSC clocks in primary processor.
It is understood that primary processor can be the processor chosen from the processor for fully enter SMM, it is right
In primary processor specific selection and perform SMI interrupt corresponding to SMI handler process, can use and prior art phase
As mode realize, other modes can also be used to realize that the present embodiment not do any restrictions to this.
Specifically, can also include choosing host CPU in this step and perform SMI handler corresponding to SMI interrupt, other
CPU waits host CPU to complete SMI task, prepares to exit SMM process.
It should be noted that because host CPU is the CPU that last exits SMM, so the method that the present embodiment is provided
The counting of the TSC clocks of itself is read before SMI is exited using host CPU, as the second timestamp.By institute in a system
It is all synchronous error very little to have the respective TSC of CPU, and different CPU TSC counting can be used to calculate corresponding to SMI interrupt
Perform the time.
Step 103：Primary processor judges to perform whether the time is more than SMI maximum times corresponding to SMI interrupt；If it is not, then
Into step 104；If so, then enter step 105.
Wherein, it is that the second timestamp subtracts very first time stamp to perform the time, and SMI maximum times pre-set
Parameter in OEMACPI tables.
It is understood that SMI interrupt corresponding to perform the time can be primary processor by the second timestamp of reading with
The very first time stamp read from the predeterminated position in internal memory subtracts each other, the numerical value of acquisition.SMI maximum times can be primary processor from
The numerical value that argument address corresponding to SMI maximum times obtains in OEMACPI tables；Corresponding, this step can also include main process task
Device performs SMI processing functions, obtains the step of time and SMI maximum times are performed corresponding to SMI interrupt.The present embodiment to this not
It is restricted.
Specifically, for the particular content in OEMACPI tables, SMI maximum times can be included as shown in Figure 2, SMI adds up
Time and SMI triggering times these three parameters, one or two parameter that may also be included in which can be with other specification, this
Embodiment does not do any restrictions to this.
It should be noted that the OEMACPI tables that system firmware can initialize in system starting process, including definition
SMI maximum times, SMI triggering times, these three parameters of SMI cumulative times etc., while can inform that SMI handles the above-mentioned ginseng of function
Argument address corresponding to number, when handling function to facilitate primary processor to perform SMI, it can directly access parameter and reduce SMI processing
The execution time of function, do clear operation before operating system is entered afterwards.
Corresponding, the method that the present embodiment is provided can also include：The OEMACPI is initialized in system starting process
Table, and each self-corresponding argument address of each parameter in the OEMACPI tables is informed that processor enters the SMI that the SMM is performed
The step of handling function.The present embodiment does not do any restrictions to this.
Step 104：SMI cumulative times and SMI triggering times in main processor updates OEMACPI tables, and exit SMM.
It is understood that when if the SMI maximums that the time is not more than in OEMACPI tables are performed corresponding to this SMI interrupt
Between, then primary processor can not update the SMI maximum times in OEMACPI tables, but the SMI only updated in OEMACPI tables tires out
With SMI triggering times between timing, as in this step, primary processor can perform SMI processing functions, read SMI in OEMACPI tables
Cumulative time and each self-corresponding argument address of SMI triggering times, the SMI cumulative times are updated to the SMI cumulative times and add this
The time is performed corresponding to SMI interrupt, SMI triggering times are updated into SMI triggering times adds 1, and completes backed off after random in renewal
SMM。
As long as specifically, in this step primary processor can with the SMI cumulative times in OEMACPI tables and SMI triggering times,
For specific renewal process, can voluntarily be set by designer, the present embodiment does not do any restrictions to this.
Step 105：SMI maximum times, SMI cumulative times and SMI triggerings time in main processor updates OEMACPI tables
Number, and exit SMM.
If it is understood that this SMI interrupt corresponding to perform the time be more than OEMACPI tables in SMI maximum times,
Then primary processor can update SMI maximum times, SMI cumulative times and the SMI triggering times in OEMACPI tables, such as this step
In, primary processor can perform SMI processing functions, read SMI maximum times, SMI cumulative times and SMI in OEMACPI tables and touch
Each self-corresponding argument address of number is sent out, SMI maximum times are updated to perform the time corresponding to this SMI interrupt, SMI is tired out
Being updated to the SMI cumulative times between timing adds the time is performed corresponding to this SMI interrupt, and SMI triggering times are updated into SMI triggerings
Number adds 1, and completes backed off after random SMM in renewal.
As long as specifically, in this step primary processor can with the SMI maximum times in OEMACPI tables, the SMI cumulative times and
SMI triggering times, for specific renewal process, can voluntarily it be set by designer, the present embodiment does not do any limit to this
System.
It should be noted that in order to reduce the time that primary processor performs SMI processing functions, SMM is exited as early as possible, therefore,
The method that the present embodiment is provided does not add excessive diagnosis content, that is, does not add main place in SMI handles function
Reason device needs other operations carried out.The whole that can be performed if necessary to more diagnosis contents by system serially printing SMI
Content includes the SMI execution time, and whether the printing SMI execution times exceed the warning message of setting, are believed by serial ports
Breath record queries system is in SMI concrete operations.The present embodiment does not do any restrictions to this.
Further, corresponding parameter in OEMACPI tables can be obtained in order to facilitate operating system and be subject to analyzing and diagnosing, this
The method that embodiment is provided can also include operating system software and read OEMACPI tables, and SMI maximum times and SMI are added up
The step of chronomere (tick) of time is converted into time (ms)；, can for the particular type and content of operating system software
Voluntarily to be set by designer, the present embodiment does not do any restrictions to this.Likewise, operating system software is not utilized by SMI
The chronomere of maximum time and SMI cumulative times are converted into the time, but are updating the mistake of OEMACPI tables by primary processor
The chronomere of SMI maximum times and SMI cumulative times are converted into the time in journey, the purpose of this step can also be reached, this
Embodiment does not do any restrictions equally to this.
In the present embodiment, the embodiment of the present invention is read each respectively by the processor and primary processor at first into SMM
TSC clocks counting, TSC clocks can be used to obtain the SMI execution time, it is smart because the frequency of TSC clocks is more than 2GHz
Degree is higher, and it is small to access delay, it is possible to reduce accesses delay, improves the accuracy of the SMI of acquisition execution time；Pass through root
According to the SMI comparison for performing time and SMI maximum times, the parameter in OEMACPI tables can be updated so that operation system
System can obtain the parameter needed by OEMACPI tables and analysis result is used for weighing systematic function.
It refer to Fig. 3, a kind of knot of the device for measurement system management interrupt time that Fig. 3 is provided by the embodiment of the present invention
Composition.The device can include：
Memory module 100, after triggering SMI interrupt, read the meter of the first TSC clocks into SMM processor at first
Number, as very first time stamp storage to the predeterminated position in internal memory；Wherein, the first TSC clocks is at first into SMM processors
In TSC clocks；
Read module 200, after having performed SMI handler corresponding to SMI interrupt for primary processor, read the 2nd TSC
The counting of clock is as the second timestamp；Wherein, primary processor is the processor chosen from the processor for entering SMM,
2nd TSC clocks are the TSC clocks in primary processor；
Judge module 300, judge to perform whether the time is more than SMI maximum times corresponding to SMI interrupt for primary processor；
Wherein, it is that the second timestamp subtracts very first time stamp to perform the time, and SMI maximum times are in the OEMACPI tables pre-set
Parameter；
First update module 400, if being less than or equal to SMI maximum times, main processor updates for performing the time
SMI cumulative times and SMI triggering times in OEMACPI tables, and exit SMM；
Second update module 500, if being more than SMI maximum times, main processor updates OEMACPI tables for performing the time
In SMI maximum times, SMI cumulative times and SMI triggering times, and exit SMM.
Optionally, the device can also include：
Module is informed, for initializing OEMACPI tables in system starting process, and by each parameter in OEMACPI tables each
Corresponding argument address informs that processor enters the SMI processing functions that SMM is performed.
Optionally, the second update module 500, can include：
Submodule is updated, SMI processing functions is performed for primary processor, reads SMI maximum times, SMI in OEMACPI tables
Cumulative time and each self-corresponding argument address of SMI triggering times, SMI maximum times are updated to perform the time, SMI is added up
Time be updated to the SMI cumulative times add perform the time, SMI triggering times are updated to SMI triggering times and add 1.
Optionally, the device can also include：
Modular converter, OEMACPI tables are read for operating system software, by SMI maximum times and SMI cumulative times when
Between unit conversion into the time；Wherein, chronomere is specially tick, and the time is specially ms.
In the present embodiment, the embodiment of the present invention is by memory module 100 and read module 200 using at first into SMM's
Processor and primary processor read the counting of respective TSC clocks respectively, and TSC clocks can be used to obtain the SMI execution time,
Because the frequency of TSC clocks is more than 2GHz, precision is higher, and it is small to access delay, it is possible to reduce accesses delay, improves acquisition
The accuracy of SMI execution time；The comparison for performing time and SMI maximum times by judge module 300 according to SMI, can
To be updated using the first update module 400 or the second update module 500 to the parameter in OEMACPI tables so that operation system
System can obtain the parameter needed by OEMACPI tables and analysis result is used for weighing systematic function.
Each embodiment is described by the way of progressive in specification, and what each embodiment stressed is and other realities
Apply the difference of example, between each embodiment identical similar portion mutually referring to.For device disclosed in embodiment
Speech, because it is corresponded to the method disclosed in Example, so description is fairly simple, related part is referring to method part illustration
.
Professional further appreciates that, with reference to the unit of each example of the embodiments described herein description
And algorithm steps, can be realized with electronic hardware, computer software or the combination of the two, in order to clearly demonstrate hardware and
The interchangeability of software, the composition and step of each example are generally described according to function in the above description.These
Function is performed with hardware or software mode actually, application-specific and design constraint depending on technical scheme.Specialty
Technical staff can realize described function using distinct methods to each specific application, but this realization should not
Think beyond the scope of this invention.
Directly it can be held with reference to the step of method or algorithm that the embodiments described herein describes with hardware, processor
Capable software module, or the two combination are implemented.Software module can be placed in random access memory (RAM), internal memory, read-only deposit
Reservoir (ROM), electrically programmable ROM, electrically erasable ROM, register, hard disk, moveable magnetic disc, CD-ROM or technology
In any other form of storage medium well known in field.
Detailed Jie has been carried out to a kind of method and device for weighing the system management interrupt time provided by the present invention above
Continue.Specific case used herein is set forth to the principle and embodiment of the present invention, and the explanation of above example is only
It is the method and its core concept for being used to help understand the present invention.It should be pointed out that for those skilled in the art
For, under the premise without departing from the principles of the invention, some improvement and modification can also be carried out to the present invention, these improve and repaiied
Decorations are also fallen into the protection domain of the claims in the present invention.
Claims (8)
- A kind of 1. method for weighing the system management interrupt time, it is characterised in that including：After triggering SMI interrupt, the counting of the first TSC clocks is read into SMM processor at first, stabs and stores as the very first time Predeterminated position into internal memory；Wherein, the first TSC clocks is at first into the TSC clocks in the processor of the SMM；After primary processor has performed SMI handler corresponding to the SMI interrupt, the counting for reading the 2nd TSC clocks is used as the Two timestamps；Wherein, the primary processor is a processor choosing from the processor for entering the SMM, described second TSC clocks are the TSC clocks in the primary processor；The primary processor judges to perform whether the time is more than SMI maximum times corresponding to the SMI interrupt；Wherein, it is described to hold The row time is that second timestamp subtracts the very first time stamp, and the SMI maximum times are the OEMACPI tables pre-set In parameter；If it is not, then the SMI cumulative times in OEMACPI tables described in the main processor updates and SMI triggering times, and exit institute State SMM；If so, then the SMI maximum times in OEMACPI tables described in the main processor updates, the SMI cumulative times and The SMI triggering times, and exit the SMM.
- 2. the method according to claim 1 for weighing the system management interrupt time, it is characterised in that after triggering SMI interrupt, Enter at first before the SMM counting of processor the first TSC clocks of reading, in addition to：Initialize the OEMACPI tables in system starting process, and by each self-corresponding parameter of each parameter in the OEMACPI tables Inform that processor enters the SMI processing functions that the SMM is performed in address.
- 3. the method according to claim 2 for weighing the system management interrupt time, it is characterised in that the primary processor is more The SMI maximum times, the SMI cumulative times and the SMI triggering times in the new OEMACPI tables, including：The primary processor performs the SMI processing function, reads SMI maximum times described in the OEMACPI tables, described SMI cumulative times and each self-corresponding argument address of the SMI triggering times, the SMI maximum times are updated to described hold The row time, the SMI cumulative times are updated to the SMI cumulative times and add the execution time, by the SMI triggering times It is updated to the SMI triggering times and adds 1.
- 4. the method for the measurement system management interrupt time according to any one of claims 1 to 3, it is characterised in that also wrap Include：Operating system software reads the OEMACPI tables, and the time of the SMI maximum times and the SMI cumulative times is single Position is converted into the time；Wherein, the chronomere is specially tick, and the time is specially ms.
- A kind of 5. device for weighing the system management interrupt time, it is characterised in that including：Memory module, after triggering SMI interrupt, the counting of the first TSC clocks is read into SMM processor at first, as Very first time stamp is stored to the predeterminated position in internal memory；Wherein, the first TSC clocks is at first into the processing of the SMM TSC clocks in device；Read module, after having performed SMI handler corresponding to the SMI interrupt for primary processor, read the 2nd TSC clocks Counting as the second timestamp；Wherein, the primary processor is the processing chosen from the processor for entering the SMM Device, the 2nd TSC clocks are the TSC clocks in the primary processor；Judge module, when judging whether perform the time corresponding to the SMI interrupt is more than SMI maximums for the primary processor Between；Wherein, the execution time is that second timestamp subtracts the very first time stamp, and the SMI maximum times are advance Parameter in the OEMACPI tables of setting；First update module, if being less than or equal to the SMI maximum times for the execution time, the primary processor is more SMI cumulative times and SMI triggering times in the new OEMACPI tables, and exit the SMM；Second update module, if being more than the SMI maximum times for the execution time, described in the main processor updates The SMI maximum times, the SMI cumulative times and the SMI triggering times in OEMACPI tables, and exit the SMM.
- 6. the device according to claim 5 for weighing the system management interrupt time, it is characterised in that also include：Module is informed, for initializing the OEMACPI tables in system starting process, and by each parameter in the OEMACPI tables Each self-corresponding argument address informs that processor enters the SMI processing functions that the SMM is performed.
- 7. the device according to claim 6 for weighing the system management interrupt time, it is characterised in that the second renewal mould Block, including：Submodule is updated, the SMI processing function is performed for the primary processor, reads SMI described in the OEMACPI tables Maximum time, the SMI cumulative times and each self-corresponding argument address of the SMI triggering times, by the SMI maximum times The execution time is updated to, the SMI cumulative times are updated into the SMI cumulative times adds the execution time, by institute State SMI triggering times and be updated to the SMI triggering times and add 1.
- 8. the device of the measurement system management interrupt time according to any one of claim 5 to 7, it is characterised in that also wrap Include：Modular converter, the OEMACPI tables are read for operating system software, the SMI maximum times and the SMI are added up The chronomere of time is converted into the time；Wherein, the chronomere is specially tick, and the time is specially ms.
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