CN107170671A - A kind of GaN power devices and its manufacture method based on ion implanting - Google Patents

A kind of GaN power devices and its manufacture method based on ion implanting Download PDF

Info

Publication number
CN107170671A
CN107170671A CN201710483029.3A CN201710483029A CN107170671A CN 107170671 A CN107170671 A CN 107170671A CN 201710483029 A CN201710483029 A CN 201710483029A CN 107170671 A CN107170671 A CN 107170671A
Authority
CN
China
Prior art keywords
gan
power devices
potential barrier
cushions
ion implanting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201710483029.3A
Other languages
Chinese (zh)
Inventor
任远
陈志涛
刘晓燕
刘宁炀
刘久澄
李叶林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Guangdong Semiconductor Industry Technology Research Institute
Original Assignee
Guangdong Semiconductor Industry Technology Research Institute
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Guangdong Semiconductor Industry Technology Research Institute filed Critical Guangdong Semiconductor Industry Technology Research Institute
Priority to CN201710483029.3A priority Critical patent/CN107170671A/en
Publication of CN107170671A publication Critical patent/CN107170671A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/452—Ohmic electrodes on AIII-BV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/47—Schottky barrier electrodes
    • H01L29/475—Schottky barrier electrodes on AIII-BV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
    • H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Manufacturing & Machinery (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

A kind of GaN power devices and its manufacture method based on ion implanting, including the GaN cushions set gradually from lower to upper, GaN channel layers and AlGaN potential barrier, active electrode is set in the AlGaN potential barrier, gate electrode and drain electrode, wherein described source electrode and drain electrode are Ohmic contact, the gate electrode is Schottky contacts, and covered with the passivation layer being connected with AlGaN potential barrier between each electrode, the AlGaN potential barrier is formed with for heterojunction structure and due to polarity effect the two-dimensional electron gas for the conducting channel that laterally worked as GaN power devices with GaN channel layers in both interfaces, ion isolated area is formed with by the underrun ion implanting of GaN cushions in the GaN cushions, the ion isolated area is located at the top of GaN cushions and is connected with GaN channel layers, and there is provided being bonded with high heat conduction substrate in the bottom surface of GaN cushions after ion isolated area in the GaN cushions.The present invention keeps apart GaN raceway grooves with GaN cushions, so as to reduce device creepage and improve breakdown voltage due to being formed with isolated area by ion implanting using in GaN cushions.

Description

A kind of GaN power devices and its manufacture method based on ion implanting
Technical field
The present invention relates to field of semiconductor devices, be specifically related to a kind of GaN power devices based on ion implanting and its Manufacture method.
Background technology
As the representative of third generation semiconductor material with wide forbidden band, GaN be after the first generation using Si, Ge as representative and with After GaAs, InP is the second generation semi-conducting materials of representative, the novel semiconductor material grown up over nearly twenty or thirty year. GaN material has critical breakdown strength height, energy gap is big, carrier mobility is high, saturated electron drift velocity is high, thermal conductivity The features such as big, possess the incomparable advantage of traditional Si material, be very suitable for making high temperature (more than 300 DEG C), it is high-power, Low-loss power electronic devices, miniaturization, lightweight and the cost degradation of feasible system, and system drive energy can improved Make system more energy-efficient in the case of power.
Although GaN bases power electronic devices achieves huge progress in recent years, but still is faced with some key technologies Problem, such as power device are pressure-resistant relatively low, OFF leakage current is larger, poor reliability.At present, adopted ripe GaN power devices more It is operated with cross conduction, the two-dimensional electron gas that polarity effect is formed between AlGaN potential barrier and GaN channel layers is as leading Electric raceway groove.Need to deposit one layer of GaN cushion before growth GaN channel layers, for improving quality of materials, reduce dislocation, increase Strong insulating properties, realizes more preferable raceway groove shut-off.
At present, the device electric breakdown strength of report is also much smaller than the theoretical limit of GaN material.One main cause is that electric current leads to Cross dislocation or defect enters GaN cushions even growth substrates and causes puncturing in advance for device.Raising is pressure-resistant can be by high-quality Extension and increase GaN cushioning layer materials thickness and realize, but Material growth uses metal organic chemical vapor deposition, deposition Speed is slow, and production cost is very high, and growth conditions regulation and control are complicated.The method that another raising is pressure-resistant is that GaN cushions are carried out Acceptor doping, by introducing a certain amount of acceptor impurity in GaN body materials, to compensate the electronics of surplus, so as to reduce body Material leaks electricity, and improves breakdown voltage.But these acceptor impurities can cause device reliability to reduce, dynamic characteristic is deteriorated.
The problem of existing for these, all expands a series of research both at home and abroad, by remove leakage path or Cushion is changed into resistive formation to improve device performance.
Belgian Puneet Srivastava et al. employ Si substrate portions and peel off scheme, are shelled by selection region From Si substrates, the breakdown characteristics of device are effectively improved, the breakdown voltage for the device that grid leak spacing is 20 μm is reached Significant 2200 V [55].But, selective substrate desquamation technical matters is complicated, difficulty greatly, add element manufacturing into This.Moreover, after Si substrate desquamations, its thermal conductivity is also deteriorated, heating can not be suitable for big clearly under high power work The preparation of power device（Bibliography：Srivastava P, Das J, Visalli D, et al. Record Breakdown Voltage (2200 V) of GaN DHFETs on Si With 2-$\ mu\ hbox {m} $ Buffer Thickness by Local Substrate Removal[J]. IEEE Electron Device Letters, 2011, 32(1): 30-32.）.
Shichuang Sun of the Central China University of Science and Technology et al. are prepared for AlGaN/GaN metal-insulators by Al ion implantings Layer semiconductor HEMT, they are grown GaN cushions, carried out using Al ion implantings on a si substrate first Insulating processing, then prepares GaN channel layers and AlGaN potential barrier by diauxic growth.Compared using the device of ion implanting Control group, OFF leakage current reduces 3 times, while breakdown voltage improves 6 times.However, its ion implanting can cause injection to damage Wound, can cause the quality of Material growth to deteriorate in secondary epitaxy, and a series of processing to sample in addition are also possible to introduce dirty Dye（Bibliography：Sun S, Fu K, Yu G, et al. AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors with reduced leakage current and enhanced breakdown voltage using aluminum ion implantation[J]. Applied Physics Letters, 2016, 108(1): 013507.）.
The content of the invention
It is an object of the invention to for it is above-mentioned exist problem and shortage there is provided a kind of structure it is novel, suppress leakage current, hit Wear voltage high GaN power devices and its manufacture method based on ion implanting.
The technical proposal of the invention is realized in this way：
GaN power devices of the present invention based on ion implanting, are characterized in：Including the GaN set gradually from lower to upper Active electrode, gate electrode and drain electrode are set in cushion, GaN channel layers and AlGaN potential barrier, the AlGaN potential barrier, its Described in source electrode and drain electrode be Ohmic contact, the gate electrode be between Schottky contacts, and each electrode covered with The passivation layer that AlGaN potential barrier is connected, the AlGaN potential barrier is heterojunction structure and the interface at both with GaN channel layers Place is formed with the two-dimensional electron gas for the conducting channel that laterally worked as GaN power devices, the GaN bufferings due to polarity effect Ion isolated area is formed with by the underrun ion implanting of GaN cushions in layer, the ion isolated area is located at GaN cushions Top and be connected with GaN channel layers, and in the GaN cushions be provided with ion isolated area after in GaN cushions Bottom surface is bonded with high heat conduction substrate.
The manufacture method of GaN power devices of the present invention based on ion implanting, is characterized in comprising the following steps：
1. using Metalorganic Chemical Vapor Deposition in growth substrates epitaxial growth GaN cushions, GaN channel layers successively And AlGaN potential barrier；
2. using ultraviolet photolithographic preparation first time mask in AlGaN potential barrier, the pattern etched as active region mesa, and Mesa etch is carried out using dry etch process to realize discrete GaN power devices, and etching depth is 50nm~200nm；
3. the metal of second of mask preparation, evaporation source electrode and drain electrode is carried out in AlGaN potential barrier by photoetching, and Ultrasound is carried out to metal-stripping using organic solvent, obtains the metallic pattern of source electrode and drain electrode, and pass through rapid thermal annealing Technique realizes the Ohmic contact of source electrode and drain electrode and AlGaN potential barrier；
4. deposit thickness is 50nm~500nm passivation layer on the surface of AlGaN potential barrier, and using optical graving for mask, Source electrode window, drain electrode window and grid groove are etched over the passivation layer；
5. the metal for forming gate electrode, and gate electrode and AlGaN potential barrier formation Schottky contacts are deposited in grid groove；
6. one layer of insulating barrier for covering source electrode, drain electrode and gate electrode is prepared on the surface of passivation layer as interim to turn Move layer；
7. growth substrates are removed, expose the bottom surface of GaN cushions, and from the underrun ion implanting of GaN cushions Form the ion isolated area of a high resistant in GaN cushions, and the ion isolated area be located at GaN cushions top and with GaN ditches Channel layer is connected；
8. one layer of bonding material is grown on the bottom surface of GaN cushions, and high heat conduction is bonded with by this layer of bonding material and is served as a contrast Bottom；
9. interim transfer layer is removed, the preparation of whole GaN power devices is completed.
Wherein, the present invention first can carry out surface clean, then carry out after above-mentioned steps are carried out 1. to AlGaN potential barrier 2., its cleaning way is to be cleaned by ultrasonic 5 minutes in acetone and aqueous isopropanol respectively to above-mentioned steps, then in sulfuric acid and dioxygen Each immersion 10 minutes in water mixed solution and pure hydrochloric acid, and dried up in deionized water after rinsing with nitrogen, dried using hot plate The moisture of dry remained on surface.
The metal of the source electrode and drain electrode is selected from one or more of combinations in Ti, Al, Mo, Au, Ni, W Or their alloy, thickness is 50~200 nm, and rapid thermal anneal process is to carry out in a nitrogen environment, and treatment temperature is 700~950 DEG C.
The passivation layer selection deposits the SiN prepared by PECVD, LPCVD, ALD or Sputterx、SiO2、SiNO、 Al2O3, one or more in AlN.
One or more of combinations of the metal of the gate electrode in Ni, Au, Pt, Al, TiW, TiN, thickness is 50 ~200nm.
The bonding material is one or more of combination in Au, Sn, In, Ti, Ni, Pt, Pb or their alloy.
The temperature of the bonding is 200~350 DEG C, and pressure is 0~5000 Kg.
The high heat conduction substrate is the good silicon or copper or carborundum or ceramics of thermal conductance.
The method for removing growth substrates is laser lift-off, light assisted electrochemical method etch, wet etching method, ground One or more of combinations in mill method, polishing processes, ICP/RIE dry etching methods.
The ion implanting is to use one or more elements in Fe, C, B, Zn, Al, and use 20KeV~ 150KeV energy is injected, and implantation dosage is 1012~1016/cm2。
Ion implantation technology of the present invention can form deep energy level in GaN material, and GaN cushions are changed into The good highly resistant material of insulating properties, realizes resistivity ＞ 108Ω cm, so as to suppress body material leakage current, while improving device The breakdown voltage of part.Compared with prior art, the present invention has following remarkable advantage：
1st, GaN cushions are changed into resistive formation by the present invention by ion implanting, reduce the electric leakage that device passes through GaN cushions, Improve breakdown voltage；
2nd, compared with improving the method for dislocation density using epitaxial growth, the present invention need not be deposited using the technique of ion implanting Thicker GaN cushions, reduce material gross thickness, shorten growth time, while saving production cost；
3rd, the repeatability for the ion implanting mode that the present invention is used is high, accurately controls dosage and depth, can using different ions The material insulation property of particular requirement is obtained, practicality is extensive；
4th, the present invention is using dorsal part ion implanting by the way of, it is to avoid conventional face injects the damage to barrier layer and channel layer Wound；
5th, the present invention has completely cut off substrate leakage current by substrate desquamation, while the novel heat-conducting substrate of bonding can greatly improve device Part heat dissipation characteristics, can preferably support high power, the high voltage applications of GaN power devices.
The present invention is further illustrated below in conjunction with the accompanying drawings.
Brief description of the drawings
Fig. 1 is the structural representation of device of the present invention.
Fig. 2 manufactures the process chart of the device for the present invention.
Embodiment
As shown in figure 1, the GaN power devices of the present invention based on ion implanting, including set gradually from lower to upper GaN cushions 2, GaN channel layers 3 and AlGaN potential barrier 4, active electrode 5, gate electrode 8 are set in the AlGaN potential barrier 4 With drain electrode 6, wherein the source electrode 5 and drain electrode 6 are Ohmic contact, the gate electrode 8 is Schottky contacts, and each electricity Covered with the passivation layer 7 being connected with AlGaN potential barrier 4 between pole, the AlGaN potential barrier 4 and GaN channel layers 3 are heterogeneous Structure and the two dimension for being formed with the conducting channel that laterally worked as GaN power devices due to polarity effect in both interfaces Ion isolated area 10 is formed with by the underrun ion implanting of GaN cushions 2 in electron gas, the GaN cushions 2, it is described Ion isolated area 10 is located at the top of GaN cushions 2 and is connected with GaN channel layers 3, and is provided with the GaN cushions 2 After ion isolated area 10 high heat conduction substrate 11 is bonded with the bottom surface of GaN cushions 2.Wherein, high heat conduction substrate 11 is insulation Property and the good material of heat conductivility, for improve GaN power devices backward voltage and improve heat dissipation problem；The source electrode 5th, gate electrode 8 and drain electrode 6 are used to control being switched on and off for GaN power devices；The passivation layer 7 is using chemically or physically High-quality thin film prepared by depositional mode, for reducing semiconductor-interface-state, is reduced between source electrode and drain electrode and gate electrode Leakage current；The ion isolated area 10 is used to form electric isolation to reduce the leakage current by cushion and substrate conduction.
As shown in Fig. 2 the manufacture method of the GaN power devices of the present invention based on ion implanting, including following step Suddenly：
1. using Metalorganic Chemical Vapor Deposition in growth substrates 1 epitaxial growth GaN cushions 2, GaN raceway grooves successively Layer 3 and AlGaN potential barrier 4；
2. using ultraviolet photolithographic preparation first time mask in AlGaN potential barrier 4, the pattern etched as active region mesa, and Mesa etch is carried out using dry etch process to realize discrete GaN power devices, and etching depth is 50nm~200nm；
3. the metal of second of mask preparation, evaporation source electrode and drain electrode, source are carried out in AlGaN potential barrier 4 by photoetching The metal of electrode and drain electrode is selected from one or more of combinations or their alloy in Ti, Al, Mo, Au, Ni, W, Thickness is 50~200 nm, and carries out ultrasound to metal-stripping using organic solvent, obtains the metal of source electrode 5 and drain electrode 6 Figure, and source electrode 5 and drain electrode 6 and the Ohmic contact of AlGaN potential barrier 4, fast speed heat are realized by rapid thermal anneal process Annealing process is to carry out in a nitrogen environment, and treatment temperature is 700~950 DEG C；
4. on the surface of AlGaN potential barrier 4 deposit thickness be 50nm~500nm passivation layer 7, passivation layer selection by SiN prepared by PECVD, LPCVD, ALD or Sputter depositionx、SiO2、SiNO、Al2O3, one or more in AlN, and make With optical graving for mask, source electrode window, drain electrode window and grid groove are etched on passivation layer 7；
5. the metal for forming gate electrode 8 is deposited in grid groove, the metal of gate electrode is selected from Ni, Au, Pt, Al, TiW, TiN In one or more of combinations, thickness is 50~200nm, and gate electrode 8 and AlGaN potential barrier 4 formation Schottky contacts；
6. one layer of insulating barrier for covering source electrode 5, drain electrode 6 and gate electrode 8 is prepared on the surface of passivation layer 7 as facing When transfer layer 9；
7. done using laser lift-off, light assisted electrochemical method etch, wet etching method, polishing, polishing processes, ICP/RIE One or more of combinations in method etching method remove growth substrates 1, expose the bottom surface of GaN cushions 2, and from GaN cushions 2 Underrun ion implanting and the ion isolated area 10 of a high resistant is formed in GaN cushions 2, ion implanting be using Fe, One or more elements in C, B, Zn, Al, and injected using 20KeV~150KeV energy, implantation dosage is 1012~1016/cm2, and the ion isolated area 10 be located at GaN cushions 2 top and be connected with GaN channel layers 3；
8. one layer of bonding material is grown on the bottom surface of GaN cushions 2, bonding material is in Au, Sn, In, Ti, Ni, Pt, Pb One or more of combinations or their alloy, and high heat conduction substrate 11, the temperature of bonding are bonded with by this layer of bonding material Spend for 200~350 DEG C, pressure is 0~5000 Kg, and high heat conduction substrate is the good silicon or copper or carborundum or ceramics of thermal conductance；
9. interim transfer layer 9 is removed, the preparation of whole GaN power devices is completed.
In order to further improve the quality of the present invention, the present invention, can be first to AlGaN potential barriers after above-mentioned steps are carried out 1. Layer 4 carries out surface clean, then carries out above-mentioned steps 2., and its cleaning way is to be cleaned by ultrasonic respectively in acetone and aqueous isopropanol 5 minutes, then each immersion 10 minutes in sulfuric acid and hydrogen peroxide mixed solution and pure hydrochloric acid, and in deionized water after rinsing Dried up with nitrogen, the moisture of remained on surface is dried using hot plate.
Below by specific embodiment, the present invention is further illustrated.
Embodiment one：
Case study on implementation of the present invention provides a kind of manufacture method of the GaN power devices based on ion implanting, and it includes following step Suddenly：
Step 1）, grow GaN cushions, GaN channel layers successively using equipment of metal organic chemical vapor deposition on a silicon substrate And AlGaN potential barrier, epitaxial growth temperature is between 950 DEG C to 1350 DEG C；
Step 2）, the AlGaN/GaN samples grown on silicon substrate are subjected to surface clean, specific method is：Respectively in acetone and It is cleaned by ultrasonic in aqueous isopropanol 5 minutes, it is then each in sulfuric acid and hydrogen peroxide mixed solution and pure hydrochloric acid to soak 10 minutes, And dried up after rinsing in deionized water with nitrogen, the moisture of remained on surface is dried using hot plate；
Step 3）, in AlGaN potential barrier using Conventional UV photoetching process prepare photoresist mask, carved as active region mesa The pattern of erosion, and mesa etch is carried out using dry etch process, remove the AlGaN potential barrier and part GaN ditches of subregion Channel layer, to realize discrete GaN power devices, specific etching mode is sense coupling（ICP）, use Cl2/BCl3/ Ar is as working gas, and ICP power is 250W, and RF power is 400W, and etching depth is 50nm~200nm；
Step 4）, second of mask preparation is carried out in AlGaN potential barrier by photoetching, use electron beam evaporation plating machine evaporation multilayer Metal Ti/Al/Ni/Au, thickness is respectively 20/150/50/80 nm, carries out ultrasound to metal-stripping using organic solvent, obtains The metallic pattern of source electrode and drain electrode, and realize by rapid thermal anneal process the Ohmic contact of metal and semiconductor, alloy Change processing is carried out in a nitrogen environment, and treatment temperature is 850 degrees Celsius, and the time is 30s；
Step 5）, use plasma enhanced chemical vapor deposition equipment（PECVD）In the upper surface deposition of thick of GaN power devices Spend the SiO for 100nm2As passivation layer, depositing temperature is 300 DEG C, and the working gas used is N2O、N2、5%SiH4/N2, and lead to Optical graving is crossed for mask, source electrode window, drain electrode window and grid groove is etched over the passivation layer using wet corrosion technique, had The etchant solution of body is BOE, and etching time is 30s；
Step 6）, deposit in grid groove metal for forming gate electrode, the metal of gate electrode uses Ni/Au double-level-metals, thick Degree is respectively 20/200nm, carries out ultrasound to metal-stripping using organic solvent, obtains the metallic pattern of gate electrode, and gate electrode With AlGaN potential barrier formation Schottky contacts；
Step 7）, spin coating uv-curable glue covering passivation layer, source electrode, the upper surface of drain electrode and gate electrode be used as interim transfer Layer, is solidified using ultraviolet exposure machine irradiation 30min；
Step 8）, the silicon substrate for epitaxial growth removed using wet etching, be specifically that sample is immersed in HF solution to delay Slowly Si substrates are eroded；And it is laminated in the GaN bufferings exposed, by ion implanting, formation one is high in GaN cushions The ion isolated area of resistance, and the ion isolated area is to be located at GaN cushions close to the side of GaN channel layers, ion implanting uses B+Ion, injection isolation is carried out using 110 KeV energy, and implantation dosage is 5 × 1015 cm2；
Step 9）, one layer of bonding material is grown on the face that GaN cushions expose, and pottery is bonded with by this layer of bonding material Ceramic material is used as high heat conduction substrate；Specifically, bonding material is using one kind in the metals such as gold, tin, indium, titanium, lead, nickel, platinum, titanium Or several combinations or their alloy, it is preferable that bonding material is used using gold-tin alloy and golden indium alloy, and bonding technology Temperature be 200-350 DEG C, pressure be 0-5000 Kg；
Step 10）, sample is immersed in glue-dispenser 30 minutes, be heated to 80 DEG C, remove interim transfer layer, complete whole GaN The preparation of power device.
Embodiment two：
The difference of the embodiment and embodiment one is：
Step 1）In be to grow GaN cushions, GaN channel layers and AlGaN potential barrier successively on sic substrates；
Step 5）In be use LPCVD equipment makings SiNxAs the passivation layer of GaN power devices, depositing temperature is 780 DEG C, SiNxThickness is 300nm；
Step 8）In be using grinding combine ICP etch method remove silicon carbide substrates.
Embodiment three：
The difference of the embodiment and embodiment one is：
Step 1）In be to grow GaN cushions, GaN channel layers and AlGaN potential barrier successively on a sapphire substrate；
Step 5）In be to use atomic layer deposition apparatus（ALD）Make Al2O3As the passivation layer of device, sedimentary origin uses Al- CH3And Al-OH, deposit thickness is 50nm；
Step 8）In be using laser lift-off method remove Sapphire Substrate；Moreover, ion implanting is carried out using Al ions Injection isolation, and carried out using injection mode twice, injected for the first time using 135 KeV energy, implantation dosage is 5 ×1014 cm2, injected for the second time using 90 KeV energy, implantation dosage is 3 × 1014 cm2。
Example IV：
The difference of the embodiment and embodiment one is：
Step 4）In be use electron beam evaporation plating multiple layer metal Pd/Ni/Au, thickness is respectively 50/100/200 nm, be used as source electricity Pole and the metal of drain electrode；
Step 6）The metal of middle gate electrode is prepared by reaction magnetocontrol sputtering, and specific metal level is TiN/Ti/Au multiple layer metals, Thickness is respectively 150/100/200nm；
Step 9）In be using high heat conduction high resistant carbofrax material as high heat conduction substrate.
The present invention is described by embodiment, but not limited the invention, with reference to description of the invention, institute Other changes of disclosed embodiment, are such as readily apparent that, such change should belong to for the professional person of this area Within the scope of the claims in the present invention are limited.

Claims (10)

1. a kind of GaN power devices based on ion implanting, it is characterised in that：Including the GaN bufferings set gradually from lower to upper Layer（2）, GaN channel layers（3）And AlGaN potential barrier（4）, the AlGaN potential barrier（4）Upper setting active electrode（5）, gate electrode （8）And drain electrode（6）, wherein the source electrode（5）And drain electrode（6）It is Ohmic contact, the gate electrode（8）For Schottky Contact, and between each electrode covered with AlGaN potential barrier（4）The passivation layer being connected（7）, the AlGaN potential barrier（4）With GaN channel layers（3）It is for heterojunction structure and horizontal as GaN power devices because polarity effect is formed with both interfaces The two-dimensional electron gas of work conducting channel, the GaN cushions（2）In by GaN cushions（2）Underrun ion implanting shape Into there is ion isolated area（10）, the ion isolated area（10）Positioned at GaN cushions（2）Top and with GaN channel layers（3）Phase Connection, and the GaN cushions（2）In be provided with ion isolated area（10）Afterwards in GaN cushions（2）Bottom surface be bonded with height Thermal conductive substrate（11）.
2. a kind of manufacture method of the GaN power devices based on ion implanting, this method is used to manufacture described in the claims 1 GaN power devices, it is characterised in that comprise the following steps：
1. using Metalorganic Chemical Vapor Deposition in growth substrates（1）On epitaxial growth GaN cushions successively（2）、GaN Channel layer（3）And AlGaN potential barrier（4）；
2. in AlGaN potential barrier（4）Upper use ultraviolet photolithographic preparation first time mask, the pattern etched as active region mesa, And mesa etch is carried out to realize discrete GaN power devices using dry etch process, etching depth is 50nm~200nm；
3. by photoetching in AlGaN potential barrier（4）The metal of second of mask preparation of upper progress, evaporation source electrode and drain electrode, And ultrasound is carried out to metal-stripping using organic solvent, obtain source electrode（5）And drain electrode（6）Metallic pattern, and by fast Speed heat annealing process realizes source electrode（5）And drain electrode（6）With AlGaN potential barrier（4）Ohmic contact；
4. in AlGaN potential barrier（4）Surface on deposit thickness be 50nm~500nm passivation layer（7）, and use optical graving Standby mask, in passivation layer（7）Upper etching source electrode window, drain electrode window and grid groove；
5. deposited in grid groove for forming gate electrode（8）Metal, and gate electrode（8）With AlGaN potential barrier（4）Form Xiao Te Ji is contacted；
6. in passivation layer（7）Surface on prepare one layer cover source electrode（5）, drain electrode（6）And gate electrode（8）Insulation Layer is used as interim transfer layer（9）；
7. growth substrates are removed（1）, expose GaN cushions（2）Bottom surface, and from GaN cushions（2）Underrun ion Injection and in GaN cushions（2）The middle ion isolated area for forming a high resistant（10）, and the ion isolated area（10）It is slow positioned at GaN Rush layer（2）Top and with GaN channel layers（3）It is connected；
8. in GaN cushions（2）Bottom surface on grow one layer of bonding material, and high heat conduction is bonded with by this layer of bonding material Substrate（11）；
9. interim transfer layer is removed（9）, complete the preparation of whole GaN power devices.
3. the manufacture method of the GaN power devices according to claim 2 based on ion implanting, it is characterised in that：It is described The metal of source electrode and drain electrode is selected from one or more of combinations or their conjunction in Ti, Al, Mo, Au, Ni, W Gold, thickness is 50~200 nm, and rapid thermal anneal process is to carry out in a nitrogen environment, and treatment temperature is 700~950 DEG C.
4. the manufacture method of the GaN power devices according to claim 2 based on ion implanting, it is characterised in that：It is described Passivation layer selection deposits the SiN prepared by PECVD, LPCVD, ALD or Sputterx、SiO2、SiNO、Al2O3, one kind in AlN Or it is a variety of.
5. the manufacture method of the GaN power devices according to claim 2 based on ion implanting, it is characterised in that：It is described One or more of combinations of the metal of gate electrode in Ni, Au, Pt, Al, TiW, TiN, thickness is 50~200nm.
6. the manufacture method of the GaN power devices according to claim 2 based on ion implanting, it is characterised in that：It is described Bonding material is one or more of combination in Au, Sn, In, Ti, Ni, Pt, Pb or their alloy.
7. the manufacture method of the GaN power devices according to claim 2 based on ion implanting, it is characterised in that：It is described The temperature of bonding is 200~350 DEG C, and pressure is 0~5000 Kg.
8. the manufacture method of the GaN power devices according to claim 2 based on ion implanting, it is characterised in that：It is described High heat conduction substrate is the good silicon or copper or carborundum or ceramics of thermal conductance.
9. the manufacture method of the GaN power devices according to claim 2 based on ion implanting, it is characterised in that：It is described Remove growth substrates method for laser lift-off, light assisted electrochemical method etch, wet etching method, polishing, polishing processes, One or more of combinations in ICP/RIE dry etching methods.
10. the manufacture method of the GaN power devices according to claim 2 based on ion implanting, it is characterised in that：It is described Ion implanting is to use one or more elements in Fe, C, B, Zn, Al, and is carried out using 20KeV~150KeV energy Injection, implantation dosage is 1012~1016/cm2。
CN201710483029.3A 2017-06-22 2017-06-22 A kind of GaN power devices and its manufacture method based on ion implanting Pending CN107170671A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201710483029.3A CN107170671A (en) 2017-06-22 2017-06-22 A kind of GaN power devices and its manufacture method based on ion implanting

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201710483029.3A CN107170671A (en) 2017-06-22 2017-06-22 A kind of GaN power devices and its manufacture method based on ion implanting

Publications (1)

Publication Number Publication Date
CN107170671A true CN107170671A (en) 2017-09-15

Family

ID=59819109

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710483029.3A Pending CN107170671A (en) 2017-06-22 2017-06-22 A kind of GaN power devices and its manufacture method based on ion implanting

Country Status (1)

Country Link
CN (1) CN107170671A (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108198747A (en) * 2018-01-09 2018-06-22 湖南理工学院 A kind of method that secondary epitaxy growth prepares gallium nitride material
CN110808285A (en) * 2019-11-26 2020-02-18 华南理工大学 HEMT device based on Cu substrate and preparation method thereof
CN111048471A (en) * 2019-12-05 2020-04-21 中国电子科技集团公司第五十五研究所 Preparation method of n-channel and p-channel enhanced GaN device integrated structure
CN111755524A (en) * 2020-07-20 2020-10-09 西安电子科技大学 Schottky accumulation layer silicon carbide transverse field effect transistor and manufacturing method thereof
US20210118871A1 (en) * 2019-10-22 2021-04-22 Analog Devices, Inc. Aluminum-based gallium nitride integrated circuits
CN113130643A (en) * 2020-12-18 2021-07-16 英诺赛科(苏州)科技有限公司 Semiconductor device and method of manufacturing semiconductor device
CN113555431A (en) * 2021-07-21 2021-10-26 西安电子科技大学 Homoepitaxy gallium nitride high electron mobility transistor based on P-type GaN leakage isolation layer and manufacturing method
CN113823681A (en) * 2021-08-30 2021-12-21 瑶芯微电子科技(上海)有限公司 HEMT device based on grid field plate and double-source field plate and preparation method thereof
CN113871477A (en) * 2021-08-30 2021-12-31 瑶芯微电子科技(上海)有限公司 Double-heterojunction HEMT device based on grid field plate and source field plate and preparation method thereof
US11888054B2 (en) 2020-12-18 2024-01-30 Innoscience (Suzhou) Technology Co., Ltd. Semiconductor device and method for manufacturing the same

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1419713A (en) * 2000-02-04 2003-05-21 美商克立光学公司 Group III nitride based fets and hemts with reduced trapping and method for producing the same
CN101908511A (en) * 2010-07-27 2010-12-08 南京大学 Gallium nitride schottky rectifier with metal substrate and production method thereof
CN102368501A (en) * 2011-10-20 2012-03-07 中山大学 GaN based enhanced MOSHFET device and preparation method thereof
US20130175539A1 (en) * 2012-01-11 2013-07-11 Samsung Electronics Co., Ltd. High electron mobility transistors and methods of manufacturing the same
US20140021481A1 (en) * 2012-07-23 2014-01-23 Samsung Electronics Co., Ltd. Nitride-based semiconductor device and manufacturing method thereof
WO2015123534A1 (en) * 2014-02-14 2015-08-20 Dow Corning Corporation Group iii-n substrate and transistor with implanted buffer layer
CN104916771A (en) * 2014-03-12 2015-09-16 山东浪潮华光光电子股份有限公司 Substrate-replaced normally-mounted GaN-based light-emitting diode chip and preparation method thereof
CN206907738U (en) * 2017-06-22 2018-01-19 广东省半导体产业技术研究院 A kind of GaN power devices based on ion implanting

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1419713A (en) * 2000-02-04 2003-05-21 美商克立光学公司 Group III nitride based fets and hemts with reduced trapping and method for producing the same
CN101908511A (en) * 2010-07-27 2010-12-08 南京大学 Gallium nitride schottky rectifier with metal substrate and production method thereof
CN102368501A (en) * 2011-10-20 2012-03-07 中山大学 GaN based enhanced MOSHFET device and preparation method thereof
US20130175539A1 (en) * 2012-01-11 2013-07-11 Samsung Electronics Co., Ltd. High electron mobility transistors and methods of manufacturing the same
US20140021481A1 (en) * 2012-07-23 2014-01-23 Samsung Electronics Co., Ltd. Nitride-based semiconductor device and manufacturing method thereof
WO2015123534A1 (en) * 2014-02-14 2015-08-20 Dow Corning Corporation Group iii-n substrate and transistor with implanted buffer layer
CN104916771A (en) * 2014-03-12 2015-09-16 山东浪潮华光光电子股份有限公司 Substrate-replaced normally-mounted GaN-based light-emitting diode chip and preparation method thereof
CN206907738U (en) * 2017-06-22 2018-01-19 广东省半导体产业技术研究院 A kind of GaN power devices based on ion implanting

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108198747A (en) * 2018-01-09 2018-06-22 湖南理工学院 A kind of method that secondary epitaxy growth prepares gallium nitride material
US20210118871A1 (en) * 2019-10-22 2021-04-22 Analog Devices, Inc. Aluminum-based gallium nitride integrated circuits
US12087713B2 (en) 2019-10-22 2024-09-10 Analog Devices, Inc. Gallium nitride integrated circuits including non-gold-based metallic materials
US11569182B2 (en) * 2019-10-22 2023-01-31 Analog Devices, Inc. Aluminum-based gallium nitride integrated circuits
CN110808285A (en) * 2019-11-26 2020-02-18 华南理工大学 HEMT device based on Cu substrate and preparation method thereof
CN110808285B (en) * 2019-11-26 2024-08-02 华南理工大学 HEMT device based on Cu substrate and preparation method thereof
CN111048471A (en) * 2019-12-05 2020-04-21 中国电子科技集团公司第五十五研究所 Preparation method of n-channel and p-channel enhanced GaN device integrated structure
CN111755524B (en) * 2020-07-20 2022-06-07 西安电子科技大学 Schottky accumulation layer silicon carbide transverse field effect transistor and manufacturing method thereof
CN111755524A (en) * 2020-07-20 2020-10-09 西安电子科技大学 Schottky accumulation layer silicon carbide transverse field effect transistor and manufacturing method thereof
US11888054B2 (en) 2020-12-18 2024-01-30 Innoscience (Suzhou) Technology Co., Ltd. Semiconductor device and method for manufacturing the same
US12027615B2 (en) 2020-12-18 2024-07-02 Innoscience (Suzhou) Technology Co., Ltd. Semiconductor device and method for manufacturing the same
CN113130643A (en) * 2020-12-18 2021-07-16 英诺赛科(苏州)科技有限公司 Semiconductor device and method of manufacturing semiconductor device
CN113555431B (en) * 2021-07-21 2022-12-02 西安电子科技大学 Homoepitaxy gallium nitride high electron mobility transistor based on P-type GaN leakage isolation layer and manufacturing method
CN113555431A (en) * 2021-07-21 2021-10-26 西安电子科技大学 Homoepitaxy gallium nitride high electron mobility transistor based on P-type GaN leakage isolation layer and manufacturing method
CN113871477A (en) * 2021-08-30 2021-12-31 瑶芯微电子科技(上海)有限公司 Double-heterojunction HEMT device based on grid field plate and source field plate and preparation method thereof
CN113823681A (en) * 2021-08-30 2021-12-21 瑶芯微电子科技(上海)有限公司 HEMT device based on grid field plate and double-source field plate and preparation method thereof
CN113871477B (en) * 2021-08-30 2024-08-16 瑶芯微电子科技(上海)有限公司 Double heterojunction HEMT device based on gate field plate and source field plate and preparation method thereof

Similar Documents

Publication Publication Date Title
CN107170671A (en) A kind of GaN power devices and its manufacture method based on ion implanting
CN104992974B (en) Buddha's warrior attendant ground mass double hyer insulation gate medium field-effect transistor and preparation method thereof
CN100557815C (en) InAlN/GaN heterojunction enhancement type high electron mobility transistor structure and manufacture method
CN103928344B (en) One kind improves N-type DiMOSFET channel mobility method based on N-type nano thin-layer
CN110112215A (en) Have both the normally-off power device and preparation method thereof of gate-dielectric and etching barrier layer functional structure
CN108666359A (en) A kind of device architecture and implementation method improving GaN enhancement type channel mobilities using novel barrier layer
CN108305834A (en) A kind of preparation method of enhancement type gallium nitride fieldtron
CN107240605A (en) A kind of GaN MIS raceway grooves HEMT device and preparation method
CN206907738U (en) A kind of GaN power devices based on ion implanting
CN115312389A (en) Method for manufacturing semiconductor device having vertical structure and semiconductor device
CN208028062U (en) A kind of enhanced and depletion type GaN HEMT integrated morphologies
CN101252100B (en) Method for insulating AlGaN / GaN HEMT device
CN110364575A (en) A kind of junction barrier schottky diode and preparation method thereof with floating field ring terminal structure
CN103681256B (en) A kind of silicon carbide MOSFET device and preparation method thereof
CN107919390A (en) Based on WO3The diamond field effect transistor and production method of gate medium
CN104681646A (en) Silicon carbide embedded electrode planar photoconductive switch and manufacture method thereof
CN105448974B (en) A kind of GaN base thin-film transistor structure and preparation method thereof
CN110504299A (en) GaN groove anode Schottky diode preparation method based on graphical regrowth
CN112018177B (en) Full-vertical Si-based GaN UMOSFET power device and preparation method thereof
CN107230625A (en) Gallium nitride transistor and its manufacture method
CN116705605B (en) Silicon-based gallium nitride HEMT device and preparation method thereof
CN207068860U (en) A kind of GaN MIS raceway groove HEMT devices
CN113628963B (en) III-nitride enhanced HEMT device and manufacturing method thereof
CN113628962B (en) III-nitride enhanced HEMT device and manufacturing method thereof
CN104979195B (en) The preparation method of SiC Base HEMT device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20170915