CN107026130B - Apparatus and method for packaging devices - Google Patents

Apparatus and method for packaging devices Download PDF

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Publication number
CN107026130B
CN107026130B CN201610826015.2A CN201610826015A CN107026130B CN 107026130 B CN107026130 B CN 107026130B CN 201610826015 A CN201610826015 A CN 201610826015A CN 107026130 B CN107026130 B CN 107026130B
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Prior art keywords
packaged
component
package
grooves
mounting structure
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CN107026130A (en
Inventor
兰多夫·克鲁兹
小劳埃德·M·卡朋特
马克·A·科沃卡
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Intersil Americas LLC
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Intersil Americas LLC
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00—Details of transformers or inductances, in general
    • H01F27/02—Casings
    • H01F27/022—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3142—Sealing arrangements between parts, e.g. adhesion promotors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/003—Constructional details, e.g. physical layout, assembly, wiring or busbar connections

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Dc-Dc Converters (AREA)

Abstract

One embodiment relates to a packaged device. The packaged device includes a device and a first package overlying the device. The first encapsulant has one or more outer surfaces. One or more recesses in the one or more outer surfaces are configured to receive a second encapsulant.

Description

Apparatus and method for packaging devices
Cross Reference to Related Applications
This application claims priority to us provisional patent application No. 62/218687 filed on 15/9/2015 and us provisional patent application No. 62/242447 filed on 16/10/2015, both of which are incorporated herein by reference in their entirety.
Technical Field
The present application relates to an apparatus and method for packaging a device.
Background
Devices encapsulated with a plastic, such as a thermosetting plastic material, such as Epoxy Molding Compound (EMC), or a thermoplastic material, and formed with an encapsulation molding are used in systems such as electrical systems. The device may be encapsulated to protect it from the environment and to protect its mechanical and electrical integrity. In one particular approach, the device terminals are not encapsulated to facilitate connection to other items.
The device may be an active device, such as an Integrated Circuit (IC), a transistor, or other active semiconductor device. The device may also be a passive device such as an inductor, a capacitor, or a mechanical device such as an accelerometer. The device may have conductive terminals that are wired or non-wired.
When one or more devices are mounted on the mounting structure, the component is formed. The mounting structure includes a carrier, a lead frame (lead frame), a substrate, and a Printed Circuit Board (PCB). The mounting structure may have terminals with or without leads. The component may be mounted on another mounting structure, for example mounting the component (such as a device on a carrier) on a PCB. The components may also be encapsulated (as described above and for the same reasons).
When the packaged device is mounted on the mounting structure, a gap is formed between the packaged device and the mounting structure. (mounting structures can be used to make System-in-Package (System-in-Package) or multi-chip module (Multichip module.) due to System miniaturization requirements, the gap is narrow compared to the size of the components to be packaged. It is difficult to vent and remove trapped air and volatile gases from the molten component package (e.g., a molten thermoset plastic material such as molten EMC or a molten thermoplastic material from a closed mold) so that the molten material fills the gap.
There is an increased risk of: during the encapsulation of the component, one or more voids, i.e. air and/or volatile gas pockets, enclosed by the encapsulation are formed in the gap. Such voids exacerbate the thermal mechanical mismatch and create interfacial stresses between the component and the package of the device. This results in localized stress concentration points that can induce interfacial material delamination and fracture. In addition, moisture may accumulate in the voids; during subsequent thermal cycling, the hydrostatic pressure of the moisture may induce delamination of the component package where it adjoins the mounting structure and/or the device package. Hydrostatic pressure may also induce cracks in the component and/or device package. Thus, such voids undesirably reduce the reliability of the package components.
Furthermore, depending on the shape and size of the packaged device, any differences in thermo-mechanical properties between the device package and the component package, interfacial stresses may be induced in one or both of those materials. For example, stresses may be created in a component package, such as in an encapsulation cap. This may lead to fractures in the component packaging cap (which may lead to delamination of the cap) and/or deformation of the cap. Such deformation and/or breakage may also undesirably reduce the reliability of the packaged component.
Disclosure of Invention
The interfacial stress can be reduced by increasing the contact surface area at the interface. To reduce the risk of forming deformations, fractures and voids, one or more grooves may be formed in one or more surfaces of the device package.
According to the present invention, there is provided a packaged device comprising:
a device;
a first encapsulant covering the device and having one or more outer surfaces; and
one or more grooves in the one or more outer surfaces and configured to receive a second encapsulant.
Wherein the one or more recesses are located on opposing surfaces of the first encapsulant.
Wherein the first encapsulation is one of a thermoset plastic material or a thermoplastic material.
Wherein the second package is one of a thermoset plastic material or a thermoplastic material.
Wherein the device is an inductor.
Wherein a height and a width of at least one of the one or more grooves are each greater than or equal to fifty microns.
Wherein a ratio of a width of at least one of the one or more grooves to a height of the at least one of the one or more grooves is between fifty percent and one hundred percent.
Wherein the one or more grooves are one of L-shaped grooves, parallelogram grooves, and trapezoidal grooves.
According to the present invention, there is also provided a packaged device comprising:
one or more packaged devices packaged by the first package;
wherein each packaged device has an outer surface on the first package;
one or more grooves in at least one of the outer surfaces; and
a second encapsulant covering the one or more encapsulated devices, the second encapsulant substantially filling the one or more recesses of at least one of the encapsulated devices.
The package assembly further comprises:
a mounting structure to which the packaged device is attached;
a gap between the packaged device and the mounting structure; and
wherein the second encapsulant substantially fills the gap.
Wherein the first encapsulation is one of a thermoset plastic material or a thermoplastic material.
Wherein the second encapsulation is one of a thermoset plastic material or a thermoplastic material.
Wherein a ratio of a width of one of the one or more grooves in the outer surface of one of the packaged devices to a width of the one of the packaged devices is between one percent and twenty-five percent.
Wherein a height and a width of one of at least one of the one or more grooves are each greater than or equal to fifty microns.
Wherein a ratio of a width of one groove of the one or more grooves to a height of the one groove is between fifty percent and one hundred percent.
Wherein one of the one or more grooves is one of an L-shaped groove, a parallelogram groove, and a trapezoidal groove.
Wherein at least one of the packaged devices is one of an inductor, a PWM controller and driver, a capacitor, and at least one power transistor.
Wherein the packaged component is a DC-DC voltage transformer, the DC-DC voltage transformer comprising:
a PWM controller and driver;
at least one power transistor connected to the output of the PWM controller and driver; and
an output filter connected to the at least one power transistor.
Wherein an output of the DC-DC voltage transformer is connected to a processing system.
Wherein the processing system includes a processor coupled to a memory.
There is also provided a method comprising the steps of:
encapsulating the device with a first encapsulation member to form an encapsulated device; and
forming a recess on one or more surfaces of the first encapsulant, the recess configured to receive a subsequently placed second encapsulant that will cover the encapsulated device.
The method further comprises the steps of: mounting the packaged device on a mounting structure.
The method further comprises the steps of: one or more additional packaged devices or additional unpackaged devices are mounted on the mounting structure.
The method further comprises the steps of: covering the packaged device and mounting structure with the second encapsulant substantially filling at least one of the recesses.
Drawings
FIG. 1A is a cross-sectional view of one embodiment of a packaged component including a packaged device and an unpackaged device.
FIG. 1B is a cross-sectional view of various embodiments of a groove.
Figure 2A is a cross-sectional view of one embodiment of a groove in a device package.
Figure 2B is a cross-sectional view of another embodiment of a groove in a device package.
FIG. 3A is a perspective view of one embodiment of multiple grooves parallel along one axis.
FIG. 3B is a perspective view of one embodiment of multiple parallel grooves on one axis with a single groove along a vertical axis.
FIG. 4 is a diagram illustrating one embodiment of an electrical system.
Fig. 5 is a diagram illustrating one embodiment of a method of manufacturing a packaged device and a packaged component and then mounting the packaged component on a mounting structure.
Fig. 6 illustrates one embodiment of bonding (attach) an array of package components to each other via connectors.
Detailed Description
Devices encapsulated with a plastic, such as a thermoset plastic material, such as an Epoxy Molding Compound (EMC), or a thermoplastic material, and formed by encapsulation molding, are used in systems such as electrical systems. The device may be encapsulated to protect it from the environment and to protect its mechanical and electrical integrity. In one particular approach, the device terminals are not encapsulated to facilitate connection to other items.
The device may be an active device, such as an Integrated Circuit (IC), a transistor, or other active semiconductor device. The device may also be a passive device such as an inductor, a capacitor, or a mechanical device such as an accelerometer. The device may have conductive terminals that are leaded or non-leaded.
When one or more devices are mounted on the mounting structure, the component is formed. The mounting structure includes a carrier, a lead frame (lead frame), a substrate, and a Printed Circuit Board (PCB). The mounting structure may have terminals with or without leads. The component may be mounted on another mounting structure, for example mounting the component (such as a device on a carrier) on a PCB. The components may also be encapsulated (as described above and for the same reasons).
When the packaged device is mounted on the mounting structure, a gap is formed between the packaged device and the mounting structure. (the mounting structure may be used to make a System-in-Package (System-in-Package) or a multi-chip module.) due to System miniaturization requirements, the gap is narrow compared to the size of the components to be packaged. It is difficult to vent and remove trapped air and volatile gases from the molten component package (e.g., a molten thermoset plastic material such as molten EMC or a molten thermoplastic material from a closed mold) so that the molten material fills the gap.
There is an increased risk of: during the encapsulation of the component, one or more voids, i.e. air and/or volatile gas pockets, enclosed by the encapsulation are formed in the gap. Such voids exacerbate the thermal mechanical mismatch and create interfacial stresses between the component and the package of the device. This results in localized stress concentration points that can induce interfacial material delamination and fracture. In addition, moisture may accumulate in the voids; during subsequent thermal cycling, the hydrostatic pressure of the moisture may induce delamination of the component package where it adjoins the mounting structure and/or the device package. Hydrostatic pressure may also induce cracks in the component and/or device package. Thus, such voids undesirably reduce the reliability of the package components.
Furthermore, depending on the shape and size of the packaged device, any differences in thermo-mechanical properties between the device package and the component package, interfacial stresses may be induced in one or both of those materials. For example, stresses may be created in a component package, such as in a package lid (encapsulation cap). This may lead to fractures in the component packaging cap (which may lead to delamination of the cap) and/or deformation of the cap. Such deformation and/or breakage may also undesirably reduce the reliability of the packaged component.
The interfacial stress can be reduced by increasing the contact surface area at the interface. To reduce the risk of forming deformations, fractures and voids, one or more grooves may be formed in one or more surfaces of the device package. Fig. 1A illustrates one embodiment of the present invention, with a packaged component 100 comprising a packaged device 104 and an unpackaged device 106. The packaged device 104 and the unpackaged device 106 are mounted on a mounting structure 108. The packaged devices 104, the unpackaged devices 106, and the mounting structures 108 are covered by a component package 110. The packaged device 104 is covered with a device package 105.
A recess 122 is formed in the device package 105. The set of recesses 122A (the set being in the bottom surface 114A of the packaged device, the bottom surface 114A being closest to the mounting structure 108 and substantially parallel to the mounting structure 108) facilitates venting of the component package 110 through the gap 107. In fig. 1A, gap 107 is more specifically formed by mounting structure 108 and the exposed region of unpackaged device 106, all under packaged device 104.
The set of recesses 122B (the set in the top surface 114B of the packaged device, the top surface 114B closest to the top surface 112 of the package component 100 and substantially parallel to the top surface 112) facilitates eliminating, for example, delamination and cracking around the top surface 112.
Recess 122 also serves to interlock device package 105 and component package 110, thus enhancing the mechanical integrity (mechanical integrity) and reliability of packaged component 100. Such interlocking improves adhesion between device package 105 and component package 110. Typical groove profiles are shown in FIG. 1B, including inverted L-shaped grooves 122a, L-shaped grooves 122B, quadrilateral grooves 122c, parallelogram grooves 122d, inverted trapezoidal grooves 122e, trapezoidal grooves 122f, and rectangular grooves 122g. Shapes such as L-shaped groove 122b, parallelogram-shaped groove 122d, and trapezoidal-shaped groove 122f enhance interlocking strength and reduce interface stress between component package 110 and device package 105 due to their shapes.
The size of the recess 122 depends on the technique used to form the recess, the size of the device package 105, the size required to facilitate venting, and the number of recesses 122 required to enhance adhesion between the device package 105 and the component package 110. In one embodiment, the height and width of the grooves 122 are each greater than or equal to fifty microns. In another embodiment, the ratio of the width of the recess 122 to the width of the packaged device 104 is between one percent and twenty-five percent. The width of the packaged device 104 will be the same size as the width of the corresponding recess 122. In yet another embodiment, the ratio of the width of the groove 122 to the height of the groove 122 is between fifty percent and one hundred percent.
Fig. 2A illustrates an exemplary recess 122 in the device package 105. Each recess 122 is formed by two sidewalls 204 extending below a nominal outer surface 210 of the device package 105. Fig. 2B illustrates another exemplary recess 122 above the nominal outer surface 210 of the device package 105. The recess 122 is formed with a protrusion 206 having a sidewall 204, the sidewall 204 extending above a nominal outer surface 210 of the device package 105.
In one embodiment, the recess 122 in the device package 105 may be formed along one or more axes. In another embodiment, two or more grooves 122 may be skewed (skew) at any angle from each other, such as from zero degrees to one hundred and eighty degrees; in one embodiment, the grooves intersect at ninety degrees. FIG. 3A illustrates an embodiment having a plurality of grooves 122 parallel along one axis; such that a typical recess extends through one axis of device package 105. Fig. 3B illustrates another embodiment having multiple parallel grooves 122 on one axis and a single groove 122 along a perpendicular axis.
In one embodiment, the package 100 may be used to implement all or part of a DC-DC voltage transformer (voltage converter), such as a buck transformer, boost transformer, buck-boost transformer, or synchronous buck transformer. Fig. 4 illustrates a typical electrical system 400, the system 400 including a load (e.g., a processing system 416) and a power supply 402, the power supply 402 including a DC-DC voltage transformer 404, the DC-DC voltage transformer 404 manufactured, for example, as a packaged component like the packaged component 100 of fig. 1A. In one embodiment, the processing system 416 is configured to be electrically connected to the DC-DC voltage transformer 404 to receive DC power. In another embodiment, the DC-DC voltage transformer 404 and the processing system 416 are configured to be coupled to each other by a data bus 450, the data bus 450 facilitating communication therebetween; this enables the processing system 416 to control the DC-DC voltage transformer 404. The electrical system 400 may be a device associated with telecommunications, automotive, semiconductor test and manufacturing equipment, consumer electronics, or other types of electronic equipment.
The power source 402 may be an AC to DC power source or may be a DC power source powered by a battery. In one embodiment, the processing system 416 may include a processor 418 and a memory 420 coupled to one another. In another embodiment, the processor 418 may be one or more microprocessors, microcontrollers, embedded processors, digital signal processors, or a combination of two or more of the foregoing. In yet another embodiment, the memory 420 may be one or more of volatile memory and/or non-volatile memory (such as static random access memory, dynamic random access memory, read only memory, and flash memory), or a combination of two or more of the foregoing.
In one embodiment, as illustrated in fig. 4, the DC-DC voltage transformer 404 includes a pulse width modulation ("PWM") controller and driver 406, power transistors, such as upper metal oxide semiconductor field effect transistors ("MOSFETs") 408A and lower MOSFETs 408B, and an output filter 410. The PWM controller and driver 406 causes the upper MOSFET408A and the lower MOSFET408B to alternately turn on and off. In another embodiment, the controller and driver 406 may include dead time control (dead time control). The output filter 410 includes, for example, a series inductor 412 and a shunt capacitor 414. The PWM controller and starter 406, the power transistor and the output filter 410 (or separate components thereof — the inductor 412 and the capacitor 414) may be implemented as one or more packaged and/or unpackaged devices in the packaged component 100.
In one embodiment, the PWM controller and driver 406 are mounted on a single IC. Alternatively, the PWM controller and driver 406 may be mounted on separate ICs. In yet another embodiment, the upper MOSFET408A and the lower MOSFET408B may be mounted on a single IC. In yet another embodiment, the upper MOSFET408A and the lower MOSFET408B may be mounted on the same IC as the PWM controller and driver 406.
In further examples, the packaged component 100 will include one or more components of other power management systems, including all or part of a charger, a hot swap controller, an AC-DC transformer, or a bridge driver.
Fig. 5 illustrates an exemplary method 500 of manufacturing the previously described package component 100 and packaged device 400, and then mounting the package component 100 on a second mounting structure. In block 502, one or more packaged devices 104 are formed (as will be described further below). In one embodiment, the recess 122 is formed when the device is covered with a thermoplastic material or a thermoset plastic material such as EMC in the device package 105, for example, by encapsulation molding such as injection molding. The mold may be designed to form the protrusion 206 and/or the recess 122 illustrated in fig. 2A and 2B, respectively.
In another embodiment, the device is first covered with device package 105. One or more recesses 122 are then formed in each packaged device 104 by removing portions of the device package 105. Removal of the device packages 105 can be achieved, for example, by photolithography and chemical etching, laser ablation, mechanical removal such as with sawing, or any combination thereof.
In one embodiment, the packaged device 104 is mounted on each of the one or more mounting structures 108 in block 504. Returning to fig. 1A, in one embodiment, the package device terminals 152 are electrically connected to the mounting structure terminals 154 with solder 150.
In optional block 506, other packaged devices 104 and/or unpackaged devices 106 are mounted on the mounting structure 108. Depending on the location of the unpackaged devices 106, such unpackaged devices 106 may have to be installed prior to installing the packaged devices 104 in block 504. For example, if the unpackaged device 106 is mounted below the packaged device 104, the unpackaged device 106 would be mounted prior to mounting the packaged device 104. In one embodiment, these other devices are mounted on the mounting structure 108 in the same manner as the packaged device 104 is mounted to the mounting structure 108 (as described above).
In block 508, the device and mounting structure 108 are covered with the component package 110 (e.g., in the manner described above for packaging the device). In block 510, the package component 100 is mounted on the second mounting structure 156 (as illustrated in fig. 1A). In one embodiment, the package component 100 may be mounted on the second mounting structure 156 in the same manner as the package device 104 is mounted on the mounting structure (as described above), e.g., with the solder 150 electrically connecting the package component terminals 158 to the second mounting structure terminals 160.
The packaged device 104 and/or the packaged component 100 may be manufactured in such a way that a plurality of packaged devices 104 and/or packaged components 100 are manufactured at the same time. Therefore, a plurality of packaged devices 104 can be made adjacent to each other. As illustrated in fig. 6, in one embodiment, the packaged devices 104 can be fabricated in an array 600 and joined by a connector 602, such as a notch (kerf). Once assembled, each packaged device 104 can be singulated (singulated) by substantially eliminating connectors 602, such as by sawing, for example, after block 502. Similarly, as illustrated above for the package component 100, a plurality of package components 100 can be manufactured together. These package components 100 may be fabricated in an array 600 and, for example, after block 508, the package components 100 may be singulated, for example, in the manner described above. Thus, in one embodiment, block 502 described above may include forming more than one packaged device 104 and recess 122 therein. In another embodiment, block 502 may also include singulating the packaged devices 104 of the array 600 with the grooves 122 therein, for example, by kerf removal by sawing.
Many examples have been defined by the appended claims. Nevertheless, it will be understood that various modifications to the described examples may be made without departing from the scope of the claimed invention. The features and aspects of particular examples described herein can be combined with or substituted for those of others. Accordingly, other examples are within the scope of the following claims.
Examples of the embodiments
Example 1 includes a packaged device, comprising: a device; a first encapsulant covering the device and having one or more outer surfaces; and one or more grooves in the one or more outer surfaces and configured to receive a second encapsulant.
Example 2 includes the packaged device of example 1, wherein the one or more recesses are located on opposing surfaces of the first package.
Example 3 includes the packaged device of example 1, wherein the first package is one of a thermoset plastic material or a thermoplastic material.
Example 4 includes the packaged device of example 1, wherein the second package is one of a thermoset plastic material or a thermoplastic material.
Example 5 includes the packaged device of example 1, wherein the device is an inductor.
Example 6 includes the packaged device of example 1, wherein a height and a width of at least one of the one or more grooves are each greater than or equal to fifty microns.
Example 7 includes the packaged device of example 1, wherein a ratio of a width of at least one of the one or more grooves to a height of the at least one of the one or more grooves is between fifty percent and one hundred percent.
Example 8 includes the packaged device of example 1, wherein the one or more grooves are one of L-shaped grooves, parallelogram-shaped grooves, and trapezoidal-shaped grooves.
Example 9 includes a package component, the package component comprising: one or more packaged devices packaged by the first package; wherein each packaged device has an outer surface on the first package; one or more grooves in at least one of the outer surfaces; and a second encapsulant covering the one or more encapsulated devices, the second encapsulant substantially filling the one or more recesses of at least one of the encapsulated devices.
Example 10 includes the package component of example 9, further comprising: a mounting structure to which the packaged device is attached; a gap between the packaged device and the mounting structure; and wherein the second encapsulant substantially fills the gap.
Example 11 includes the encapsulated component of example 9, wherein the first encapsulation is one of a thermoset plastic material or a thermoplastic material.
Example 12 includes the encapsulated component of example 9, wherein the second encapsulation is one of a thermoset plastic material or a thermoplastic material.
Example 13 includes the packaging component of example 9, wherein a ratio of a width of one of the one or more grooves in the outer surface of one packaged device to a width of the one packaged device is between one percent and twenty-five percent.
Example 14 includes the packaging component of example 9, wherein a height and a width of one of the at least one of the one or more grooves are each greater than or equal to fifty microns.
Example 15 includes the packaging component of example 9, wherein a ratio of a width of one groove of the one or more grooves to a height of the one groove is between fifty percent and one hundred percent.
Example 16 includes the packaging component of example 9, wherein one of the grooves is one of an L-shaped groove, a parallelogram groove, and a trapezoidal groove.
Example 17 includes the packaged component of example 9, wherein at least one of the packaged devices is one of an inductor, a PWM controller and driver, a capacitor, and at least one power transistor.
Example 18 includes the packaged component of example 10, wherein the packaged component is a DC-DC voltage transformer, the DC-DC voltage transformer including: a PWM controller and a driver; at least one power transistor connected to the output of the PWM controller and driver; and an output filter connected to the at least one power transistor.
Example 19 includes the packaging component of example 18, wherein an output of the DC-DC voltage transformer is connected to a processing system.
Example 20 includes the packaging component of example 19, wherein the processing system includes a processor connected to a memory.
Example 21 includes a method comprising: encapsulating the device with a first encapsulation member to form an encapsulated device; and forming a recess on one or more surfaces of the first encapsulant, the recess configured to receive a subsequently placed second encapsulant that will cover the encapsulated device.
Example 22 includes the method of example 21, further including the steps of: mounting the packaged device on a mounting structure.
Example 23 includes the method of example 21, further including the steps of: one or more additional packaged devices or additional unpackaged devices are mounted on the mounting structure.
Example 24 includes the method of example 21, further including the steps of: covering the packaged device and mounting structure with the second encapsulant substantially filling at least one of the recesses.

Claims (17)

1. A packaged device, comprising:
a device to be packaged; and
a first encapsulation covering the device to be encapsulated and having one or more outer surfaces;
wherein the one or more outer surfaces comprise one or more grooves configured to receive a second encapsulant,
wherein the one or more recesses are located on opposite surfaces of the device to be packaged and are formed in at least one of the outer surfaces that is closest to a mounting structure that can be attached to the packaged device,
wherein the first package is one of a thermoset plastic material or a thermoplastic material, and
wherein the second encapsulation is one of a thermoset plastic material or a thermoplastic material.
2. The packaged device of claim 1, wherein the device to be packaged is an inductor.
3. The packaged device of claim 1, wherein a height and a width of at least one of the one or more grooves are each greater than or equal to fifty microns.
4. The packaged device of claim 1, wherein a ratio of a width of at least one of the one or more grooves to a height of the at least one of the one or more grooves is between fifty percent and one hundred percent.
5. The packaged device of claim 1, wherein the one or more grooves are one of an L-shaped groove, a parallelogram-shaped groove, and a trapezoidal-shaped groove.
6. A packaged component, comprising:
one or more packaged devices including a device to be packaged and a first package covering the device to be packaged;
wherein each packaged device has an outer surface comprising one or more recesses;
a second encapsulant covering the one or more encapsulated devices, the second encapsulant filling the one or more recesses of at least one of the encapsulated devices;
a mounting structure to which the packaged device is attached; and
a gap between the packaged device and the mounting structure;
wherein the second encapsulation fills the gap and the recess is formed in at least one of the outer surfaces that is closest to the mounting structure,
wherein the first package is one of a thermoset plastic material or a thermoplastic material, and
wherein the second encapsulation is one of a thermoset plastic material or a thermoplastic material.
7. The packaging component of claim 6, wherein a ratio of a width of one of the one or more grooves in an outer surface of one packaging device to a width of the one packaging device is between one percent and twenty-five percent.
8. The package component of claim 6, wherein a height and a width of one of at least one of the one or more grooves are each greater than or equal to fifty microns.
9. The package component of claim 6, wherein a ratio of a width of one of the one or more grooves to a height of the one groove is between fifty percent and one hundred percent.
10. The packaging component of claim 6, wherein one of the one or more grooves is one of an L-shaped groove, a parallelogram groove, and a trapezoidal groove.
11. The packaged component of claim 6, wherein at least one of the packaged devices is one of an inductor, a PWM controller and driver, a capacitor, and at least one power transistor.
12. The packaged component of claim 6, wherein the packaged component is a DC-DC voltage transformer comprising:
a PWM controller and driver;
at least one power transistor connected to an output of the PWM controller and driver; and
an output filter connected to the at least one power transistor.
13. The packaged component of claim 12, wherein an output of the DC-DC voltage transformer is connected to a processing system.
14. The packaged component of claim 13, wherein the processing system comprises a processor connected to a memory.
15. A method for packaging a device to be packaged, comprising the steps of:
packaging the device to be packaged by using the first packaging part to form a packaged device;
forming a recess on one or more surfaces of the first encapsulant, the recess corresponding to one or more recesses of the encapsulated device and configured to receive a subsequently placed second encapsulant, the second encapsulant covering the encapsulated device; and
mounting the packaged device on a mounting structure, wherein the recess of the packaged device is formed closest to the mounting structure,
wherein the first package is one of a thermoset plastic material or a thermoplastic material, and
wherein the second encapsulation is one of a thermoset plastic material or a thermoplastic material.
16. The method of claim 15, further comprising the steps of: one or more additional packaged devices or additional unpackaged devices are mounted on the mounting structure.
17. The method of claim 15, further comprising the steps of: covering the packaged device and the mounting structure with the second encapsulant, filling at least one of the recesses.
CN201610826015.2A 2015-09-15 2016-09-14 Apparatus and method for packaging devices Active CN107026130B (en)

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Publication number Priority date Publication date Assignee Title
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101611484A (en) * 2005-12-02 2009-12-23 宇芯（毛里求斯）控股有限公司 Leadless semiconductor encapsulation and manufacture method thereof
WO2015023536A1 (en) * 2013-08-12 2015-02-19 3M Innovative Properties Company Emissive article with light extraction film
CN104538425A (en) * 2014-12-19 2015-04-22 上海天马微电子有限公司 Barrier film, manufacturing method thereof and display device

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1652227A2 (en) 2003-06-25 2006-05-03 Advanced Interconnect Technologies Limited Lead frame routed chip pads for semiconductor packages
US8916966B2 (en) * 2004-09-28 2014-12-23 Triquint Semiconductor, Inc. Integrated circuit including a heat dissipation structure
CN100555589C (en) * 2005-06-29 2009-10-28 皇家飞利浦电子股份有限公司 Make the method for semiconductor subassembly
TW200743190A (en) * 2006-05-10 2007-11-16 Chung-Cheng Wang A heat spreader for electrical device
US8093693B2 (en) 2006-09-15 2012-01-10 Stats Chippac Ltd. Integrated circuit package system with encapsulation lock
US7718884B2 (en) 2008-07-17 2010-05-18 Sony Computer Entertainment America Inc. Method and apparatus for enhanced gaming
US8551820B1 (en) 2009-09-28 2013-10-08 Amkor Technology, Inc. Routable single layer substrate and semiconductor package including same
US8871572B2 (en) 2012-12-20 2014-10-28 Intersil Americas LLC Lead frame having a perimeter recess within periphery of component terminal

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101611484A (en) * 2005-12-02 2009-12-23 宇芯（毛里求斯）控股有限公司 Leadless semiconductor encapsulation and manufacture method thereof
WO2015023536A1 (en) * 2013-08-12 2015-02-19 3M Innovative Properties Company Emissive article with light extraction film
CN104538425A (en) * 2014-12-19 2015-04-22 上海天马微电子有限公司 Barrier film, manufacturing method thereof and display device

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