CN106898557B - It is integrated with the packaging method of the packaging part of power transmission system - Google Patents

It is integrated with the packaging method of the packaging part of power transmission system Download PDF

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Publication number
CN106898557B
CN106898557B CN201710124498.6A CN201710124498A CN106898557B CN 106898557 B CN106898557 B CN 106898557B CN 201710124498 A CN201710124498 A CN 201710124498A CN 106898557 B CN106898557 B CN 106898557B
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China
Prior art keywords
metal
lead wire
carrier
power transmission
transmission system
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CN201710124498.6A
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CN106898557A (en
Inventor
林章申
林正忠
何志宏
周祖源
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SJ Semiconductor Jiangyin Corp
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SJ Semiconductor Jiangyin Corp
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Priority to CN201710124498.6A priority Critical patent/CN106898557B/en
Publication of CN106898557A publication Critical patent/CN106898557A/en
Priority to PCT/CN2017/095403 priority patent/WO2018157547A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/071—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] involving a temporary auxiliary member not forming part of the bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

The present invention provides a kind of packaging method of packaging part for being integrated with power transmission system, includes the following steps: 1) to provide a carrier；2) metal lead wire is formed in carrier surface using lead key closing process；3) active module embedded therein and passive module are set to carrier to be formed on the surface of metal lead wire, and form metal connecting column in active module embedded therein and the passive module surface；4) by metal lead wire, active module embedded therein, passive module and metal connecting column encapsulated moulding；5) wiring layer again is formed on capsulation material surface；6) it will be set to electrical chip and be routed layer surface again, and realized with electrical chip via multiple dimpling blocks and docked with low voltage power supply track；7) carrier is removed, the solder projection being connected with metal lead wire is formed.By the present invention in that improving power transfer efficiency with three-dimensional chip Stack Technology, the quantity available of different voltages track is increased.

Description

It is integrated with the packaging method of the packaging part of power transmission system
Technical field
The present invention relates to technical field of semiconductor encapsulation, more particularly to a kind of packaging part for being integrated with power transmission system Packaging method.
Background technique
All calculating and communication system require power transmission system.Power transmission system can turn the high voltage of power supply Change many different low-voltages needed for discrete devices in system into.The efficiency of power transmission system determines the electricity converted downwards Power loss, and power supply rail number determines the quantity of supported discrete voltage supply or device.
Current power supply technique is faced with following challenge:
One, as the contraction of process interior joint, the efficiency of the reduction of equipment voltage, power Transmission can decrease, make function Rate consumption is bigger.
Two, more power supply rails are added and needs to replicate more Power Supply Assemblies, such as increase number of elements, increasing circuit plate Size, increases system bulk, cost and weight at the number of plies for increasing circuit board.
Three, it due to the limitation of the line-spacing of wiring layer, line width again, needs to increase package dimension.
Therefore, power transfer efficiency how is improved, increases the quantity available of different voltages track, it has also become art technology Personnel's important technological problems urgently to be resolved.
Summary of the invention
In view of prior art described above, the purpose of the present invention is to provide a kind of encapsulation for being integrated with power transmission system The packaging method of part, for solving variety of problems in the prior art.
In order to achieve the above objects and other related objects, the present invention provides a kind of above-mentioned envelope for being integrated with power transmission system The packaging method of piece installing, the packaging method the following steps are included:
1) carrier is provided；
2) using lead key closing process in the carrier surface metal lead wire；
3) active module embedded therein and passive module are set to the carrier to be formed on the surface of the metal lead wire, and in institute It states active module embedded therein and the passive module surface forms metal connecting column；
4) metal lead wire, the active module embedded therein, the passive module and the metal are connected using capsulation material Column encapsulated moulding, and the part capsulation material is removed to expose the metal lead wire and the metal connecting column；
5) wiring layer again is formed on the capsulation material surface, the wiring layer again is by the metal lead wire, described active Module and passive module electrical connection；The active module embedded therein, the passive module and the wiring layer again collectively form power supply Transmission system；The high voltage that the power transmission system is suitable for providing external power supply is converted into multiple and different low-voltages, and A plurality of low voltage power supply track is provided；
6) provide and use electrical chip, by it is described with electrical chip be set to it is described be routed layer surface again, it is described with electrical chip via Multiple dimpling blocks realizations are docked with the low voltage power supply track；
7) carrier is removed, the solder projection being connected with the metal lead wire is formed.
Optionally, further include the steps that forming peeling layer in the carrier surface between step 1) and step 2)；Step 2) In, the metal lead wire is formed in the removing layer surface；In step 3), the active module embedded therein and the passive module are set to The removing layer surface；By removing the peeling layer to remove the carrier in step 7).
Optionally, included the following steps: using lead key closing process in the carrier surface metal lead wire
The position of the metal lead wire 2-1) is needed to form in the carrier surface or is needed to form in the carrier surface The position of the metal lead wire and need to be arranged active module embedded therein and the position of passive module forms virtual weld pad；
2-2) formed on corresponding to the virtual weld pad for needing to form the metal lead wire using lead key closing process The metal lead wire.
Optionally, in step 3), the back side of the back side of the active module embedded therein and the passive module is and the carrier phase In conjunction with faying face.
Optionally, the active module embedded therein includes controller and buck converter；The passive module include capacitor, inductance and Resistance.
Optionally, in step 4), using capsulation material by the metal lead wire, the active module embedded therein, the passive module And the method for the metal connecting column encapsulated moulding includes: compression forming, transfer modling, hydro-forming, vacuum lamination or spin coating.
Optionally, the wiring layer again formed in step 5) includes: metal connecting line, metal plug and is set to the gold Belong to the dielectric layer around line and metal plug, the metal connecting line for realizing the metal lead wire, the active module embedded therein and The electrical connection of the passive module, the metal plug connect for realizing the interlayer between the metal connecting line between each layer It connects.
Optionally, the method for forming the metal connecting line includes at least one of plating, chemical plating and silk-screen printing.
Optionally, the layer surface that is routed again is provided with the bump metal layer being electrically connected with the metal connecting line, the gold Belong to lead, the active module embedded therein, the passive module and described is routed again via the bump metal layer with described with electrical chip Layer is connected.
Optionally, between step 6) and step 7) further include area between the dimpling block of the electricity consumption chip bottom Domain carries out the step of underfill, is fixed on described on the wiring layer again with electrical chip.
Optionally, after the region between the dimpling block described in the electricity consumption chip bottom carries out underfill, further include It is described with capsulation material layer is formed around electrical chip and around the underfill of underfill the step of.
As described above, the packaging method of the packaging part for being integrated with power transmission system of the invention, has below beneficial to effect Fruit:
(1) active 2.5D intermediate plate is formed using existing active component and passive element, then by dimpling block or its Electricity consumption integrated chip on active 2.5D intermediate plate, is obtained three-dimensional stacking structure by its projection cube structure；Wherein, described to use electrical chip It can be specific integrated circuit (Application Specific Integrated Circuit, abbreviation ASIC).
(2) in three-dimensional stacking structure, active 2.5D intermediate plate is closely integrated Yu Yong as power transmission power chip Below electrical chip, solves the problems, such as power transmission.
(3) power transmission system of whole system circuit board is realized by the power transmission chip, the power transmission core Piece includes controller, buck converter (buck converter), capacitor (CAP (3T)), inductance (L (2T)) and resistance, thus Eliminate passive element all on system board.
(4) buck converter in the power transmission chip can produce thousands of low-voltage power transmission tracks (power supply rail), these low-voltage power transmission tracks use electrical chip by the docking of dimpling block.
(5) encapsulating structure of the invention can eliminate encapsulation due to being integrated with the power transmission chip comprising passive element Dead resistance on substrate such as pcb board improves the response time of power control to improve power transmission efficiency.
(6) fidelity is improved by reducing pressure drop and noise, so as to improve the response time.Due to needing less set Surplus is counted, better fidelity performance improvement can be obtained.
Detailed description of the invention
Fig. 1 is shown as the flow diagram of the packaging method of the packaging part for being integrated with power transmission system of the invention.
Fig. 2~Figure 12 is shown as each step in the packaging method of the packaging part for being integrated with power transmission system of the invention Structural schematic diagram.
Component label instructions
11 carriers
12 metal lead wires
13 peeling layers
14 active module embedded thereins
15 passive modules
151 capacitors
152 inductance
16 metal connecting columns
17 capsulation materials
18 wiring layers again
181 metal connecting lines
182 dielectric layers
19 use electrical chip
20 dimpling blocks
21 underfills
22 capsulation material layers
23 solder projections
Specific embodiment
Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification Other advantages and efficacy of the present invention can be easily understood for disclosed content.The present invention can also pass through in addition different specific realities The mode of applying is embodied or practiced, the various details in this specification can also based on different viewpoints and application, without departing from Various modifications or alterations are carried out under spirit of the invention.
Fig. 1 is please referred to Figure 12.It should be noted that diagram provided in the present embodiment only illustrates this in a schematic way The basic conception of invention, though only show in diagram with related component in the present invention rather than package count when according to actual implementation Mesh, shape and size are drawn, when actual implementation form, quantity and the ratio of each component can arbitrarily change for one kind, and its Assembly layout kenel may also be increasingly complex.
Referring to Fig. 1, the present invention provides a kind of packaging method of packaging part for being integrated with power transmission system, the encapsulation Method the following steps are included:
1) carrier is provided；
2) using lead key closing process in the carrier surface metal lead wire；
3) active module embedded therein and passive module are set to the carrier to be formed on the surface of the metal lead wire, and in institute It states active module embedded therein and the passive module surface forms metal connecting column；
4) metal lead wire, the active module embedded therein, the passive module and the metal are connected using capsulation material Column encapsulated moulding, and the part capsulation material is removed to expose the metal lead wire and the metal connecting column；
5) wiring layer again is formed on the capsulation material surface, the wiring layer again is by the metal lead wire, described active Module and passive module electrical connection；The active module embedded therein, the passive module and the wiring layer again collectively form power supply Transmission system；The high voltage that the power transmission system is suitable for providing external power supply is converted into multiple and different low-voltages, and A plurality of low voltage power supply track is provided；
6) provide and use electrical chip, by it is described with electrical chip be set to it is described be routed layer surface again, it is described with electrical chip via Multiple dimpling blocks realizations are docked with the low voltage power supply track；
7) carrier is removed, the solder projection being connected with the metal lead wire is formed.
In step 1), S1 step and Fig. 2 in Fig. 1 are please referred to, a carrier 11 is provided.
As an example, the material of the carrier 11 can be in glass, stainless steel, silicon, silica, metal or ceramics One or more or other similar object.The carrier 11 can be plate.For example, the carrier 11 can be but not only limit In with certain thickness glass circle plate.
Referring to Fig. 3, further including the steps that forming peeling layer 13 on 11 surface of carrier after step 1).
As an example, the peeling layer 13 is for sticking fixed subsequent structure to be formed.Specifically, the peeling layer 13 It can be glue layer or adhesive tape.When the subsequent removal carrier 11, peeling layer 13 also removes together.For example, peeling layer 13 can be with The double faced adhesive tape using heating or UV dispergation, when removing can on one side using UV dispergation another side using heating dispergation, or It is directly torn off using heating dispergation another side on one side, the method that both sides tape releases viscosity is different.Alternatively, peeling layer 13 can also be with It is the sacrificial layer of radium-shine dispergation, after forming this layer of sacrificial layer, it is subsequent to be formed can to stick fixation for cementing on sacrificial layer Structure；When removing, radium-shine removal sacrificial layer can be used, then remove glue again.Sacrificial layer can be heavy using CVD on carrier 11 Product, can also coat LTHC (light to heat) material and obtain, and glue can be removed using chemical reagent.
In step 2), S2 step and Fig. 4 in Fig. 1 are please referred to, using wire bonding (wire bond) technique described 11 surface metal lead 12 of carrier.
It should be noted that when 11 surface of carrier is formed with the peeling layer 13, the metal lead wire 12 and after The structure on the continuous formation mentioned and 11 surface of carrier is both formed in the surface of the peeling layer 13.
As an example, being included the following steps: with lead key closing process in the 11 surface metal lead 12 of carrier
The position of the metal lead wire 12 2-1) is needed to form on 11 surface of carrier or is needed on 11 surface of carrier The position for forming the position of the metal lead wire 12 and needing to be arranged active module embedded therein and passive module forms virtual weld pad and (does not show Out)；
2-2) use lead key closing process shape on corresponding to the virtual weld pad for needing to form the metal lead wire 12 At the metal lead wire 12.
As an example, step 2-1) in, 11 surface of carrier need to form the metal lead wire 12 position or 11 surface of carrier needs to form the position of the metal lead wire 12 and needs to be arranged the position of active module embedded therein and passive module The virtual weld pad is formed to include the following steps:
2-1-1) using metal sputtering or chemical plating in 11 forming metal layer on surface of carrier；
Photoresist layer 2-1-2) is formed in the layer on surface of metal, is formed by exposing, being developed in the photoresist layer Through-hole, the through-hole define the region except the virtual weld pad；
2-1-3) using etching technics removal exposure the metal layer, remove the photoresist layer obtain it is described virtually Weld pad.
It should be noted that the active module embedded therein 14 and the passive module 15 that step 3) is related to can be there are two types of classes Type, front and the back side of a kind of front for the active module embedded therein 14 and the back side and the passive module 15 be equipped with inside it The metal pad that structure is connected, another kind set for the front of the only positive and described passive module 15 of the active module embedded therein 14 There is the metal pad being connected with its internal structure, the back side of the active module embedded therein 14 and the back side of the passive module 15 do not have Metal pad is set.The front in the front and the back side and the passive module 15 of the active module embedded therein 14 described in the active module embedded therein 14 When being equipped with the metal pad being connected with its internal structure with the back side, step 2-1) in, shape is needed on 11 surface of carrier At the metal lead wire 12 position and need to be arranged the position of active module embedded therein and passive module and be formed simultaneously virtual weld pad；When only There is the front of the positive and described passive module 15 of the active module embedded therein 14 to be equipped with the metal pad being connected with its internal structure, When the back side of the i.e. described active module embedded therein 14 and the back side of the passive module 15 are not provided with metal pad, step 2-1) in only need The virtual weld pad is formed in the position that 11 surface of carrier needs to form the metal lead wire 12.
As an example, the material of the metal lead wire 12 may include one of Cu, Al, Ag, Au, Sn, Ni, Ti, Ta Or a variety of or other suitable conductive metallic materials.The material of the virtual weld pad equally may include Cu, Al, Ag, Au, Sn, One of Ni, Ti, Ta or a variety of or other suitable conductive metallic materials.For example, the material of the metal lead wire 12 can be with For Cu, the material of the virtual weld pad can be Ti/Cu.
As an example, the metal lead wire 12 can be vertical column, the metal lead wire 12 can be more.Due to adopting With the routing method of wire bonding, the wire beaten every time is thinner, it is therefore desirable to play a plurality of wire as a gold Belonging to lead 12 in order to be connected with subsequent wiring layer again, i.e., the every metal lead wire 12 may include a plurality of wire, These wires can be used lead key closing process and be bonded on the carrier 11；For example, a plurality of spun gold, copper wire can be beaten at one Or copper-gold alloy silk is as a metal lead wire 12.
In step 3), S1 step and Fig. 5 in Fig. 1 are please referred to, active module embedded therein 14 and passive module 15 are set to institute It states carrier 11 to be formed on the surface of the metal lead wire 12, and in 15 surface shape of the active module embedded therein 14 and the passive module At metal connecting column 16.
As an example, the active module embedded therein 14 may include controller and buck converter, the passive module 15 can be with Including capacitor 151, inductance 152 and resistance (not shown), the active module embedded therein 14 and 152 grades of capacitor 151, inductance institutes Stating the passive modules such as resistance 15 can laterally be arranged in same leveling, convenient for being electrically connected with the wiring layer again that is subsequently formed And layout-design, certainly, the position of the active module embedded therein more than 14 passive module 15 specifically arranged can be according to practical need It is designed, the invention is not limited in this regard.
It should be noted that in the step, the back side of the active module embedded therein 14 and the back side of the passive module 15 be with The faying face that the carrier 11 combines, i.e., the described active module embedded therein 14 and the passive module 15 are face-up placed, the gold Belong to connecting column 16 be connected with the active module embedded therein 14 and the positive weld pad of the passive module 15, in order to subsequent shape At wiring layer again electrical connection.
It should be further noted that when the back side of the active module embedded therein 14 and the back side of the passive module 15 are equipped with When metal pad, alloy-layer can be formed by scaling powder, and using high temperature reflow processes, to realize the active module embedded therein 14 The back side and the metal pad at the back side of the passive module 15 and being welded and fixed for the virtual weld pad, to have described Source module 14 and the passive module 15 are fixed on the carrier 11；The back side and the passive mould when the active module embedded therein 14 It, can be by bindings such as glue or double-sided adhesives by the active module embedded therein 14 and described when the back side of block 15 does not have metal pad Passive module 15 is fixed on the carrier 11.
In step 4), the S4 step and Fig. 6 and Fig. 7 in Fig. 1 are please referred to, using capsulation material 17 by the metal lead wire 12, the active module embedded therein 14, the passive module 15 and 16 encapsulated moulding of metal connecting column, and remove the part plastic packaging Material 17 is to expose the metal lead wire 12 and the metal connecting column 16.
As an example, the techniques such as compression forming, transfer modling, hydro-forming, vacuum lamination or spin coating can be used institute State metal lead wire 12, the active module embedded therein 14, the passive module 15 and 16 encapsulated moulding of metal connecting column.The plastic packaging Material 17 can be epoxylite, liquid-type thermosetting epoxy resin, plastic molding compound or the like.
As an example, can be using one of mechanical lapping, chemical polishing or etching or the modeling of a variety of removal parts Closure material 17.
In step 5), S5 step and Fig. 8 in Fig. 1 are please referred to, forms wiring layer again on 17 surface of capsulation material 18, the metal lead wire 12, the active module embedded therein 14 and the passive module 15 are electrically connected by the wiring layer again 18；It is described to have Source module 14, the passive module 15 and the wiring layer again 18 collectively form power transmission system；The power transmission system High voltage suitable for providing external power supply is converted into multiple and different low-voltages, and provides a plurality of low voltage power supply track.
It should be noted that " high voltage " described herein refers to the electricity higher than the subsequent voltage needed for electrical chip mentioned Pressure, " low-voltage " described herein refer to the voltage lower than " high voltage ", that is, the voltage needed for electrical chip.
As an example, the wiring layer again 18 includes: metal connecting line 182, metal plug and is set to the metal connecting line 182 and metal plug around dielectric layer 181, the metal connecting line 182 is for realizing the metal lead wire 12, the active mould The electrical connection of block 14 and the passive module 15, the metal plug for realizing the metal connecting line 182 between each layer it Between interlayer connection.
As an example, the material of the metal connecting line 182 includes one of Cu, Al, Ag, Au, Sn, Ni, Ti, Ta or more Kind or other suitable conductive metallic materials.For example, the metal connecting line 182 can be Cu line, the seed layer of production Cu line can Think Ti/Cu layers.The method for forming the metal connecting line 182 may include electrolysis plating, chemical plating, one of silk-screen printing or A variety of or other suitable metal deposition process.Laser drill, machine drilling, reactive ion etching, nanometer pressure can be first passed through Print or other suitable boring methods form through-hole in the dielectric layer 181, then fill metal material in the through-hole again The metal plug can be formed；The material of the metal plug can be solder or Cu, and fill method can be electrolysis plating, change Learn plating, silk-screen printing, wire bonding or other suitable methods for filling conductive material in through-holes.
As an example, 18 surface of wiring layer again is provided with the bump metal layer being electrically connected with the metal connecting line 182 (not shown), the metal lead wire 12, the active module embedded therein 14, the passive module 15 and it is subsequent use passed through with electrical chip Be connected by the bump metal layer with the wiring layer again 18, specifically, the metal lead wire 12, the active module embedded therein 14, The passive module 15 and with electrical chip via the metal connecting line in the bump metal layer and the wiring layer again 18 182 are connected.
In step 6), S6 step and Fig. 9 in Fig. 1 are please referred to, provides with electrical chip 19, is set described with electrical chip 19 It is placed in 18 surface of wiring layer again, it is described to be realized and the low voltage power supply track with electrical chip 19 via multiple dimpling blocks 20 Docking.
As an example, electrical chip can be used by described using techniques such as ultrasonic bond, thermocompression bonding or common Reflow Solderings 19 are welded on the wiring layer 18 again via multiple dimpling blocks 20.
As an example, described can be but be not limited only to specific integrated circuit naked core (ASIC Die) with electrical chip 19.
Referring to Fig. 10, further including the area between the dimpling block 20 with 19 bottom of electrical chip after step 6) Domain carries out the step of underfill, is fixed on described on the wiring layer 18 again with electrical chip 19.Specifically, by institute The area filling underfill 21 stated between the dimpling block 20 with 19 bottom of electrical chip consolidates the electrical chip 19 Due on the wiring layer again 18, the packing material can be but be not limited only to underfill.
Specifically, the underfill can for capillary underfill (CUF, Capillary Underfill) or at Profile material underfill (MUF, Molding UnderFill).
As an example, after the region between the dimpling block 20 described in 19 bottom of electrical chip carries out underfill, It further include described with around electrical chip 19 and 21 surrounding of underfill of underfill forms the step of capsulation material layer 22 Suddenly.
In step 7), please refer to the S7 step and Figure 11 and Figure 12 in Fig. 1, remove the carrier 11, formed with it is described The solder projection 23 that metal lead wire 12 is connected.
As an example, can using mechanical lapping, chemical polishing, etching, ultraviolet light removing, one of mechanical stripping or A variety of removing carriers 11；It preferably, can be by removing the peeling layer 13 to remove the carrier in the present embodiment 11.The structure removed after the carrier 11 is as shown in figure 11.
As an example, the solder projection 23 can be solder ball, it is preferable that in the present embodiment, the solder projection 23 Using ball grid array structure (Ball Grid Array, BGA).The packaging part passes through the solder projection 23 and external power supply It is connected.The structure for forming the solder projection 23 being connected with the metal lead wire 12 is as shown in figure 12.
In conclusion the present invention provides a kind of packaging method of packaging part for being integrated with power transmission system, the encapsulation Method includes the following steps: 1) to provide a carrier；2) using electroplating technology in the carrier surface metal lead wire；3) by active mould Block and passive module are set to the carrier and are formed on the surface of the metal lead wire, and in the active module embedded therein and the nothing Source module surface forms metal connecting column；4) use capsulation material by the metal lead wire, the active module embedded therein, the passive mould Block and the metal connecting column encapsulated moulding, and the part capsulation material is removed to expose the metal lead wire and the gold Belong to connecting column；5) wiring layer again is formed on the capsulation material surface, the wiring layer again is by the metal lead wire, described active Module and passive module electrical connection；The active module embedded therein, the passive module and the wiring layer again collectively form power supply Transmission system；The high voltage that the power transmission system is suitable for providing external power supply is converted into multiple and different low-voltages, and A plurality of low voltage power supply track is provided；6) provide and use electrical chip, by it is described with electrical chip be set to it is described be routed layer surface again, institute It states and is realized with electrical chip via multiple dimpling blocks and docked with the low voltage power supply track；7) remove the carrier, formed with The solder projection that the metal lead wire is connected.The invention has the following advantages: (1) uses existing active component and nothing Source element forms active 2.5D intermediate plate, then passes through dimpling block or other projection cube structures for electricity consumption integrated chip in active 2.5D On intermediate plate, three-dimensional stacking structure is obtained；Wherein, described to can be specific integrated circuit (Application with electrical chip Specific Integrated Circuit, abbreviation ASIC)；(2) in three-dimensional stacking structure, active 2.5D intermediate plate conduct Power transmission power chip is closely integrated in electricity consumption beneath chips, solves the problems, such as power transmission；(3) whole system electricity The power transmission system of road plate is realized that the power transmission chip includes controller, decompression transformation by the power transmission chip Device (buck converter), capacitor (CAP (3T)), inductance (L (2T)) and resistance, to eliminate nothing all on system board Source element；(4) buck converter in the power transmission chip can produce thousands of low-voltage power transmission tracks and (supply Electric rail), these low-voltage power transmission tracks use electrical chip by the docking of dimpling block；(5) encapsulating structure of the invention due to It is integrated with the power transmission chip comprising passive element, the dead resistance on package substrate such as pcb board can be eliminated, to mention High power transmission efficiency, improves the response time of power control；(6) fidelity is improved by reducing pressure drop and noise, So as to improve the response time.Due to needing less design margin, better fidelity performance improvement can be obtained.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe The personage for knowing this technology all without departing from the spirit and scope of the present invention, carries out modifications and changes to above-described embodiment.Cause This, institute is complete without departing from the spirit and technical ideas disclosed in the present invention by those of ordinary skill in the art such as At all equivalent modifications or change, should be covered by the claims of the present invention.

Claims (10)

1. a kind of packaging method for the packaging part for being integrated with power transmission system, which comprises the following steps:
1) carrier is provided；
2) using lead key closing process in the carrier surface metal lead wire；
3) active module embedded therein and passive module are set to the carrier to be formed on the surface of the metal lead wire, and had described Source module and the passive module surface form metal connecting column；
4) metal lead wire, the active module embedded therein, the passive module and the metal connecting column are sealed using capsulation material Type is dressed up, and removes the part capsulation material to expose the metal lead wire and the metal connecting column；
5) in capsulation material surface formation, wiring layer, the wiring layer again include metal connecting line, metal plug and setting again Dielectric layer around the metal connecting line and metal plug, the metal connecting line for realizing the metal lead wire, described have The electrical connection of source module and the passive module, the metal plug is for realizing between the metal connecting line between each layer Interlayer connection；The active module embedded therein, the passive module and the wiring layer again collectively form power transmission system；The power supply The high voltage that Transmission system is suitable for providing external power supply is converted into multiple and different low-voltages, and provides a plurality of low voltage power supply Track；
6) provide and use electrical chip, by it is described with electrical chip be set to it is described be routed layer surface again, it is described with electrical chip via multiple The realization of dimpling block is docked with the low voltage power supply track；
7) carrier is removed, the solder projection being connected with the metal lead wire is formed.
2. the packaging method of the packaging part according to claim 1 for being integrated with power transmission system, it is characterised in that: step 1) further include the steps that forming peeling layer in the carrier surface between step 2)；In step 2), the metal lead wire is formed In the removing layer surface；In step 3), the active module embedded therein and the passive module are set to the removing layer surface；Step 7) by removing the peeling layer to remove the carrier in.
3. the packaging method of the packaging part according to claim 1 for being integrated with power transmission system, it is characterised in that: step 2) in, included the following steps: using lead key closing process in the carrier surface metal lead wire
The position of the metal lead wire 2-1) is needed to form in the carrier surface or is needed to form in the carrier surface described The position of metal lead wire and need to be arranged active module embedded therein and the position of passive module forms virtual weld pad；
Described in 2-2) being formed on corresponding to the virtual weld pad for needing to form the metal lead wire using lead key closing process Metal lead wire.
4. the packaging method of the packaging part according to claim 1 for being integrated with power transmission system, it is characterised in that: step 3) in, the back side of the back side of the active module embedded therein and the passive module is the faying face combined with the carrier.
5. the packaging method of the packaging part according to claim 1 for being integrated with power transmission system, it is characterised in that: described Active module embedded therein includes controller and buck converter；The passive module includes capacitor, inductance and resistance.
6. the packaging method of the packaging part according to claim 1 for being integrated with power transmission system, it is characterised in that: step 4) in, the metal lead wire, the active module embedded therein, the passive module and the metal connecting column are encapsulated using capsulation material Molding method includes: compression forming, transfer modling, hydro-forming, vacuum lamination or spin coating.
7. the packaging method of the packaging part according to claim 1 for being integrated with power transmission system, it is characterised in that: formed The method of the metal connecting line includes at least one of plating, chemical plating and silk-screen printing.
8. the packaging method of the packaging part according to claim 1 for being integrated with power transmission system, it is characterised in that: described Be routed layer surface again and be provided with the bump metal layer being electrically connected with the metal connecting line, the metal lead wire, the active module embedded therein, The passive module and described it is connected via the bump metal layer with the wiring layer again with electrical chip.
9. the packaging method of the packaging part according to claim 1 for being integrated with power transmission system, it is characterised in that: step 6) between step 7) further include step that region between the dimpling block of the electricity consumption chip bottom carries out underfill Suddenly, it is fixed on described on the wiring layer again with electrical chip.
10. the packaging method of the packaging part according to claim 1 for being integrated with power transmission system, it is characterised in that: It further include described with around electrical chip after region between dimpling block described in the electricity consumption chip bottom carries out underfill And the step of capsulation material layer is formed around the underfill of underfill.
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CN112243317B (en) * 2019-07-18 2022-01-18 欣兴电子股份有限公司 Circuit board structure and manufacturing method thereof
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