CN106783632B - A kind of packaging method and triode of triode - Google Patents
A kind of packaging method and triode of triode Download PDFInfo
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- CN106783632B CN106783632B CN201611202117.3A CN201611202117A CN106783632B CN 106783632 B CN106783632 B CN 106783632B CN 201611202117 A CN201611202117 A CN 201611202117A CN 106783632 B CN106783632 B CN 106783632B
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 50
- 238000000034 method Methods 0.000 title claims abstract description 46
- 239000002131 composite material Substances 0.000 claims abstract description 28
- 238000003466 welding Methods 0.000 claims abstract description 23
- 238000012545 processing Methods 0.000 claims abstract description 18
- 238000005553 drilling Methods 0.000 claims abstract description 9
- 238000007747 plating Methods 0.000 claims description 25
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 20
- 229910052802 copper Inorganic materials 0.000 claims description 18
- 239000010949 copper Substances 0.000 claims description 18
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 15
- 229910052718 tin Inorganic materials 0.000 claims description 15
- 239000002184 metal Substances 0.000 claims description 13
- 229910052751 metal Inorganic materials 0.000 claims description 13
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 6
- 239000000853 adhesive Substances 0.000 claims description 6
- 230000001070 adhesive effect Effects 0.000 claims description 6
- 239000006071 cream Substances 0.000 claims description 6
- 239000003292 glue Substances 0.000 claims description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 6
- 229910052737 gold Inorganic materials 0.000 claims description 6
- 239000010931 gold Substances 0.000 claims description 6
- 238000003384 imaging method Methods 0.000 claims description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 3
- 230000005611 electricity Effects 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 239000004332 silver Substances 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 239000011135 tin Substances 0.000 claims description 3
- 239000011133 lead Substances 0.000 claims description 2
- 230000000717 retained effect Effects 0.000 claims description 2
- 238000009413 insulation Methods 0.000 claims 1
- 239000000463 material Substances 0.000 description 12
- 230000008569 process Effects 0.000 description 12
- 238000010586 diagram Methods 0.000 description 10
- 238000005538 encapsulation Methods 0.000 description 9
- 239000000956 alloy Substances 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 4
- 230000006870 function Effects 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 239000007787 solid Substances 0.000 description 3
- 239000011889 copper foil Substances 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000009833 condensation Methods 0.000 description 1
- 230000005494 condensation Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005868 electrolysis reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000006116 polymerization reaction Methods 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 239000002023 wood Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
- H01L23/49844—Geometry or layout for devices being provided for in H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66272—Silicon vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/732—Vertical transistors
- H01L29/7325—Vertical transistors having an emitter-base junction leaving at a main surface and a base-collector junction leaving at a peripheral surface of the body, e.g. mesa planar transistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Wire Bonding (AREA)
Abstract
The embodiment of the invention discloses a kind of packaging method of triode and triodes, and the occupied space for solving existing triode is big, the low problem of packaging efficiency.This method comprises: providing carrier, and surface metal-layer is covered at least one face of the carrier；In the line pattern region overlay etchant resist of the surface metal-layer；The logicalnot circuit graphics field of the surface metal-layer is electroplated, at least one first pad is formed；The welding chip at least one described first pad；The second pad is welded on the chip forms triode template；Plastic packaging processing is carried out to the triode template using composite material；The drilling blind hole in the vertical direction of second pad and at least one the first pad, and the blind hole is processed into metalized blind vias；Route closed circuit is formed by graphic making to the metalized blind vias, encapsulates out triode.
Description
Technical field
The present invention relates to triode fields, and in particular to a kind of packaging method and triode of triode.
Background technique
As electronic product is to miniaturization, integrated, universalness development, three poles used for electronic product inside
Pipe also minimizes therewith.
Triode uses conventional package mode at present, such as: pass through collect money from the audience (full name in English: Wire bond, abbreviation: WB)
Chip (full name in English: Chip) is packaged into the triode with certain function by mode.
But the electronic product for the miniaturization that certain triodes are integrated, it is encapsulated out using traditional routing mode
Triode, occupied space is big, and packaging efficiency is low.
Summary of the invention
The embodiment of the invention provides a kind of packaging method of triode and triodes, for solving accounting for for existing triode
It is big with space, the low problem of packaging efficiency.
First aspect present invention provides a kind of packaging method of triode, comprising:
Carrier is provided, and covers surface metal-layer at least one face of the carrier；
In the line pattern region overlay etchant resist of the surface metal-layer；
The logicalnot circuit graphics field of the surface metal-layer is electroplated, at least one first pad is formed；
The welding chip at least one described first pad；
At least two second pads of welding form triode template on the chip；
Plastic packaging processing is carried out to the triode template using composite material；
The drilling blind hole in the vertical direction of second pad and at least one the first pad, and the blind hole is processed into
Metalized blind vias；
Route closed circuit is formed by graphic making to the metalized blind vias, encapsulates out triode.
In some possible implementations, the line pattern region overlay etchant resist packet in the surface metal-layer
It includes:
Etchant resist is coated on the surface metal-layer；
By exposure and imaging step, the etchant resist of the logicalnot circuit graphics field is removed, covers the etchant resist retained
Cover the line pattern region.
It is described at least one described first pad before welding chip in some possible implementations, it is described
Packaging method further include:
Remove the etchant resist in the line pattern region.
In some possible implementations, the welding chip at least one described first pad includes:
The chip placement at least one described first pad, and use tin cream, tin plating, metal bonding, conductive adhesive
At least one of mode the chip is welded at least one described first pad.
In some possible implementations, second pad that welds on the chip forms triode template packet
It includes:
The target area of the chip is electroplated, the second pad is formed.
In some possible implementations, the vertical direction in second pad and at least one the first pad
Upper drilling blind hole includes:
By the way of laser blind hole in the vertical direction of second pad and at least one the first pad drilling blind hole.
It is described the blind hole is processed into metalized blind vias to include:
Using electroless copper plating, the blind hole is processed into institute by least one of electro-coppering, sputtering copper, conductive copper glue mode
State metalized blind vias.
It is described that the metalized blind vias is closed back by graphic making formation route in some possible implementations
After road, the packaging method further include:
Mold is added in the composite material, and carries out plastic packaging processing, cuts away extra composite material.
In some possible implementations, the packaging method further include:
Target electronic component is welded at least one first pad, wherein the target electronic component includes electricity
At least one of resistance, capacitor.
Second aspect of the present invention provides a kind of triode, and the triode is to utilize above-mentioned first aspect or first aspect
In any one packaging method it is packaged go out triode.
As can be seen from the above technical solutions, the embodiment of the present invention has the advantage that
Unlike the prior art, replace the mode of traditional routing to encapsulate triode, connected using welding or blind hole
By chip and pad solder, and by chip package at the triode with certain function, the triode encapsulated out accounts for the mode connect
Small with space, entire process flow is simple, effectively improves the packaging efficiency of triode.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for
For those skilled in the art, without creative efforts, it can also be obtained according to these attached drawings other attached
Figure.
Fig. 1 is one embodiment schematic diagram of the packaging method of triode in the embodiment of the present invention；
Fig. 2 a is a structural schematic diagram for covering surface metal-layer in the embodiment of the present invention on carrier；
Fig. 2 b is a structural schematic diagram for covering etchant resist in the embodiment of the present invention on surface metal-layer；
Fig. 2 c is a structural schematic diagram of the welding chip on the first pad in the embodiment of the present invention；
Fig. 2 d is a structural schematic diagram for welding the second pad in the embodiment of the present invention on chip；
Fig. 2 e is a structural schematic diagram for carrying out plastic packaging processing in the embodiment of the present invention to triode template；
Fig. 2 f is the structural schematic diagram that metalized blind vias is formed in the embodiment of the present invention；
Fig. 3 is a structural schematic diagram of triode in the embodiment of the present invention；
Fig. 4 is another structural schematic diagram of triode in the embodiment of the present invention.
Specific embodiment
The embodiment of the invention provides a kind of packaging method of triode and triodes, for solving accounting for for existing triode
It is big with space, the low problem of packaging efficiency.
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, those skilled in the art's every other implementation obtained without creative efforts
Example, shall fall within the protection scope of the present invention.
Description and claims of this specification and term " first ", " second ", " third ", " in above-mentioned attached drawing
The (if present)s such as four " are to be used to distinguish similar objects, without being used to describe a particular order or precedence order.It should manage
The data that solution uses in this way are interchangeable under appropriate circumstances, so that the embodiments described herein can be in addition to illustrating herein
Or the sequence other than the content of description is implemented.In addition, term " includes " and " having " and their any deformation, it is intended that
Cover it is non-exclusive include, for example, containing the process, method, system, product or equipment of a series of steps or units need not limit
In step or unit those of is clearly listed, but may include be not clearly listed or for these process, methods, produce
The other step or units of product or equipment inherently.
Referring to Fig. 1, in the embodiment of the present invention packaging method of triode one embodiment schematic diagram, the embodiment
Detailed process is as follows:
Step 101 provides carrier, and covers surface metal-layer at least one face of the carrier.
Before encapsulating triode, the carrier of encapsulation triode is provided first, wherein the carrier has rippability, side
Continue removing after an action of the bowels, therefore carrier is considered as one of triode encapsulation process medium, and at least one face of carrier
Cover surface metal-layer, wherein the carrier side that cover surface metal-layer can be selected according to actual needs, do not do and have herein
Body limits.Under normal circumstances, which is specially copper foil layer, it is of course also possible to be other metal material layers, herein not
It is specifically limited.
Step 102, the line pattern region overlay etchant resist in the surface metal-layer.
In the embodiment of the present invention, the region where the surface metal-layer includes line pattern region and logicalnot circuit graph area
Domain, wherein need in the line pattern region overlay etchant resist, since etchant resist is a kind of high molecular compound, it passes through
Polymerization reaction can be generated after exposure (such as: ultraviolet irradiation) form a kind of stable substance be attached to line pattern area
Domain reaches the function of stopping plating and etching, thus play the role of protection circuit graphics field, in practical applications, the line
The position of road graphics field is related to the form of specific product, structure and route design etc., does not do and specifically repeats herein.
It should be noted that the etchant resist can be dry film, it is also possible to wet film, can also be other with etch-resistance
Material, be not specifically limited herein.
In practical applications, there are many kinds of the modes of the line pattern region overlay etchant resist of the surface metal-layer,
In, it include: on the surface in the line pattern region overlay etchant resist of surface metal-layer in some possible implementations
Etchant resist is coated on metal layer；By exposure and imaging step, the etchant resist of the logicalnot circuit graphics field is removed, makes to retain
Etchant resist cover the line pattern region.
The logicalnot circuit graphics field of the surface metal-layer is electroplated in step 103, forms at least one first weldering
Disk.
In the embodiment of the present invention, the logicalnot circuit graphics field of surface metal-layer is insulated heat, in surface metal-layer
Logicalnot circuit image-region is electroplated out at least one first pad, the material of the first pad be copper, nickel, gold, silver, tin, in lead extremely
A kind of at least one of few or its alloy.Wherein, the height of the first pad is related to position with actual product, does not do herein
It is specific to limit.
It should be noted that the first pad in the embodiment of the present invention is used to distinguish the second following pads, first weldering
The material of disk and the second following pads can be identical, can also be different, is not specifically limited herein.
Step 104, the welding chip at least one described first pad.
It in practical applications, may be horizontal position relationship between the pad of triode, it is also possible to vertical positional relationship,
In some possible implementations, at least one first pad before welding chip, need to remove the line pattern
The etchant resist in region, the convenient welding chip on first pad, wherein the chip with the upper surface of pad solder and/or
Lower surface carries pad.
In some possible implementations, welding chip includes: described at least one at least one first pad
Chip placement on a first pad, and use at least one of tin cream, tin plating, metal bonding, conductive adhesive mode by institute
Chip is stated to be welded at least one described first pad.
It should be noted that except at least one welding manner such as above-mentioned tin cream, tin plating, metal bonding, conductive adhesive or
Outside person's a combination thereof mode, it can also be other welding manners, be not specifically limited herein.
Step 105 welds the second pad formation triode template on the chip.
At this at least one first pad after welding chip, continue to weld the second pad on the chip, thus shape
At triode template, wherein the material of second pad is at least one of copper, nickel, gold, silver, tin, lead or its alloy
At least one of.Wherein, the height of the second pad is related to position with actual product, is not specifically limited herein.If first
Pad at least there are two, then need to weld at least one second pad on chip, if the first pad at least one, need
At least two second pads are welded on chip.
In some possible implementations, welding the second pad on the chip and forming triode template includes: pair
The target area of the chip is electroplated, and the second pad is formed, to form the triode template.Wherein, the target
The setting in region is related to actual product, and the mode of the plating can be physics plating or electroless copper plating plating etc., in addition,
Other than plating mode, at least one of tin cream, tin plating, metal bonding, conductive adhesive mode can also be used second
Pad solder, it is, of course, also possible to be other welding manners, is not specifically limited herein in the target area of the chip.
Step 106 carries out plastic packaging processing to the triode template using composite material.
In the embodiment of the present invention, need to carry out plastic packaging processing to triode template using composite material, to reach protection
The effect of first pad, the second pad and chip, wherein the composite material is solid capsulation material, powder capsulation material, liquid
At least one of resin, semi-solid preparation resin, pure glue or a combination thereof material.
In some possible implementations, carrying out plastic packaging processing to the triode template using composite material includes:
Mold is added in the composite material, and carries out plastic packaging processing.
Step 107, the drilling blind hole in the vertical direction of second pad and at least one the first pad, and will be described blind
Hole is processed into metalized blind vias.
In some possible implementations, bored in the vertical direction of second pad and at least one the first pad
Blind hole include: bored in the vertical direction of second pad and at least one the first pad by the way of laser blind hole it is blind
Hole.
It is described that the blind hole is processed into metalized blind vias includes: electro-coppering, sputtering copper, conductive copper using electroless copper plating
The blind hole is processed into the metalized blind vias by least one of glue mode or a combination thereof mode.
Step 108 forms route closed circuit by graphic making to the metalized blind vias, encapsulates out triode.
In the embodiment of the present invention, closed circuit is formed by graphic making to the metalized blind vias, inductance is formed, to seal
Take on triode.
In some possible implementations, to the metalized blind vias by graphic making formed route closed circuit it
Afterwards, mold is added in the composite material, and carries out plastic packaging processing, cut away extra composite material.
In practical applications, after by the way that mold is added to the composite material, plastic packaging processing is carried out according to the size of the mold,
And extra composite material is cut away according to the size structure of diode, to complete the encapsulation of diode, wherein the composite wood
Material is at least one of resin, pure glue or prepreg or its composition material.
In some possible implementations, target electronic component can also be welded on pad, wherein the target
Electronic component includes at least one of resistance, capacitor.
In practical applications, during encapsulating triode, pass through the welding kesistance at least one first pad, electricity
Hold, connector, the electronic components such as clockwork spring, to effectively improve the integrated level of triode, in addition, the target electronic component with
Actual product is related, and the number etc. of electronic component and electronic component can be determined according to actual product, does not do herein specific
It limits.
The technical solution that embodiment provides to facilitate the understanding of the present invention is situated between below by a specific embodiment
Continue the encapsulation process of triode.
Fig. 2 a is please referred to, carrier 10 is provided, and covers the formation of surface metal-layer 11 on a face of the carrier 10 and covers copper
Plate, wherein a substrate of the copper-clad plate as encapsulation triode, and the carrier has rippability, for when three poles of completion
After the encapsulation of pipe, the carrier is peeled off.Since the cost of copper metal is low, which is generally copper foil layer, when
So, other metal layers be can also be, be not specifically limited herein.
Fig. 2 b is please referred to, after processing copper-clad plate, etchant resist 12 is covered on the surface metal-layer 11, wherein should
Etchant resist can be dry film, be also possible to wet film, can also be the material of other corrosion stabilities, since etchant resist is with photosensitive and anti-
The effect of corrosion, by exposure and imaging step, so that line pattern is transferred on etchant resist, it will be on the surface metal-layer 11
The etchant resist 12 of logicalnot circuit graphics field removes, thus the only etchant resist 12 of reserved line graphics field, then in surface gold
At least one first pad 13 is electroplated out in the logicalnot circuit graphics field for belonging to layer, wherein the size of the first pad, height, material with
Actual product is related, is not specifically limited herein, in addition, the mode of plating can be physics plating or electroless copper plating plating,
The principle being specifically electroplated is utilized by plating a thin layer metal or alloy on the surface metal-layer of logicalnot circuit graphics field
The technique that electrolysis makes the surface of metal or alloy adhere to layer of metal film.
Please refer to Fig. 2 c, remove the etchant resist 12 in the line pattern region of surface metal-layer 11, and at this at least one
Welding chip 14 on one pad 13, wherein the chip carries pad, is not shown in Fig. 2 c.In practical applications, using tin cream,
Chip 14 is welded on this at least one by least one of tin plating, metal bonding, conductive adhesive mode or combination
On first pad 13.
Fig. 2 d is please referred to, the second pad 15 is welded on the chip 14 and forms triode template, wherein detailed process are as follows:
Target area on the chip 14 is electroplated, which is set to actual product correlation, the second pad 15 is formed,
Wherein, the mode of plating can be physics plating or electroless copper plating plating etc., be not specifically limited herein.It needs to illustrate
Be, as shown in Figure 2 d, if the first pad 13 at least there are two, need to weld at least one second pad 15 on chip.If
First pad 13 at least one, then need on chip weld at least two second pads 15, it is similar to Fig. 2 d, it is not shown
Out.
Fig. 2 e is please referred to, plastic packaging processing is carried out to the triode template using composite material 16.Detailed process are as follows: will answer
Mold is added in condensation material 16, and carries out plastic packaging processing, according to the required size of triode, cuts away extra composite material.Its
In, which can be solid, and perhaps liquid capsulation material is for example: pure glue or prepreg etc..
Fig. 2 f is please referred to, for the connection between route, is needed in second pad 15 and at least one first pad 13
Vertical direction on drilling blind hole 17, in practical applications, can by the way of laser blind hole drilling blind hole 17, due to triode mould
Plate itself is insulated heat, and heavy copper and plating can be carried out to the blind hole, the blind hole bored is metallized, and to the metallization
Blind hole forms route closed circuit by graphic making, forms inductance, mold then is added in the composite material, and carry out plastic packaging
Processing, according to the required size of diode, cuts away extra composite material, it should be noted that can also be using machinery
Mode evens the composite material out, or polishes the composite material by the way of polishing, is not specifically limited herein.Then
Carrier 10 is removed, to complete the encapsulation of triode.
In practical applications, the embodiment of the present invention also provides a kind of triode, which is by above-mentioned shown in FIG. 1
The triode that packaging method encapsulates out.
As shown in figure 3, the triode encapsulated out for packaging method shown in FIG. 1, the triode at least there are three pad,
In, the first pad 301 is located at lower part, and at least two second pads 302 are located at top, the welding chip on the first pad 301
303, which is welded at least two second pads 302 on one side, is then carried out at plastic packaging by composite material 305
Reason, and blind hole is drilled out by the way of laser blind hole in the vertical direction of the first pad 301 and the second pad 302, and to blind
Hole metallization does graphics process to metalized blind vias 304 to form metalized blind vias 304, realizes the connection of route.When
So, in practical applications, other electronic components such as more chips or resistance, capacitor can also be welded on triode,
It is not specifically limited herein, then carries out plastic packaging again by composite material 305, for protecting the first pad 301, the second pad
302 and chip 303.
As described in Figure 4, another triode encapsulated out for packaging method shown in FIG. 1, wherein the triode is at least
Three pads, wherein at least two first pads 401 are located in same level, or close in same level, at least
Welding chip 402 on two the first pads 401.In practical applications, more cores can also be welded on other first pads
Other electronic components such as piece, or welding capacitor, resistance, to improve the integrated level of triode encapsulation.The chip 402
It is welded at least one second pad 403 on one side, plastic packaging processing is then carried out using composite material 405, and in the first pad 401
With drill out blind hole in the vertical direction of the second pad 403 by the way of laser blind hole, and metallize to form gold to blind hole
Categoryization blind hole 404, and graphics process is done to metalized blind vias, realize the connection of route.Then again by composite material 405 into
Row plastic packaging, for protecting the first pad 401 and chip 402 and the second pad 403.
It should be noted that the size of the first pad needed for encapsulation triode and the second pad can be identical, it can also not
Together, three pads are not specifically limited herein not necessarily on same horizontal line.
Show three that the packaged triode out of packaging method shown in FIG. 1 encapsulates out than conventional method through test data
Pole pipe is substantially reduced in height, and the cost used is significantly reduced, and is a test data table such as following table:
It is apparent to those skilled in the art that for convenience and simplicity of description, the system of foregoing description,
The specific work process of device and unit, can refer to corresponding processes in the foregoing method embodiment, and details are not described herein.
In several embodiments provided herein, it should be understood that disclosed system, device and method can be with
It realizes by another way.For example, the apparatus embodiments described above are merely exemplary, for example, the unit
It divides, only a kind of logical function partition, there may be another division manner in actual implementation, such as multiple units or components
It can be combined or can be integrated into another system, or some features can be ignored or not executed.Another point, it is shown or
The mutual coupling, direct-coupling or communication connection discussed can be through some interfaces, the indirect coupling of device or unit
It closes or communicates to connect, can be electrical property, mechanical or other forms.
The unit as illustrated by the separation member may or may not be physically separated, aobvious as unit
The component shown may or may not be physical unit, it can and it is in one place, or may be distributed over multiple
In network unit.It can select some or all of unit therein according to the actual needs to realize the mesh of this embodiment scheme
's.
It, can also be in addition, the functional units in various embodiments of the present invention may be integrated into one processing unit
It is that each unit physically exists alone, can also be integrated in one unit with two or more units.Above-mentioned integrated list
Member both can take the form of hardware realization, can also realize in the form of software functional units.
If the integrated unit is realized in the form of SFU software functional unit and sells or use as independent product
When, it can store in a computer readable storage medium.Based on this understanding, technical solution of the present invention is substantially
The all or part of the part that contributes to existing technology or the technical solution can be in the form of software products in other words
It embodies, which is stored in a storage medium, including some instructions are used so that a computer
Equipment (can be personal computer, server or the network equipment etc.) executes the complete of each embodiment the method for the present invention
Portion or part steps.And storage medium above-mentioned includes: USB flash disk, mobile hard disk, read-only memory (ROM, Read-Only
Memory), random access memory (RAM, Random Access Memory), magnetic or disk etc. are various can store journey
The medium of sequence code.
The above, the above embodiments are merely illustrative of the technical solutions of the present invention, rather than its limitations；Although referring to before
Stating embodiment, invention is explained in detail, those skilled in the art should understand that: it still can be to preceding
Technical solution documented by each embodiment is stated to modify or equivalent replacement of some of the technical features；And these
It modifies or replaces, the spirit and scope for technical solution of various embodiments of the present invention that it does not separate the essence of the corresponding technical solution.
Claims (7)
1. a kind of packaging method of triode characterized by comprising
Carrier is provided, and covers surface metal-layer at least one face of the carrier；
In the line pattern region overlay etchant resist of the surface metal-layer；
The logicalnot circuit graphics field of the surface metal-layer is electroplated, at least one first pad is formed；First weldering
Disk be at least one of copper, nickel, gold, silver, tin, lead, wherein the logicalnot circuit graphics field of the surface metal-layer be insulation every
Heat；
The welding chip at least one described first pad；
The second pad is welded on the chip forms triode template；
Plastic packaging processing is carried out to the triode template using composite material；
The drilling blind hole in the vertical direction of second pad and at least one the first pad, and the blind hole is processed into metal
Change blind hole；
Target electronic component is welded at least one first pad, wherein the target electronic component includes resistance, electricity
At least one of hold；
Route closed circuit is formed by graphic making to the metalized blind vias, inductance is formed, to encapsulate out triode.
2. packaging method according to claim 1, which is characterized in that the line pattern area in the surface metal-layer
Domain covers etchant resist
Etchant resist is coated on the surface metal-layer；
By exposure and imaging step, the etchant resist of the logicalnot circuit graphics field is removed, makes the etchant resist retained covering institute
State line pattern region.
3. packaging method according to claim 2, which is characterized in that described to be welded at least one described first pad
Before chip, the packaging method further include:
Remove the etchant resist in the line pattern region.
4. packaging method according to claim 1, which is characterized in that described to be welded at least one described first pad
Chip includes:
The chip placement at least one described first pad, and using in tin cream, tin plating, metal bonding, conductive adhesive
The chip is welded at least one described first pad by least one mode.
5. packaging method according to claim 1, which is characterized in that described to be bored in the vertical direction of second pad
Blind hole includes:
By the way of laser blind hole in the vertical direction of second pad drilling blind hole；
It is described the blind hole is processed into metalized blind vias to include:
Using electroless copper plating, the blind hole is processed into the gold by least one of electro-coppering, sputtering copper, conductive copper glue mode
Categoryization blind hole.
6. packaging method according to claim 1, which is characterized in that described to pass through graphic making to the metalized blind vias
It is formed after route closed circuit, the packaging method further include:
Mold is added in the composite material, and carries out plastic packaging processing, cuts away extra composite material.
7. a kind of triode, which is characterized in that the triode is using the claims 1 to any in claim 6
A kind of packaged triode out of packaging method.
Priority Applications (8)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611202117.3A CN106783632B (en) | 2016-12-22 | 2016-12-22 | A kind of packaging method and triode of triode |
| PCT/CN2017/117770 WO2018113746A1 (en) | 2016-12-22 | 2017-12-21 | Discrete device packaging method and discrete device |
| CN201780077355.2A CN110383437A (en) | 2016-12-22 | 2017-12-21 | A kind of packaging method and diode of diode |
| PCT/CN2017/117747 WO2018113741A1 (en) | 2016-12-22 | 2017-12-21 | Diode encapsulation method and diode |
| CN201780077305.4A CN110268510B (en) | 2016-12-22 | 2017-12-21 | Packaging method of discrete device and discrete device |
| PCT/CN2017/117771 WO2018113747A1 (en) | 2016-12-22 | 2017-12-21 | Triode packaging method and triode |
| CN201780077309.2A CN110268511A (en) | 2016-12-22 | 2017-12-21 | A kind of packaging method and triode of triode |
| US16/900,380 US11296042B2 (en) | 2016-12-22 | 2020-06-12 | Triode packaging method and triode |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611202117.3A CN106783632B (en) | 2016-12-22 | 2016-12-22 | A kind of packaging method and triode of triode |
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| CN106783632A CN106783632A (en) | 2017-05-31 |
| CN106783632B true CN106783632B (en) | 2019-08-30 |
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| WO2018113747A1 (en) * | 2016-12-22 | 2018-06-28 | 深圳中科四合科技有限公司 | Triode packaging method and triode |
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| CN102768960A (en) * | 2011-05-03 | 2012-11-07 | 旭德科技股份有限公司 | Packaging structure and manufacturing method thereof |
| CN103635996A (en) * | 2011-06-30 | 2014-03-12 | 英特尔公司 | Bumpless build-up layer package warpage reduction |
| CN104576421A (en) * | 2013-10-25 | 2015-04-29 | 英飞凌科技股份有限公司 | Semiconductor device and method for manufacturing the semiconductor device |
| CN105336632A (en) * | 2014-08-05 | 2016-02-17 | 英飞凌科技股份有限公司 | Batch process for connecting chips to carrier |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8692135B2 (en) * | 2008-08-27 | 2014-04-08 | Nec Corporation | Wiring board capable of containing functional element and method for manufacturing same |
| CN102751254A (en) * | 2012-07-18 | 2012-10-24 | 日月光半导体制造股份有限公司 | Semiconductor packaging piece, stack packaging piece using semiconductor packaging piece and manufacturing method of semiconductor packaging piece |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102768960A (en) * | 2011-05-03 | 2012-11-07 | 旭德科技股份有限公司 | Packaging structure and manufacturing method thereof |
| CN103635996A (en) * | 2011-06-30 | 2014-03-12 | 英特尔公司 | Bumpless build-up layer package warpage reduction |
| CN104576421A (en) * | 2013-10-25 | 2015-04-29 | 英飞凌科技股份有限公司 | Semiconductor device and method for manufacturing the semiconductor device |
| CN105336632A (en) * | 2014-08-05 | 2016-02-17 | 英飞凌科技股份有限公司 | Batch process for connecting chips to carrier |
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