CN105789052A - Fabrication method of low-temperature poly-silicon thin film transistor and product - Google Patents
Fabrication method of low-temperature poly-silicon thin film transistor and product Download PDFInfo
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 57
- 238000000034 method Methods 0.000 title claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 title abstract description 4
- 239000010409 thin film Substances 0.000 title abstract description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 29
- 238000009413 insulation Methods 0.000 claims abstract description 29
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 25
- 239000004065 semiconductor Substances 0.000 claims abstract description 20
- 230000008021 deposition Effects 0.000 claims abstract description 10
- 238000005530 etching Methods 0.000 claims abstract description 10
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 10
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 9
- 238000005224 laser annealing Methods 0.000 claims abstract description 9
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 9
- 239000001301 oxygen Substances 0.000 claims abstract description 9
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 9
- 238000006243 chemical reaction Methods 0.000 claims abstract description 8
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 7
- 238000002347 injection Methods 0.000 claims abstract description 5
- 239000007924 injection Substances 0.000 claims abstract description 5
- 230000008569 process Effects 0.000 claims abstract description 3
- 239000010410 layer Substances 0.000 claims description 88
- 229920005591 polysilicon Polymers 0.000 claims description 50
- 230000009466 transformation Effects 0.000 claims description 39
- -1 oxonium ion Chemical class 0.000 claims description 22
- 238000002360 preparation method Methods 0.000 claims description 14
- 239000011241 protective layer Substances 0.000 claims description 13
- 238000007789 sealing Methods 0.000 claims description 9
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 6
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 6
- 101100373011 Drosophila melanogaster wapl gene Proteins 0.000 claims description 5
- 210000004483 pasc Anatomy 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 5
- 230000004913 activation Effects 0.000 claims description 4
- 238000010884 ion-beam technique Methods 0.000 claims description 3
- 238000004380 ashing Methods 0.000 claims description 2
- 238000004140 cleaning Methods 0.000 claims description 2
- 241000790917 Dioxys <bee> Species 0.000 claims 1
- 229910003978 SiClx Inorganic materials 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 1
- 239000013078 crystal Substances 0.000 claims 1
- 238000001259 photo etching Methods 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- 238000005516 engineering process Methods 0.000 abstract description 4
- 238000003079 width control Methods 0.000 abstract description 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000012528 membrane Substances 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 239000010408 film Substances 0.000 description 15
- 229910021419 crystalline silicon Inorganic materials 0.000 description 6
- 229910052796 boron Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005401 electroluminescence Methods 0.000 description 1
- 239000007792 gaseous phase Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000002000 scavenging effect Effects 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/223—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Recrystallisation Techniques (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention provides a fabrication method of a low-temperature poly-silicon thin film transistor. The fabrication method comprises the following steps of forming an oxygen heavily doped region on a non-protection region (an insulation conversion region) by an oxygen injection technology after an amorphous silicon layer a-Si is deposited through a photoresist protection pattern region; carrying out an excimer laser annealing (ELA) process to enable non-doped amorphous silicon and oxygen-doped amorphous silicon to respectively form poly-silicon and SiO2; and carrying out GI membrane deposition of a gate dielectric layer, and improving GI step coverage and line width control of P-Si. Since the amorphous silicon layer outside a semiconductor conversion region is removed not by an etching mode, no step is formed at the edge of the poly-silicon semiconductor layer P-Si, the step coverage rate of the high gate dielectric layer GI is effectively improved, and electric leakage is prevented.
Description
Technical field
The invention belongs to organic electroluminescence device technical field, be specifically related to a kind of low temperature polycrystalline silicon thin
The manufacture method of film transistor and utilize low-temperature polysilicon film transistor prepared by the method.
Background technology
It is by glass base by low temperature polycrystalline silicon (LTPS) thin film transistor (TFT) (TFT) structure as shown in Figure 1
On plate 1, the non-crystalline silicon (a-Si) of deposition is converted into polysilicon (P-Si) being formed by etching and partly leads
Body layer 2, the most thereon cvd silicon oxide (SiO2) as gate dielectric layer 3 (GI), metal gate layers
4(Gate).Due to P-Si marginal existence step after over etching, for ensureing that silicon oxide can cover
Step and prevent short circuit electric leakage, frequently with way be to reduce the slope angle of P-Si and increase the thickness of GI.
But the mode that P-Si uses quasi-molecule laser annealing (ELA) is formed, often there is projection in its surface,
When projection is near marginal position, if GI layer step coverage is deteriorated or Gate etching occurred quarter
Shi Ze is susceptible to electric leakage or punctures；On the other hand, reduce the slope angle of P-Si, be unfavorable for the line of figure
Wide control, is susceptible to residual.
Summary of the invention
The technical problem to be solved is that in prior art, semiconductor layer surface exists step and causes
Gate dielectric layer spreadability is deteriorated and electrical leakage problems occurs, thus provides the system of low-temperature polysilicon film transistor
Preparation Method and the low-temperature polysilicon film transistor prepared by this method.The present invention partly leads
Body layer edge is formed without step, is effectively improved the step coverage of gate dielectric layer and prevents electric leakage.
For solving above-mentioned technical problem, the present invention is achieved by the following technical solutions:
The preparation method of a kind of low-temperature polysilicon film transistor, comprises the steps:
S1: deposition of amorphous silicon layers on substrate, and amorphous silicon layer is divided into insulation switch region and partly leads
Body zone of transformation；
S2: armor coated on described amorphous silicon layer, and etch above the described insulation zone of transformation of removal
Protective layer, make described in state insulation zone of transformation and expose, and retain the protective layer above quasiconductor zone of transformation；
S3: inject oxonium ion in insulation zone of transformation；
S4: removed by the protective layer above quasiconductor zone of transformation, uses quasi-molecule laser annealing technique to make
The amorphous silicon layer of quasiconductor zone of transformation is converted to polysilicon semiconductor layer, activates insulation zone of transformation note simultaneously
The oxonium ion entered, the oxonium ion of described state of activation forms silicon dioxide with the pasc reaction in amorphous silicon layer
Sealing coat；
S5, on the basis of step S4, deposit gate dielectric layer, grid layer, intermediate insulating layer and source-drain electrode.
The dosage injecting oxonium ion in described step S3 is more than marginal value, injects oxygen in insulation zone of transformation
During ion, the injection direction of oxygen ion beam is perpendicular to the plane at described insulation zone of transformation place.
Described protective layer is photoresist layer.
In described step S2, etching is the photoresist using Exposure mode to remove above described insulation zone of transformation
Layer.
Described step S4 is:
Photoresist layer above quasiconductor zone of transformation is carried out ashing process, after then carrying out peeling off cleaning,
Quasi-molecule laser annealing technique is used to make the amorphous silicon layer of quasiconductor zone of transformation be converted to polysilicon semiconductor
Layer, activates the oxonium ion that insulation zone of transformation injects, the oxonium ion of described state of activation and non-crystalline silicon simultaneously
Pasc reaction in Ceng forms silicon dioxide sealing coat；
In described step S5 before deposition gate dielectric layer to polysilicon semiconductor layer and silicon dioxide every
The surface of absciss layer uses hydrofluoric acid clean, to reduce the height of its protrusion of surface.
The present invention also provides for a kind of low-temperature polysilicon film transistor prepared by said method.
The technique scheme of the present invention has the advantage that compared to existing technology
The preparation method of the low-temperature polysilicon film transistor that the present invention provides, is at deposition of amorphous silicon layers
Protect graphics field by photoresistance after a-Si, note oxygen is used for non-protected area (insulation zone of transformation)
Technology forms oxygen heavily doped region, then carries out quasi-molecule laser annealing (ELA) technique, makes unadulterated
The non-crystalline silicon of non-crystalline silicon and oxygen doping forms P-Si and SiO2 respectively, carries out GI the most again and sinks film, improves
The live width of GI Step Coverage and P-Si controls.Owing to not being employing etching mode removal quasiconductor conversion
Amorphous silicon layer beyond district, therefore the edge of polysilicon semiconductor layer P-Si is formed without step, effectively carries
The step coverage of high gate dielectric layer GI prevents electric leakage.
Additionally, due to do not use etching mode to remove the amorphous silicon layer beyond quasiconductor zone of transformation, polycrystalline
Silicon semiconductor layer P-Si can form the biggest slope angle, improves the live width control of polysilicon semiconductor layer P-Si
System, reduces the probability of etching residue.Further, the amorphous silicon layer beyond quasiconductor zone of transformation leads to
Crossing and react formation silicon dioxide sealing coat with oxonium ion, silicon dioxide sealing coat is at polysilicon semiconductor layer
The surrounding of P-Si forms silicon oxide heat-insulation layer, is conducive to improving the mobility of P-Si when ELA.
Accompanying drawing explanation
In order to make present disclosure be more likely to be clearly understood, below in conjunction with the accompanying drawings, to the present invention
It is described in further detail, wherein,
Fig. 1 is the structural representation of the TFT of prior art；
Fig. 2-Fig. 3 is the TFT preparation process schematic diagram of the present invention；
Wherein reference is: 1-substrate, 2-semiconductor layer, 3-gate dielectric layer, 4-grid layer, 5-
Protective layer, 21-amorphous silicon layer, 22-silicon dioxide sealing coat, 23-TFT channel region, 24-heavily doped region,
6-intermediate insulating layer, 7-source-drain electrode layer.
Detailed description of the invention
In order to make the purpose of invention, technical scheme and advantage clearer, below in conjunction with accompanying drawing to sending out
Bright embodiment is described in further detail.
Invention can be embodied in many different forms, and should not be construed as limited to set forth herein
Embodiment.On the contrary, it is provided that these embodiments so that the disclosure will be thorough and complete, and will
The design of invention is fully conveyed to those skilled in the art, and invention will only be defined by the appended claims.
In the accompanying drawings, for clarity, layer and the size in region and relative size can be exaggerated.It is to be understood that
, when element such as layer, region or substrate are referred to as " being formed at " or " being arranged on " another yuan
Part " on " time, this element can be arranged directly on another element described, or can also exist
Between element.On the contrary, it is referred to as " being formed directly into " or " being set directly at " another element when element
Time upper, there is not intermediary element.
As shown in Figures 2 and 3, the invention provides a kind of low-temperature polysilicon film transistor, described
Low-temperature polysilicon film transistor preparation method, comprise the steps:
S1: use the method deposition of amorphous silicon layers 21 of chemical gaseous phase deposition on substrate, and by non-crystalline silicon
Layer 21 is divided into insulation switch region and quasiconductor zone of transformation；
S2: on described amorphous silicon layer 21 armor coated 5, described protective layer 5 is photoresist layer,
And pass through exposure imaging and etch the protective layer 5 removed above described insulation zone of transformation, make described insulation turn
Change district to expose, and retain the protective layer above quasiconductor zone of transformation；
S3: to insulation zone of transformation in inject oxonium ion, can use source and drain areas is doped from
Sub-injection device, the dosage injecting oxonium ion needs more than marginal value, and typical dosage is 1*1017/cm2；
When injecting oxonium ion in insulation zone of transformation, the injection direction of oxygen ion beam is perpendicular to described insulation and converts
The plane at place, district.
S4: after being removed by the protective layer above quasiconductor zone of transformation, uses quasi-molecule laser annealing technique
The amorphous silicon layer making quasiconductor zone of transformation is converted to polysilicon semiconductor layer 2, due to excimer laser irradiation
Non-crystalline silicon can produce high temperature, and typical temperature is more than 1400 DEG C, therefore at quasi-molecule laser annealing
The oxonium ion simultaneously making insulation zone of transformation activates and forms silicon dioxide isolation with the pasc reaction in amorphous silicon layer
Layer 22；
S5: deposit gate dielectric layer 3, grid layer 4, intermediate insulating layer 6 and on the basis of step S4
Source-drain electrode.
To polysilicon semiconductor layer 2 and silicon dioxide before deposition gate dielectric layer in described step S5
The surface of sealing coat 22 uses hydrofluoric acid clean, and typical concentration is 1wt%, scavenging period 30 seconds,
To reduce the height of its protrusion of surface.
Low-temperature polysilicon film transistor preparation method of the present invention also includes step S6 and step
S7:
S6: use ion implantation apparatus that polysilicon semiconductor layer 2 is carried out boron ion note after step s 5
Entering, typical implantation dosage is more than 1*1015/cm2To form heavy doping, owing to gate metal is to boron ion
Barrier effect, the polysilicon region covered by grid layer 4 forms TFT channel without boron ion implanting
District, the polysilicon region not covered by grid layer 4 forms heavily doped region, this district due to boron ion implanting
Territory is as source-drain electrode contact area.
S7: deposit intermediate insulating layer 6 on the grid layer 4 that step S5 is formed, and etched by exposure
Method formed source-drain electrode contact hole, last sedimentary origin drain metal layer, be etched to define source-drain electrode layer 7.
The structure of the low-temperature polysilicon film transistor that the present invention provides and existing low-temperature polysilicon film
The structure of transistor in addition to semiconductor layer difference, remaining each layer, as gate dielectric layer 3, grid layer 4,
Intermediate insulating layer 6 and source-drain electrode, and structure is the most identical, does not repeats them here.
The low-temperature polysilicon film transistor that the present invention provides, is not to use etching side due to semiconductor layer
Formula removes the amorphous silicon layer beyond quasiconductor zone of transformation, therefore the edge of polysilicon semiconductor layer P-Si without
Step is formed, and the step coverage being effectively improved gate dielectric layer GI prevents electric leakage.
Obviously, above-described embodiment is only for clearly demonstrating example, and not to embodiment party
The restriction of formula.For those of ordinary skill in the field, the most also may be used
To make other changes in different forms.Here without also all of embodiment being given
With exhaustive.And the obvious change thus extended out or variation are still in the guarantor of the invention
Protect among scope.
Claims (8)
1. the preparation method of a low-temperature polysilicon film transistor, it is characterised in that include walking as follows
Rapid:
S1: deposition of amorphous silicon layers (21) on substrate, and amorphous silicon layer (21) is divided into insulation
Switch region and quasiconductor zone of transformation；
S2: upper armor coated (5) at described amorphous silicon layer (21), and etch the described insulation of removal
Protective layer (5) above zone of transformation, makes described insulation zone of transformation expose, and retains quasiconductor zone of transformation
The protective layer of top；
S3: inject oxonium ion in insulation zone of transformation；
S4: removed by the protective layer above quasiconductor zone of transformation, uses quasi-molecule laser annealing technique to make
The amorphous silicon layer of quasiconductor zone of transformation is converted to polysilicon semiconductor layer (2), activates insulation simultaneously and converts
The oxonium ion that district is injected, the oxonium ion of described state of activation forms dioxy with the pasc reaction in amorphous silicon layer
SiClx sealing coat (22)；
S5, on the basis of step S4 deposit gate dielectric layer (3), grid layer (4), intermediate insulation
Layer (6) and source-drain electrode.
The preparation method of low-temperature polysilicon film transistor the most according to claim 1, its feature
It is, described step S3 is injected the dosage of oxonium ion more than marginal value.
The preparation method of low-temperature polysilicon film transistor the most according to claim 2, its feature
It is: described step S3 is: when injecting oxonium ion in insulation zone of transformation, the injection side of oxygen ion beam
To the plane being perpendicular to described insulation zone of transformation place.
4. according to the preparation method of the low-temperature polysilicon film transistor described in any one of claim 1-3,
It is characterized in that: described protective layer (5) is photoresist layer.
The preparation method of low-temperature polysilicon film transistor the most according to claim 4, its feature
It is: in described step S2, etching is the photoetching using Exposure mode to remove above described insulation zone of transformation
Glue-line.
The preparation method of low-temperature polysilicon film transistor the most according to claim 4, its feature
It is: described step S4 is:
Photoresist layer above quasiconductor zone of transformation is carried out ashing process, after then carrying out peeling off cleaning,
Quasi-molecule laser annealing technique is used to make the amorphous silicon layer of quasiconductor zone of transformation be converted to polysilicon semiconductor
Layer (2), activates the oxonium ion that insulation zone of transformation injects simultaneously, and the oxonium ion of described state of activation is with non-
Pasc reaction in crystal silicon layer forms silicon dioxide sealing coat (22).
The preparation method of low-temperature polysilicon film transistor the most according to claim 6, its feature
It is: to polysilicon semiconductor layer (2) and two before deposition gate dielectric layer in described step S5
The surface of silicon oxide sealing coat (22) uses hydrofluoric acid clean, to reduce the height of its protrusion of surface.
8. the low-temperature polysilicon film that the method described in an any one of claim 1-6 prepares is brilliant
Body pipe.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510999757.0A CN105789052A (en) | 2015-12-28 | 2015-12-28 | Fabrication method of low-temperature poly-silicon thin film transistor and product |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510999757.0A CN105789052A (en) | 2015-12-28 | 2015-12-28 | Fabrication method of low-temperature poly-silicon thin film transistor and product |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107068768A (en) * | 2017-04-05 | 2017-08-18 | 深圳市华星光电技术有限公司 | Thin film transistor (TFT) and preparation method thereof, array base palte |
| CN107833924A (en) * | 2017-10-26 | 2018-03-23 | 京东方科技集团股份有限公司 | Top gate type thin film transistor and preparation method thereof, array base palte, display panel |
| US10439071B2 (en) | 2017-04-05 | 2019-10-08 | Shenzhen China Star Optoelectronics Technology Co., Ltd | Thin film transistors and the manufacturing methods thereof, and array substrates |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06338614A (en) * | 1993-05-28 | 1994-12-06 | Casio Comput Co Ltd | Thin-film transistor and manufacture thereof |
| CN101067701A (en) * | 2006-05-03 | 2007-11-07 | Lg.菲利浦Lcd株式会社 | LCD device and its production method |
-
2015
- 2015-12-28 CN CN201510999757.0A patent/CN105789052A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06338614A (en) * | 1993-05-28 | 1994-12-06 | Casio Comput Co Ltd | Thin-film transistor and manufacture thereof |
| CN101067701A (en) * | 2006-05-03 | 2007-11-07 | Lg.菲利浦Lcd株式会社 | LCD device and its production method |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107068768A (en) * | 2017-04-05 | 2017-08-18 | 深圳市华星光电技术有限公司 | Thin film transistor (TFT) and preparation method thereof, array base palte |
| WO2018184294A1 (en) * | 2017-04-05 | 2018-10-11 | 深圳市华星光电技术有限公司 | Thin film transistor and manufacturing method thereof, and array substrate |
| US10439071B2 (en) | 2017-04-05 | 2019-10-08 | Shenzhen China Star Optoelectronics Technology Co., Ltd | Thin film transistors and the manufacturing methods thereof, and array substrates |
| CN107833924A (en) * | 2017-10-26 | 2018-03-23 | 京东方科技集团股份有限公司 | Top gate type thin film transistor and preparation method thereof, array base palte, display panel |
| CN107833924B (en) * | 2017-10-26 | 2020-06-19 | 京东方科技集团股份有限公司 | Top gate type thin film transistor, preparation method thereof, array substrate and display panel |
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