CN105428412A - Algan/gan heterojunction field effect transistor and preparation method thereof - Google Patents
Algan/gan heterojunction field effect transistor and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 11
- 238000002353 field-effect transistor method Methods 0.000 title 1
- 230000004888 barrier function Effects 0.000 claims abstract description 42
- 229910002704 AlGaN Inorganic materials 0.000 claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 238000000034 method Methods 0.000 claims description 29
- 229910001020 Au alloy Inorganic materials 0.000 claims description 21
- 238000005516 engineering process Methods 0.000 claims description 20
- 239000000463 material Substances 0.000 claims description 18
- 229910000990 Ni alloy Inorganic materials 0.000 claims description 7
- 238000005566 electron beam evaporation Methods 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 claims description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims description 5
- 229910001182 Mo alloy Inorganic materials 0.000 claims description 4
- 229910001069 Ti alloy Inorganic materials 0.000 claims description 4
- 229910001252 Pd alloy Inorganic materials 0.000 claims description 3
- 229910001260 Pt alloy Inorganic materials 0.000 claims description 3
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 238000004064 recycling Methods 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 2
- 238000001451 molecular beam epitaxy Methods 0.000 claims description 2
- 230000005669 field effect Effects 0.000 abstract description 13
- 230000006866 deterioration Effects 0.000 abstract description 2
- 238000012545 processing Methods 0.000 abstract description 2
- 230000005540 biological transmission Effects 0.000 abstract 1
- 229910002601 GaN Inorganic materials 0.000 description 114
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 111
- 230000005684 electric field Effects 0.000 description 11
- 239000013078 crystal Substances 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 238000009826 distribution Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000009825 accumulation Methods 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 229910010271 silicon carbide Inorganic materials 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 238000000407 epitaxy Methods 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- 230000005533 two-dimensional electron gas Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7788—Vertical transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/41725—Source or drain electrodes for field effect devices
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66431—Unipolar field-effect transistors with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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Abstract
The invention relates to an AlGaN/GaN heterojunction field effect transistor and a preparation method thereof. The field effect transistor comprises a grid, a source, a drain, a substrate, an epitaxial structure and an insulated dielectric layer, wherein the drain, the substrate and the epitaxial structure are orderly arranged in a stacking form; the epitaxial structure comprises a n type GaN layer, a vertical super junction layer, a channel layer and a barrier layer, which are orderly stacked; the vertical super junction layer comprises alternatively arranged light-doped p type GaN layer and heavy-doped n type GaN layer, the heavy-doped n type GaN layer is thinner than the light-doped p type GaN layer, and the channel layer and the barrier layer are stacked on the light-doped p type GaN layer. The field effect transistor is simple in structure; performance deterioration of devices caused by complex device processing is avoided; stability is guaranteed; and relatively high forward current transmission ability and backward high voltage endurance of devices are realized simultaneously.
Description
Technical field
The present invention relates to semiconductor device, particularly relate to AlGaN/GaN HFET and preparation method thereof.
Background technology
In modern society, power electronic technology is constantly with new development, the power electronic device such as pressurizer, rectifier, inverter are applied more and more extensive in daily life, relate to the numerous areas such as high voltage supply, electric energy management, factory automation, motor vehicle energy sources distribution management.Diode and switching device are parts indispensable in applied power electronics field.In recent years, have high frequency, big current, low power consumption characteristic Schottky diode more and more noticeable with the performance advantage of its uniqueness.
Traditional power-type Schottky diode mainly makes on silicon (Si) sill.Silicon materials developing history is long, and silicon single crystal preparation cost is low, silicon device processing technology ripe, and therefore the development of silica-based Schottky diode is also the most ripe.But due to the restriction of the material behavior such as energy gap, electron mobility, the performance of silicon-based power Schottky diode, close to its theoretical limit, can not meet the demand of current high frequency, high power, high-temperature resistant.Silica-based Schottky diode is resistance to be forced down, current carrying capability is limited, harsh to system radiating requirement under the high temperature conditions, which results in that device volume weight is large, energy consumption large, be unfavorable for that power electronic system develops to integrated, miniaturized, energy-saving.
In order to break through self restriction of silicon materials, people start to find the material with more dominance energy, enter the people visual field with the third generation semiconductor material with wide forbidden band that gallium nitride (GaN), carborundum (SiC) are representative.They have excellent physics and chemistry character, as large in energy gap, breakdown field strength is high, saturated electron drift velocity is large, capability of resistance to radiation is strong, chemical stability is good, is particularly suitable for making high withstand voltage, high-temperature resistant, high frequency, high-power schottky diode device.Another outstanding feature of GaN material is exactly the polarity effect utilizing self, as shown in Figure 1, just can form electron areal density reach 1013cm at the AlGaN/GaN of undoped
-2the high concentration two-dimensional electron gas (2DEG:Two-dimensionalelectrongas) of magnitude.2DEG surface density is large, in raceway groove two dimensional surface, mobility is high, and the GaN Schottky diode of the horizontal conducting utilizing this characteristic to make is modal at present, is also most potential epitaxial structure form.
In traditional AlGaN/GaN field-effect transistor, because break-over of device layer is on the surface of semiconductor extension structure, when device belongs to shutoff operating state, the Electric Field Distribution of device too concentrates on epi-layer surface, limits device withstand voltage characteristic.Therefore, the voltage endurance how promoting this device architecture becomes one of technological difficulties needing solution badly at present.
Superjunction technology (SuperJunction) is the power insulated gate field-effect transistor (MOSFET) deriving from Si base, while carrier concentration in epitaxial loayer is improved 1 magnitude by charge compensation principle by the N-shaped post in epitaxial loayer and p-type post, under reverse spent condition, realize the distribution of electric field in epitaxial loayer close to equal perfect condition everywhere, make the optimization of epitaxial loayer voltage endurance capability.
In GaN material, also have similar thought, as shown in Figure 2, prior art proposes a kind of AlGaN/GaN HFET based on super-junction structure.The key technology of this invention is the means by ion implantation, and n-type GaN layer forms p-type GaN, thus realizes super-junction structure (as shown in Figure 2 44).The electric field that the E-field normal set up by super-junction structure is set up between grid and drain electrode, changes the spatial distribution of electric field, reduces the electric field maximum in epitaxial loayer, therefore correspondingly improve puncture voltage.But the making data report of also not this device, is enough to illustrate that the technology difficulty that will realize this device is big in current existing scientific and technical literature.In addition, p-GaN is realized by the crystal mass of serious deterioration epitaxial loayer and epi-layer surface evenness by ion implantation means, the AlGaN/GaN heterojunction boundary characteristic that regrowth is formed on this basis also can be simultaneously deteriorated, reduce the ducting capacity of 2DEG, thus have influence on current carrying capacities and the stability of device.
Vertical conducting AlGaN/GaN heterojunction field effect transistor structure based on super-junction structure also has the report of similar device, as shown in Figure 3.But the prior art just propose a kind of Theoretical Design structure in principle, do not illustrate that concrete device realizes manufacture method.This device architecture epitaxy technique difficulty is equally very large, and be difficult to instruct practical devices development & production, meanwhile, the grid schottky metal in this structure easily punctures in high back voltage situation, have impact on the lifting of device withstand voltage performance
From researching and analysing of above-mentioned prior art, from horizontal conducting structure to vertical conducting structure, the application of superjunction all embodies, but does not form the technical scheme of easier industrialization production.Main shortcoming has: 1, technique is larger to crystal mass damage, by the super-junction structure that ion implantation technology realizes, due to very near gallium nitride heterojunction active area, larger on the current carrying capacities impact of device, while lifting is withstand voltage, sacrifice the output characteristic of larger device; 2, device architecture is complicated, and practical devices process implementing difficulty is comparatively large, is unfavorable for Industry Promotion.
Summary of the invention
Based on this, be necessary to provide a kind of AlGaN/GaN HFET and preparation method thereof.
A kind of AlGaN/GaN HFET, comprise grid, source electrode, drain electrode, substrate, epitaxial structure and insulating medium layer, described drain electrode, substrate, epitaxial structure are cascading;
Described epitaxial structure comprises the n-type GaN layer, vertical super-junction layer, channel layer and the barrier layer that are cascading, wherein, described vertical super-junction layer comprises the lightly doped p-type GaN layer and highly doped n-type GaN layer that are alternately arranged, the thickness of described highly doped n-type GaN layer is little compared with described lightly doped p-type GaN layer, and described channel layer and barrier layer are laminated on described lightly doped p-type GaN layer;
Described source electrode is arranged at the side of described epitaxial structure, and one end extends to the upper surface of described barrier layer, and the other end extends to described lightly doped p-type GaN layer;
Described insulating medium layer is arranged on described highly doped n-type GaN layer, and end extends to described barrier layer, stops the loss of electronics during conducting thus, and this insulating medium layer can be prepared by the passivation layer required with device itself simultaneously;
Described grid is arranged on described insulating medium layer, and end extends to the upper surface of described barrier layer.
Wherein, substrate of the present invention can be the low-resistance silicon, carborundum or gallium nitride etc. of n doping, but is not limited to above-mentioned material, as long as can complete GaN epitaxy Material growth, form the backing material of low-resistance conducting and can be used in structure of the present invention.
Wherein in an embodiment, the thickness range of described lightly doped p-type GaN layer at 1 μm ~ 10 μm, little 100nm ~ 1 μm of thickness of the thickness more described lightly doped p-type GaN layer of described highly doped n-type GaN layer.
The function of described lightly doped p-type GaN layer is electronic barrier layer, when device is in reverse withstand voltage operating state and highly doped n-type GaN layer form the super-junction structure of mutual depletion layer, described highly doped n-type GaN layer when break-over of device as the communication channel of electronics, when device turns off and lightly doped p-type GaN layer form the super-junction structure of mutual depletion layer, its growth thickness regulates and controls according to the thickness of lightly doped p-type GaN layer.
Wherein in an embodiment, the doping content of described lightly doped p-type GaN layer is 10
16~ 10
17cm
-3, the doping content of described highly doped n-type GaN layer is 10
17~ 10
19cm
-3.
Wherein in an embodiment, described n-type GaN layer is lightly doped n-type GaN layer, and doping content is 10
16~ 10
17cm
-3, thickness range is at 1 μm ~ 20 μm.The growth of lightly doped n-type GaN layer improves upper strata GaN epitaxial layer crystal mass on the one hand, can form electron drift district during vertical conducting on the other hand.
Wherein in an embodiment, the material of described insulating medium layer is SiO
2, SiN, Al
2o
3, AlN, HfO
2, MgO, Sc
2o
3, Ga
2o
3, AlHfO
x, any one or any several combination in HfSiON, thickness is 1nm ~ 100nm.
Wherein in an embodiment, described channel layer is the GaN layer of undoped, and thickness is 1nm ~ 500nm, and the GaN channel layer forming high-quality smooth is thus beneficial to 2DEG conducting; Described barrier layer is AlGaN, AlN, AlInN layer of undoped or its combination, and thickness is 1nm ~ 50nm, can regulate and control various combination thickness and component to form the 2DEG of high concentration, high mobility at barrier layer/channel layer interface.
Wherein in an embodiment, the material of described drain electrode and source electrode is optional from Ti/Al/Ni/Au alloy, Ti/Al/Mo/Au alloy or Ti/Al/Ti/Au alloy respectively; The material of described grid is Ni/Au alloy, Pt/Au alloy or Pd/Au alloy.
Wherein in an embodiment, described vertical super-junction layer comprises two lightly doped p-type GaN layer, and the highly doped n-type GaN layer between two lightly doped p-type GaN layer, described source electrode is symmetricly set in the relative two sides of described epitaxial structure, and one end extends to the upper surface of described barrier layer, the other end extends to described lightly doped p-type GaN layer.
The present invention also provides the preparation method of described AlGaN/GaN HFET, comprises the steps:
(1) described n-type GaN layer, lightly doped p-type GaN layer, channel layer and barrier layer is grown successively by growth technology over the substrate;
(2) by wet method or dry etching techniques, described lightly doped p-type GaN layer, channel layer and barrier layer are etched, form the groove being communicated to described n-type GaN layer by the upper surface of described barrier layer, and, for holding the housing region of described source electrode, the etching depth of wherein said recessed grain requires to reach described n-type GaN layer, and the housing region of described source electrode requires to reach described lightly doped p-type GaN layer;
(3) upper surface in described housing region and described barrier layer makes mask, then grows described highly doped n-type GaN layer by selected zone growth technology in described groove;
(4) described mask is removed, utilize photoetching technique and electron beam evaporation technique, form described source electrode at described housing region, form described drain electrode at the lower surface of described substrate, this source electrode can be arranged in step, to form better contact with described lightly doped p-type GaN layer;
(5) dielectric layer growing technology is utilized, at the upper surface deposition insulating medium layer of described highly doped n-type GaN layer, and make the end of described insulating medium layer extend to described barrier layer, recycling photoetching technique and electron beam evaporation technique form described grid on described insulating medium layer.
Described dielectric layer growing technology can be physical vapor method (PVD), plasma reinforced chemical vapour deposition method (PECVD), magnetron sputtering method or atomic layer deposition method (ALD).
Wherein in an embodiment, step (1) described growth technology and the described selected zone growth technology of step (3) are Metalorganic Chemical Vapor Deposition (MOCVD) or molecular beam epitaxy (MBE).
Principle of the present invention and advantage as follows:
Described AlGaN/GaN HFET of the present invention, rationally device architecture is set, under device is in ON state operating state, grid applies forward voltage, now the GaN channel layer of dielectric and undoped and the contact interface of lightly doped p-type GaN layer form N-shaped electron accumulation layer and inversion layer, the electronics of source electrode is injected into highly doped n-type GaN layer by the 2DEG raceway groove in channel layer, N-shaped electron accumulation layer and inversion layer, and finally reach drain electrode by lightly doped n-type GaN layer, realize break-over of device, the current carrying capacities of device is strong and stable.
And when device is under OFF state operating state, grid Schottky applies reverse voltage, grid underlying conductive raceway groove blocks, now, the super-junction structure that the lightly doped p-type GaN layer in epitaxial loayer, highly doped n-type GaN layer are formed forms depleted region, from superjunction theory, the electric field of E-field normal between drain and gate that superjunction is set up, make the electric field in epitaxial loayer more even, reduce peak electric field, realize the high voltage endurance of transistor.
Compared with prior art, the present invention has following beneficial effect:
The present invention proposes a kind of high withstand voltage AlGaN/GaN heterojunction field field-effect transistor of the vertical conducting based on super-junction structure of structure innovation, avoid the device performance degradation that complicated device technology causes, stability is secure.
Heavily doped n-type GaN layer electronic conduction passage is grown by the selected zone secondary epitaxy of novelty, directly super-junction structure is formed with once epitaxially grown lightly doped p-type GaN layer, eliminate later stage ion implantation technology, will be reduced to minimum on the impact of 2DEG in heterojunction; Simultaneously, by rationally arranging the position of each electrode, be different from the plane electrode of traditional devices, source electrode Ohmic electrode contacts the barrier layer that is connected in epitaxial structure to lightly doped p-type GaN layer, be connected with the super-junction structure in source region and epitaxial loayer, superjunction when simultaneously meeting forward conduction and reverse operation exhausts demand.Thus achieve the current carrying capacities that device forward is stronger, and reverse high voltage endurance.
Accompanying drawing explanation
Fig. 1 be AlGaN/GaN epitaxial structure (left figure) and can be with, distribution of electron's density figure (right figure);
Fig. 2 is the existing AlGaN/GaN heterojunction field effect transistor structure schematic diagram based on super-junction structure;
Fig. 3 is the vertical conducting AlGaN/GaN heterojunction field effect transistor structure schematic diagram based on super-junction structure;
Fig. 4 is AlGaN/GaN heterojunction field effect transistor structure schematic diagram described in one embodiment of the invention;
Through step (1) resulting structures schematic diagram in the manufacture method that Fig. 5 is AlGaN/GaN hetero junction field effect crystal described in one embodiment of the invention;
Through step (2) resulting structures schematic diagram in the manufacture method that Fig. 6 is AlGaN/GaN hetero junction field effect crystal described in one embodiment of the invention;
Through step (3) resulting structures schematic diagram in the manufacture method that Fig. 7 is AlGaN/GaN hetero junction field effect crystal described in one embodiment of the invention, wherein,
1-substrate; 2-n type GaN layer; 3-lightly doped p-type GaN layer; 4-channel layer; 5-barrier layer; 6-2DEG raceway groove; 7-highly doped n-type GaN layer; 8-source electrode; 9-insulating medium layer; 10-grid; 11-drains; 12-groove; 13-housing region.
Embodiment
Below in conjunction with specific embodiment, AlGaN/GaN HFET of the present invention and preparation method thereof is described in further detail.
Embodiment
A kind of AlGaN/GaN HFET of the present embodiment, as shown in Figure 4, comprise grid 10, source electrode 8, drain electrode 11, substrate 1, epitaxial structure and insulating medium layer 9, described drain electrode 11, substrate 1, epitaxial structure are cascading;
Described epitaxial structure comprises the n-type GaN layer 2, vertical super-junction layer, channel layer 4 and the barrier layer 5 that are cascading, wherein, described vertical super-junction layer comprises two lightly doped p-type GaN layer 3, and the highly doped n-type GaN layer 7 between two lightly doped p-type GaN layer 3, the thickness of described lightly doped p-type GaN layer 3 is 1 μm ~ 10 μm, and doping content is 10
16~ 10
17cm
-3, little 100nm ~ 1 μm of thickness more described lightly doped p-type GaN layer 3 of described highly doped n-type GaN layer 7, doping content is 10
17~ 10
19cm
-3, described channel layer 4 and barrier layer 5 are laminated on described lightly doped p-type GaN layer;
Low-resistance silicon, carborundum or gallium nitride that this substrate 1 adulterates for n; The material of drain electrode 11 is optionally from Ti/Al/Ni/Au alloy, Ti/Al/Mo/Au alloy or Ti/Al/Ti/Au alloy;
This n-type GaN layer 2 is lightly doped n-type GaN layer, and it is 10 that doping content controls
16~ 10
17cm
-3, thickness range controls at 1 μm ~ 20 μm, can improve upper strata GaN epitaxial layer crystal mass on the one hand, can form electron drift district during vertical conducting on the other hand, improves electric current forward transmittability;
This channel layer 4 is the GaN layer of undoped, and thickness is between 1nm ~ 500nm, and the GaN channel layer forming high-quality smooth is thus beneficial to 2DEG raceway groove 6 conducting; Barrier layer 5 is AlGaN, AlN, AlInN layer of undoped or its combination, and thickness is 1nm ~ 50nm, can regulate and control various combination thickness and component to form the 2DEG of high concentration, high mobility at barrier layer 5/ channel layer 4 interface;
Described source electrode 8 is symmetricly set in the relative two sides of described epitaxial structure, and in step-like, one end extends to the upper surface of described barrier layer 5, and the other end extends to described lightly doped p-type GaN layer 3, and material is selected from Ti/Al/Ni/Au alloy, Ti/Al/Mo/Au alloy or Ti/Al/Ti/Au alloy;
Described insulating medium layer 9 is arranged on described highly doped n-type GaN layer 7, and end at least extends to described barrier layer 5, and the material of described insulating medium layer 9 is SiO
2, SiN, Al
2o
3, AlN, HfO
2, MgO, Sc
2o
3, Ga
2o
3, AlHfO
x, any one or any several combination in HfSiON, thickness is 1nm ~ 100nm.When stopping conducting thus, in channel layer 4 and lightly doped p-type GaN layer 3 and highly doped n-type GaN layer 7, electronics is run off by grid 10, the passivation layer that this insulating medium layer 9 is required with device itself is in the present embodiment prepared simultaneously, extends to the surface covering and described barrier layer 5 needs passivation;
Described grid 10 is arranged on described insulating medium layer 9, and end extends to the upper surface of described barrier layer 5, and material is Ni/Au alloy, Pt/Au alloy or Pd/Au alloy.
Under device is in ON state operating state, grid 10 Schottky applies forward voltage, now insulating medium layer 9 and the GaN channel layer 4 of undoped and the contact interface of lightly doped p-type GaN layer 3 form N-shaped electron accumulation layer and inversion layer, the electronics of source electrode 8 is injected into highly doped n-type GaN layer 7 by the 2DEG raceway groove 6 in channel layer 4, N-shaped electron accumulation layer and inversion layer, and finally reach drain electrode 11 by lightly doped n-type GaN layer, realize break-over of device, the current carrying capacities of device is strong and stable.
And when device is under OFF state operating state, grid 10 Schottky applies reverse voltage, grid 10 underlying conductive raceway groove blocks, now, the super-junction structure that the lightly doped p-type GaN layer 3 in epitaxial loayer, highly doped n-type GaN layer 7 are formed forms depleted region, from superjunction theory, the electric field of E-field normal between drain electrode 11 and grid 10 that superjunction is set up, make the electric field in epitaxial loayer more even, reduce peak electric field, realize the high voltage endurance of transistor.
The preparation method of above-mentioned AlGaN/GaN HFET, comprises the steps:
(1) on described substrate 1, described n-type GaN layer 2, lightly doped p-type GaN layer 3, channel layer 4 and barrier layer 5 is grown successively by Metalorganic Chemical Vapor Deposition, as shown in Figure 5;
(2) by wet etch techniques, described lightly doped p-type GaN layer 3, channel layer 4 and barrier layer 5 are etched, form the groove 12 being communicated to described n-type GaN layer 2 by the upper surface of described barrier layer 5, and, for holding the housing region 13 of described source electrode 8, the etching depth of wherein said recessed grain requires to reach described n-type GaN layer 2, and the housing region 13 of described source electrode 8 requires to reach described lightly doped p-type GaN layer 3, as shown in Figure 6;
(3) upper surface in described housing region 13 and described barrier layer 5 makes mask, highly doped n-type GaN layer 7 described in the epitaxial growth of Metalorganic Chemical Vapor Deposition selected zone is passed through again in described groove 12, as shown in Figure 7, wherein mask does not indicate;
(4) described mask is removed, utilize photoetching technique and electron beam evaporation technique, form described source electrode 8 at described housing region, form described drain electrode 11 at the lower surface of described substrate 1, this source electrode 8 can be arranged in step, to form better contact with described lightly doped p-type GaN layer 3;
(5) physical vapor method dielectric layer growing technology is utilized, at the upper surface deposition insulating medium layer 9 of described highly doped n-type GaN layer 7, and make the end of described insulating medium layer 9 extend to described barrier layer 5, recycling photoetching technique and electron beam evaporation technique form described grid 10 on described insulating medium layer 9, obtain described AlGaN/GaN HFET.
Each technical characteristic of the above embodiment can combine arbitrarily, for making description succinct, the all possible combination of each technical characteristic in above-described embodiment is not all described, but, as long as the combination of these technical characteristics does not exist contradiction, be all considered to be the scope that this specification is recorded.
The above embodiment only have expressed several execution mode of the present invention, and it describes comparatively concrete and detailed, but can not therefore be construed as limiting the scope of the patent.It should be pointed out that for the person of ordinary skill of the art, without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection range of patent of the present invention should be as the criterion with claims.
Claims (10)
1. an AlGaN/GaN HFET, is characterized in that, comprises grid, source electrode, drain electrode, substrate, epitaxial structure and insulating medium layer, and described drain electrode, substrate, epitaxial structure are cascading;
Described epitaxial structure comprises the n-type GaN layer, vertical super-junction layer, channel layer and the barrier layer that are cascading, wherein, described vertical super-junction layer comprises the lightly doped p-type GaN layer and highly doped n-type GaN layer that are alternately arranged, the thickness of described highly doped n-type GaN layer is little compared with described lightly doped p-type GaN layer, and described channel layer and barrier layer are laminated on described lightly doped p-type GaN layer;
Described source electrode is arranged at the side of described epitaxial structure, and one end extends to the upper surface of described barrier layer, and the other end extends to described lightly doped p-type GaN layer;
Described insulating medium layer is arranged on described highly doped n-type GaN layer, and end extends to described barrier layer;
Described grid is arranged on described insulating medium layer, and end extends to the upper surface of described barrier layer.
2. AlGaN/GaN HFET according to claim 1, it is characterized in that, the thickness range of described lightly doped p-type GaN layer at 1 μm ~ 10 μm, little 100nm ~ 1 μm of thickness of the thickness more described lightly doped p-type GaN layer of described highly doped n-type GaN layer.
3. AlGaN/GaN HFET according to claim 2, is characterized in that, the doping content of described lightly doped p-type GaN layer is 10
16~ 10
17cm
-3, the doping content of described highly doped n-type GaN layer is 10
17~ 10
19cm
-3.
4. AlGaN/GaN HFET according to claim 1, is characterized in that, described n-type GaN layer is lightly doped n-type GaN layer, and doping content is 10
16~ 10
17cm
-3, thickness range is at 1 μm ~ 20 μm.
5. AlGaN/GaN HFET according to claim 1, is characterized in that, the material of described insulating medium layer is SiO
2, SiN, Al
2o
3, AlN, HfO
2, MgO, Sc
2o
3, Ga
2o
3, AlHfO
x, any one or any several combination in HfSiON, thickness is 1nm ~ 100nm.
6. the AlGaN/GaN HFET according to any one of claim 1-5, is characterized in that, described channel layer is the GaN layer of undoped, and thickness is 1nm ~ 500nm; Described barrier layer is AlGaN, AlN, AlInN layer or its combination of undoped, and thickness is 1nm ~ 50nm.
7. the AlGaN/GaN HFET according to any one of claim 1-5, is characterized in that, the material of described drain electrode and source electrode is optional from Ti/Al/Ni/Au alloy, Ti/Al/Mo/Au alloy or Ti/Al/Ti/Au alloy respectively; The material of described grid is Ni/Au alloy, Pt/Au alloy or Pd/Au alloy.
8. the AlGaN/GaN HFET according to any one of claim 1-5, it is characterized in that, described vertical super-junction layer comprises two lightly doped p-type GaN layer, and the highly doped n-type GaN layer between two lightly doped p-type GaN layer, described source electrode is symmetricly set in the relative two sides of described epitaxial structure, and one end extends to the upper surface of described barrier layer, the other end extends to described lightly doped p-type GaN layer.
9. the preparation method of the AlGaN/GaN HFET described in any one of claim 1-8, is characterized in that, comprise the steps:
(1) described n-type GaN layer, lightly doped p-type GaN layer, channel layer and barrier layer is grown successively by growth technology over the substrate;
(2) by wet method or dry etching techniques, described lightly doped p-type GaN layer, channel layer and barrier layer are etched, form the groove being communicated to described n-type GaN layer by the upper surface of described barrier layer, and, for holding the housing region of described source electrode;
(3) upper surface in described housing region and described barrier layer makes mask, then grows described highly doped n-type GaN layer by selected zone growth technology in described groove;
(4) remove described mask, utilize photoetching technique and electron beam evaporation technique, form described source electrode at described housing region, form described drain electrode at the lower surface of described substrate;
(5) dielectric layer growing technology is utilized, at the upper surface deposition insulating medium layer of described highly doped n-type GaN layer, and make the end of described insulating medium layer extend to described barrier layer, recycling photoetching technique and electron beam evaporation technique form described grid on described insulating medium layer.
10. the preparation method of AlGaN/GaN HFET according to claim 9, it is characterized in that, step (1) described growth technology and the described selected zone growth technology of step (3) are Metalorganic Chemical Vapor Deposition or molecular beam epitaxy.
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