CN105184191A - Reconfigurable physical unclonable functional circuit - Google Patents
Reconfigurable physical unclonable functional circuit Download PDFInfo
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- CN105184191A CN105184191A CN201510491295.1A CN201510491295A CN105184191A CN 105184191 A CN105184191 A CN 105184191A CN 201510491295 A CN201510491295 A CN 201510491295A CN 105184191 A CN105184191 A CN 105184191A
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
- G06F21/72—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in cryptographic circuits
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
- G06F21/76—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
- G06F21/77—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in smart cards
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2221/00—Indexing scheme relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F2221/21—Indexing scheme relating to G06F21/00 and subgroups addressing additional information or applications relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F2221/2133—Verifying human interaction, e.g., Captcha
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Abstract
The invention discloses a reconfigurable physical unclonable functional circuit. The functional circuit comprises at least one PUF unit, wherein the PUF unit comprises PUF arrays of at least two resistance voltage dividing units, each resistance voltage dividing unit generates and outputs a PUF voltage signal to a reconfiguration array that comprises at least one reconfiguration unit, the PUF arrays and the reconfiguration array are connected with a reference voltage circuit separately, an enable signal is connected to the reference voltage circuit and each PUF unit in the PUF arrays, and a reconfiguration signal is connected to each reconfiguration unit in the reconfiguration array to control each reconfiguration unit to reconfigure PUF data. Compared with an existing non-reconfigurable PUF circuit, the reconfigurable physical unclonable functional circuit of the present invention is low in circuit cost and saves circuit power consumption. By using the reconfigurable physical unclonable functional circuit, when a chip is powered down, the PUF data disappear, and even the chip is not powered down, the PUF data also can be deleted by turning off the enable signal, thereby improving system security.
Description
Technical field
The present invention relates to physics can not clone technology and information security technology, and being specifically related to a kind of restructural physics can not cloning function circuit.
Background technology
Physics can not clone technology (PhysicalUnclonableFunction, PUF) be a kind of information security technology of development in recent years.This technology have unpredictable, not reproducible, the many merits such as can not to distort, can greatly improve system encryption, false proof etc. in security.Therefore, PUF technology will have broad application prospects at information security field.
PUF technology is mainly divided into non-electronics major PUF and electrical type PUF.Non-electronics major PUF comprises optics PUF etc.Electrical type PUF, based on integrated circuit (IntegratedCircuit) manufacturing technology, uses various integrated circuit (IC)-components to form its implementing circuit, and utilizes the random deviation of integrated circuit fabrication process, realizes it uniquely and not reproducible characteristic.Therefore, electrical type PUF can realize under various integrated circuit technology, and is integrated among chip.
Except reliability, also there is strict requirement many application scenarios to the area of PUF circuit, power consumption, and some application systems are not needing in the same time to use different PUF data, namely need to be reconstructed PUF data.Realize the reconstruct of PUF data conventionally by the quantity increasing PUF circuit module, but such a process increases cost and the power consumption of chip.Therefore, a kind of low cost, low-power consumption and reconfigurable PUF circuit has important application value is designed.
Summary of the invention
For the deficiency that above-mentioned prior art exists, the invention provides a kind of restructural physics can not cloning function circuit, utilize the process deviation of resistance to produce PUF data, there is the advantages such as reliability is high, low in energy consumption, and the reconfigurable function of PUF circuit is realized with less circuit cost, do not need to increase whole PUF circuit module, the cost of chip can be reduced.
Restructural physics provided by the invention can not the feature of cloning function circuit be: described functional circuit comprises PUF array, restructuring array, reference voltage circuit, wherein:
Described PUF array comprises at least 1 PUF unit, this PUF unit comprises at least two electric resistance partial pressure unit, each electric resistance partial pressure unit produces and exports a PUF voltage signal to described restructuring array, this restructuring array comprises at least 1 reconfiguration unit, described PUF array and described restructuring array are connected with described reference voltage circuit respectively, enable signal is connected to each PUF unit in this reference voltage circuit and described PUF array, and the reconstruction signal each reconfiguration unit be connected in described restructuring array controls it and is reconstructed PUF data.
Described electric resistance partial pressure unit comprises resistance 1, resistance 2, switch 1 and switch 2, resistance 1 and resistance 2 are connected in series, this resistance 1 is connected to described PUF voltage signal with this resistance 2 link by switch 2, one end that resistance 1 is not connected with resistance 2 is connected to power supply by switch 1, one end that resistance 2 is not connected with resistance 1 is connected to ground, and switch 1 and switch 2 are by described enable signal gauge tap.
Described reference voltage circuit comprises resistance 3, resistance 4 and switch 3, resistance 3 and resistance 4 are connected in series, this resistance 3 is connected with reference voltage signal with this resistance 4 link, one end that this resistance 3 is not connected with this resistance 4 is connected to power supply by switch 3, one end that resistance 4 is not connected with resistance 3 is connected to ground, and switch 3 is by described enable signal gauge tap.
Described reconfiguration unit comprises multiselect two circuit and a comparer, PUF data are extracted, at least two PUF voltage signals that the PUF unit corresponding with reconfiguration unit exports and the reference voltage signal that reference voltage circuit exports are connected to this multiselect two circuit respectively, two voltage signals that this multiselect two circuit exports are connected to the positive-negative input end of described comparer respectively, this comparator output terminal is connected to PUF data-signal, and multiselect two circuit is controlled by reconstruction signal.
Further, described PUF array is formed by comprising the Arbitrary Matrix that m is capable, n arranges, wherein, m and n is the integer of >=1, the number of described PUF unit equals m × n, and in described restructuring array, the number of reconfiguration unit equals n, and PUF array produces m × n position PUF data-signal.At least two PUF voltage signals that each PUF unit in each row PUF unit produces are connected to a reconfiguration unit corresponding with these row PUF unit in described restructuring array, this reconfiguration unit compares at least two PUF voltages that single PUF unit produces, and produces 1 PUF data.When extracting PUF data, described enable signal selects a line PUF unit in above-mentioned PUF array to be connected to restructuring array successively, restructuring array extracts this row PUF data, has extracted rear enable signal and has then selected next line PUF unit to extract, until all PUF data are extracted.
Further improvement project is, described electric resistance partial pressure unit breaker in middle 1 and switch 2 are controlled by enable signal, when enable signal is effective, switch 1 and switch 2 conducting, electric resistance partial pressure unit is opened, resistance 1 is switched on power by switch 1, and electric resistance partial pressure unit produces the PUF voltage determined by process deviation, and PUF voltage is connected to corresponding reconfiguration unit by switch 2.When enable signal is invalid, switch 1 and switch 2 turn off, and electric resistance partial pressure unit is closed, and save power consumption.Resistance 1 and resistance 2 adopt identical size, type and layout design.The type of above-mentioned resistance is polysilicon resistance, trap resistance or thermal resistance etc.
Further improvement project is, in described reconfiguration unit, multiselect two circuit is controlled by reconstruction signal, from least two PUF voltages and reference voltage signal of input, select wherein two voltage signals to output to comparer positive-negative input end.Comparer compares two voltage signals that multiselect two circuit exports, and produces PUF data.If comparer anode input voltage is higher than negative terminal, then export PUF data 1, otherwise, then export PUF data 0.Under different reconstruction signals controls, select two different voltages to compare among multiple PUF voltage that reconfiguration unit can produce from single PUF unit and reference voltage, from same PUF unit, extract multiple different PUF data.Therefore, restructuring array can extract the different PUF data of many groups from same PUF array, realizes the reconstruct of PUF data.If in PUF unit the number of electric resistance partial pressure unit to be k, k be >=2 integer, in reconfiguration unit, multiselect two circuit selects two circuit for (k+1), then the restructural number of PUF data is 0.5 × k × (k+1).By increasing the number of electric resistance partial pressure unit in PUF unit, the restructural number of PUF data can be increased.
In described reference voltage circuit, resistance 3 and resistance 4 adopt identical size and type, and adopt larger width and length dimension to design and domain matched design, the process deviation of this resistance 3 and resistance 4 is minimized, to produce an accurate reference voltage signal.
The described extraction of PUF data and the step of reconstruct comprise:
Step one, external control circuit starts to extract PUF data, sends effective enable signal and reconstruction signal, if desired reconstructs PUF data, then use the reconstruction signal different from last fetched, if do not need reconstruct PUF data, then uses identical reconstruction signal;
Step 2, reference voltage circuit receives enable signal, and produce reference voltage, be connected to each reconfiguration unit, PUF array received, to enable signal, opens PUF unit, and each PUF unit produces multiple PUF voltage signal, is connected to corresponding reconfiguration unit;
Step 3, restructuring array receives reconstruction signal, and reconfiguration unit to produce multiple PUF voltage signal and reference voltage from PUF unit according to reconstruction signal selects two corresponding voltage signals to compare, and produces PUF data;
Step 4, external control circuit reads all PUF data that restructuring array produces, and after completing the extraction of PUF data, close enable signal, circuit shut-down, PUF data disappear.
Restructural physics provided by the invention can not cloning function circuit, compare existing not restructural PUF circuit, by increasing a reference voltage circuit or increase an electric resistance partial pressure unit in PUF unit, restructural PUF circuit can be realized, the number of further increase electric resistance partial pressure unit then can obtain the approximate restructural number with quadratic relationship, and circuit cost is low.The circuit do not used can be enabled signal at stop, saves circuit power consumption.Can according to the structure of practical application request flexible design PUF circuit, to realize minimum cost and power consumption.Chip power-down, PUF data disappear, even if chip not power down, also can delete PUF data, improving security of system by closing enable signal.
Accompanying drawing explanation
Fig. 1 is the electrical block diagram of the embodiment of the present invention;
Fig. 2 is PUF cell schematics in the embodiment of the present invention;
Fig. 3 is electric resistance partial pressure cell schematics in the embodiment of the present invention;
Fig. 4 is reference voltage circuit schematic diagram in the embodiment of the present invention;
Fig. 5 is reconfiguration unit schematic diagram in the embodiment of the present invention.
Embodiment
Below in conjunction with drawings and Examples, the specific embodiment of the present invention is further described, easily implements the present invention to enable those skilled in the art.
Shown in Figure 1, the restructural physics that the present embodiment provides can not cloning function circuit, and comprise PUF array, restructuring array and reference voltage circuit, described PUF array and restructuring array are connected with described reference voltage circuit respectively.Described PUF array comprises at least 1 PUF unit, and this PUF unit comprises at least two electric resistance partial pressure unit, and each electric resistance partial pressure unit produces a PUF voltage signal to described restructuring array, and enable signal is connected to this PUF unit controls, and it opens or closes.Enable signal is connected to described reference voltage circuit simultaneously, controls opening or closing of reference voltage circuit.Described restructuring array comprises at least 1 reconfiguration unit, and this reconfiguration unit comprises 1 multiselect two circuit and 1 comparer, extracts PUF data, and reconstruction signal is connected to reconfiguration unit and controls it and be reconstructed PUF data.Reference voltage circuit comprises two series connection divider resistances, output reference voltage signal.
In the present embodiment circuit, if PUF array adopts the matrix structure of 1 × n, this PUF array has 1 × n PUF unit, each PUF unit comprises two electric resistance partial pressure unit, restructuring array comprises n reconfiguration unit, and in reconfiguration unit, multiselect two circuit is three select two circuit, then can obtain the embodiment of the present invention as shown in Figure 1.
As shown in Figure 1, described PUF array is made up of n PUF unit, and described restructuring array is made up of n reconfiguration unit, and n is the integer of >=1, and the large I of n is determined the demand of PUF data bits according to practical application.At least two PUF voltage signals that in PUF array, each PUF unit exports are connected to reconfiguration unit corresponding with these row PUF unit in described restructuring array.This reconfiguration unit comprises multiselect two circuit and a comparer, extracts PUF data, and this reconfiguration unit compares at least two PUF voltages that single PUF unit produces, and produces 1 PUF data.The enable signal of outside input is connected to each PUF unit in PUF array and reference voltage circuit.The reconstruction signal of outside input is connected to each reconfiguration unit in restructuring array.When extracting PUF data, described enable signal selects a line PUF unit in above-mentioned PUF array to be connected to restructuring array successively, restructuring array extracts this row PUF data, has extracted rear enable signal and has then selected next line PUF unit to extract, until all PUF data are extracted.Reconfiguration unit carries out rear exportable 1 the PUF data of extraction to PUF unit, and whole restructuring array extracts rear output n position PUF data to PUF array.The reference voltage signal that reference voltage circuit exports also is connected to this multiselect two circuit, and two voltage signals that this multiselect two circuit exports are connected to the positive-negative input end of described comparer respectively, and this comparator output terminal is connected to PUF data-signal.
Fig. 2 is the schematic diagram of above-mentioned PUF unit, and it comprises electric resistance partial pressure unit 1 and electric resistance partial pressure unit 2, and this electric resistance partial pressure unit 1 is identical with the circuit of electric resistance partial pressure unit 2.Electric resistance partial pressure unit 1 produces and exports PUF voltage 1, and electric resistance partial pressure unit 2 produces and exports PUF voltage 2.Enable signal is connected to electric resistance partial pressure unit 1 and electric resistance partial pressure unit 2, controls opening or closing of these two electric resistance partial pressure unit.
Fig. 3 is the schematic diagram of above-mentioned electric resistance partial pressure unit 1 or electric resistance partial pressure unit 2, and it comprises resistance 1, resistance 2, switch 1 and switch 2.Resistance 1 and resistance 2 are connected in series, this resistance 1 and resistance 2 link are connected to one end of switch 2, the other end of switch 2 is connected to PUF voltage signal, the other end that resistance 1 is not connected with resistance 2 is connected to one end of switch 1, the other end of switch 1 is connected to power supply, and the other end that resistance 2 is not connected with resistance 1 is connected to ground.Enable signal is connected to switch 1 and switch 2, controls the turn-on and turn-off of above-mentioned two switches.When enable signal is effective, switch 1 and switch 2 conducting, electric resistance partial pressure unit 1 or electric resistance partial pressure unit 2 are opened, resistance 1 is switched on power by switch 1, resistance 1 and resistance 2 produce an effective PUF voltage signal by dividing potential drop, this PUF voltage signal is determined by integrated circuit fabrication process deviation, and this PUF voltage signal connects the reconfiguration unit exporting correspondence to by switch 2.The conducting resistance of switch 1 and switch 2 is much smaller than the resistance of resistance 1 and resistance 2.When enable signal is invalid, switch 1 and switch 2 turn off, and electric resistance partial pressure unit 1 or electric resistance partial pressure unit 2 are closed, and the PUF voltage of output is invalid.Resistance 1 and resistance 2 adopt identical type, size and layout design, and the type of resistance 1 and resistance 2 is polysilicon resistance, trap resistance or thermal resistance etc.The size of the PUF voltage that electric resistance partial pressure unit produces is determined by the resistance of resistance 1 and resistance 2, and the resistance size of resistance 1 and resistance 2 is determined by the process deviation of resistance.Therefore, the size of above-mentioned PUF voltage determines to have randomness by the process deviation of resistance, unpredictable and not reproducible, or higher than ideal value, or lower than ideal value, there is certain deviation with ideal value, and also there is certain deviation between the PUF voltage of different electric resistance partial pressure unit generation.
Fig. 4 is the schematic diagram of above-mentioned reference voltage circuit, and it comprises resistance 3, resistance 4 and switch 3.Resistance 3 and resistance 4 are connected in series, and this resistance 3 and resistance 4 link are connected to the reference voltage signal of output, and the other end that resistance 3 is not connected with resistance 4 is connected to one end of switch 3, and the other end of switch 3 is connected to power supply.The other end that resistance 4 is not connected with resistance 3 is connected to ground.Enable signal is connected to switch 3, the turn-on and turn-off of gauge tap 3.When enable signal is effective, switch 3 conducting, resistance 3 is switched on power by switch 3, and resistance 3 and resistance 4 produce an effective reference voltage signal by dividing potential drop and is connected to output.The conducting resistance of switch 3 is much smaller than the resistance of resistance 3 and resistance 4.When enable signal is invalid, switch 3 turns off, and the reference voltage of output is invalid.Resistance 3 and resistance 4 adopt identical type and size on circuit realiration, and adopt larger width and length dimension, layout design is strictly mated, as adopted the domain matching techniques such as common centroid, reduce the process deviation that above-mentioned two resistance produces in the fabrication process as far as possible, produce a comparatively accurate reference voltage by dividing potential drop, the size of this reference voltage is approximately equal to the ideal value of the PUF voltage that above-mentioned electric resistance partial pressure unit produces.
Fig. 5 is the schematic diagram of described reconfiguration unit, and it comprises one three and selects two circuit and a comparer.The reference voltage that this three PUF voltage 1 selecting two circuit to receive described PUF unit to export, PUF voltage 2 and reference voltage circuit export, as three input signals.Reconstruction signal is connected to three and selects two circuit, controls three and selects two circuit from three input signals, select two corresponding voltage signals, be connected to the positive-negative input end of comparer respectively.Comparer compares two voltage signals that three select two circuit to export, if the voltage signal of positive input terminal is higher than negative input end, then comparer exports data 1, otherwise then export data 0, reconfiguration unit produces 1 PUF data according to the method described above.Three select two circuit from three input signals, select two signals compares and has three kinds and effectively select: reference voltage and PUF voltage 1, reference voltage and PUF voltage 2, PUF voltage 1 and PUF voltage 2.Therefore, reconfiguration unit, under the control of different reconstruction signals, can extract 3 different PUF data from a PUF unit, and restructuring array can extract 3 groups of different PUF data from PUF array, by changing reconstruction signal, can realize the reconstruct to PUF data.The PUF voltage 1 exported due to PUF unit, the relative size of PUF voltage 2 and reference voltage are determined by the random process deviation produced in resistance manufacture process, the PUF data that reconfiguration unit extracts also are determined by above-mentioned process deviation, there is uniqueness, unpredictable, and not reproducible and distort.
The process extracted PUF data below and reconstruct is described:
(1) external control circuit needs to use PUF data, starts to extract PUF data, sends effective enable signal and reconstruction signal.If desired reconstruct PUF data, then use the reconstruction signal different from last fetched, if do not need reconstruct PUF data, then use identical reconstruction signal.
(2) PUF array received is to enable signal, opens each PUF unit of its inside.PUF unit, under the control of enable signal, opens electric resistance partial pressure unit 1 and the electric resistance partial pressure unit 2 of its inside.Each electric resistance partial pressure unit is under the control of enable signal, and inner switch 1 and switch 2 conducting, resistance 1 switches on power, and resistance 1 and resistance 2 produce a PUF voltage signal by dividing potential drop, and are connected to output by switch 2.PUF unit produces PUF voltage 1 and PUF voltage 2 respectively by electric resistance partial pressure unit 1 and electric resistance partial pressure unit 2, is connected to reconfiguration unit corresponding in restructuring array.The size of above-mentioned two PUF voltage signals is determined by the process deviation of resistance, and there is certain deviation between ideal value.
(3) reference voltage circuit receives enable signal, and inner switch 3 conducting, resistance 3 switches on power, and resistance 3 and resistance 4 produce a reference voltage signal by electric resistance partial pressure, are connected to each reconfiguration unit in restructuring array.Above-mentioned reference voltage is approximately equal to the ideal value of the PUF voltage signal that PUF unit produces.
(4) in restructuring array, each reconfiguration unit receives reconstruction signal.In reconfiguration unit, three select two circuit according to reconstruction signal, select two corresponding voltage signals, and output to the positive-negative input end of comparer from PUF voltage 1, PUF voltage 2 and reference voltage three input signals.Such as, if external control circuit sends the first reconstruction signal, three select two circuit to select reference voltage and PUF voltage 1 to export.Send the second reconstruction signal, three select two circuit to select reference voltage and PUF voltage 2 to export.Send reconstructed signal, three select two circuit to select PUF voltage 1 and PUF voltage 2 to export.Two voltage signals of comparer to input compare, and produce 1 PUF data.If the voltage signal of comparer positive input terminal is higher than negative input end, then comparer exports PUF data 1, otherwise, then export PUF data 0.Restructuring array extracts PUF unit each in PUF array, produces the one group PUF data corresponding with current reconstruction signal.
(5) external control circuit reads all PUF data that restructuring array produces, and after completing the extraction of PUF data, external control circuit closes enable signal, circuit shut-down, and PUF data disappear.
If external control circuit needs to extract different PUF data, by arranging different reconstruction signals in step (1), then step (2), (3), (4), (5) are repeated, then can extract the one group PUF data corresponding with the reconstruction signal of current setting, realize the reconstruct to PUF data.
Claims (10)
1. restructural physics can not a cloning function circuit, and it is characterized in that, described functional circuit comprises PUF array, restructuring array, reference voltage circuit, wherein:
Described PUF array comprises at least 1 PUF unit, this PUF unit comprises at least two electric resistance partial pressure unit, each electric resistance partial pressure unit produces and exports a PUF voltage signal to described restructuring array, this restructuring array comprises at least 1 reconfiguration unit, described PUF array and described restructuring array are connected with described reference voltage circuit respectively, enable signal is connected to each PUF unit in this reference voltage circuit and described PUF array, and the reconstruction signal each reconfiguration unit be connected in described restructuring array controls it and is reconstructed PUF data.
2. restructural physics according to claim 1 can not cloning function circuit, it is characterized in that: described electric resistance partial pressure unit comprises resistance 1, resistance 2, switch 1 and switch 2, resistance 1 and resistance 2 are connected in series, this resistance 1 is connected to described PUF voltage signal with this resistance 2 link by switch 2, one end that resistance 1 is not connected with resistance 2 is connected to power supply by switch 1, one end that resistance 2 is not connected with resistance 1 is connected to ground, and switch 1 and switch 2 are by described enable signal gauge tap.
3. restructural physics according to claim 2 can not cloning function circuit, it is characterized in that: described electric resistance partial pressure unit breaker in middle 1 and switch 2 are controlled by enable signal, when enable signal is effective, switch 1 and switch 2 conducting, electric resistance partial pressure unit is opened, resistance 1 is switched on power by switch 1, and electric resistance partial pressure unit produces the PUF voltage determined by process deviation, and PUF voltage is connected to corresponding reconfiguration unit by switch 2; When enable signal is invalid, switch 1 and switch 2 turn off, and electric resistance partial pressure unit is closed.
4. restructural physics according to claim 2 can not cloning function circuit, it is characterized in that: in described electric resistance partial pressure unit, resistance 1 and resistance 2 adopt identical size, type and layout design, the type of this resistance 1 and resistance 2 is polysilicon resistance, trap resistance or thermal resistance.
5. restructural physics according to claim 1 can not cloning function circuit, it is characterized in that: described reference voltage circuit comprises resistance 3, resistance 4 and switch 3, resistance 3 and resistance 4 are connected in series, this resistance 3 is connected with reference voltage signal with this resistance 4 link, one end that this resistance 3 is not connected with this resistance 4 is connected to power supply by switch 3, one end that resistance 4 is not connected with resistance 3 is connected to ground, and switch 3 is by described enable signal gauge tap.
6. restructural physics according to claim 5 can not cloning function circuit, it is characterized in that: in described reference voltage circuit, resistance 3 and resistance 4 adopt identical size and type, and adopts domain matched design.
7. restructural physics according to claim 1 can not cloning function circuit, it is characterized in that: described PUF array is formed by comprising the Arbitrary Matrix that m is capable, n arranges, wherein, m and n is the integer of >=1, the number of described PUF unit equals m × n, in described restructuring array, the number of reconfiguration unit equals n, and PUF array produces m × n position PUF data-signal; At least two PUF voltage signals that each PUF unit in each row PUF unit produces are connected to a reconfiguration unit corresponding with these row PUF unit in described restructuring array, this reconfiguration unit compares at least two PUF voltages that single PUF unit produces, and produces 1 PUF data.
8. restructural physics according to claim 1 can not cloning function circuit, it is characterized in that: described reconfiguration unit comprises multiselect two circuit and a comparer, PUF data are extracted, at least two PUF voltage signals that the PUF unit corresponding with reconfiguration unit exports and the reference voltage signal that reference voltage circuit exports are connected to this multiselect two circuit respectively, two voltage signals that this multiselect two circuit exports are connected to the positive-negative input end of described comparer respectively, this comparator output terminal is connected to PUF data-signal, multiselect two circuit is controlled by reconstruction signal.
9. restructural physics according to claim 1 can not cloning function circuit, it is characterized in that: in described reconfiguration unit, multiselect two circuit is controlled by reconstruction signal, from least two PUF voltages and reference voltage signal of input, select wherein two voltage signals to output to comparer positive-negative input end; Comparer compares two voltage signals that multiselect two circuit exports, and produces PUF data; If comparer anode input voltage is higher than negative terminal, then export PUF data 1, otherwise, then export PUF data 0; Under different reconstruction signals controls, two different voltages are selected to compare among multiple PUF voltage that reconfiguration unit can produce from single PUF unit and reference voltage, multiple different PUF data are extracted from same PUF unit, realize the reconstruct of PUF data, if the number of electric resistance partial pressure unit is k in PUF unit, k is the integer of >=2, in reconfiguration unit, multiselect two circuit selects two circuit for (k+1), then the restructural number of PUF data is 0.5 × k × (k+1).
10. restructural physics according to claim 1 can not cloning function circuit, it is characterized in that: the described extraction of functional circuit PUF data and the step of reconstruct comprise:
Step one, external control circuit starts to extract PUF data, sends effective enable signal and reconstruction signal, if desired reconstructs PUF data, then use the reconstruction signal different from last fetched, if do not need reconstruct PUF data, then uses identical reconstruction signal;
Step 2, reference voltage circuit receives enable signal, and produce reference voltage, be connected to each reconfiguration unit, PUF array received, to enable signal, opens PUF unit, and each PUF unit produces multiple PUF voltage signal, is connected to corresponding reconfiguration unit;
Step 3, restructuring array receives reconstruction signal, and reconfiguration unit to produce multiple PUF voltage signal and reference voltage from PUF unit according to reconstruction signal selects two corresponding voltage signals to compare, and produces PUF data;
Step 4, external control circuit reads all PUF data that restructuring array produces, and after completing the extraction of PUF data, close enable signal, circuit shut-down, PUF data disappear.
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| CN107766749A (en) * | 2017-11-15 | 2018-03-06 | 北京中电华大电子设计有限责任公司 | A kind of circuit implementing method of the unclonable function of physics |
| CN107292200B (en) * | 2017-05-02 | 2018-07-10 | 湖北工业大学 | Strong PUF circuit structures based on switching capacity |
| CN108880818A (en) * | 2017-05-16 | 2018-11-23 | 三星电子株式会社 | The unclonable functional circuit of physics, system and integrated circuit with this function |
| CN110535651A (en) * | 2018-05-23 | 2019-12-03 | 美国亚德诺半导体公司 | The unclonable function of physics based on impedance |
| CN110851884A (en) * | 2019-10-14 | 2020-02-28 | 西安交通大学 | FPGA-based arbitration PUF Trojan horse detection and reuse method |
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| CN110535651A (en) * | 2018-05-23 | 2019-12-03 | 美国亚德诺半导体公司 | The unclonable function of physics based on impedance |
| US10560095B2 (en) | 2018-05-23 | 2020-02-11 | Analog Devices, Inc. | Impedance-based physical unclonable function |
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| CN111385091B (en) * | 2018-12-31 | 2024-05-24 | 三星电子株式会社 | Integrated circuit and device for security of physically unclonable functions |
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| CN111695162B (en) * | 2019-03-13 | 2023-03-28 | 中芯国际集成电路制造(上海)有限公司 | Device for generating a PUF signature |
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| CN110851884B (en) * | 2019-10-14 | 2021-09-03 | 西安交通大学 | FPGA-based arbitration PUF Trojan horse detection and reuse method |
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| US12041188B2 (en) * | 2020-08-06 | 2024-07-16 | Samsung Electronics Co., Ltd. | Security device including physical unclonable function cells and operation method thereof |
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