CN104637909A - Three-dimensional chip integration structure and machining process thereof - Google Patents
Three-dimensional chip integration structure and machining process thereof Download PDFInfo
- Publication number
- CN104637909A CN104637909A CN201510046297.XA CN201510046297A CN104637909A CN 104637909 A CN104637909 A CN 104637909A CN 201510046297 A CN201510046297 A CN 201510046297A CN 104637909 A CN104637909 A CN 104637909A
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- China
- Prior art keywords
- chip
- substrate
- keyset
- salient point
- metal
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92143—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a bump connector
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention provides a three-dimensional chip integration structure, which has the advantages of simple structure, low manufacturing process requirement, reduction of TSV (Through Silicon Via) manufacturing process steps and well lowering of the process cost. The three-dimensional chip integration structure comprises a substrate, and is characterized in that an adapting board is connected with the substrate through welding balls or salient points; the chip is connected with the adapting board through a first metal bonding pad or a first salient point; the substrate is provided with a metal column structure; the chip is connected with the metal column structure through a second metal bonding pad or a second salient point. The invention simultaneously provides a three-dimensional chip integration structure machining process.
Description
Technical field
The present invention relates to the technical field of the method for micro-electronic manufacturing or process semiconductor or solid state device, be specifically related to a kind of three-dimensional chip integrated morphology and processing technology thereof.
Background technology
Along with the continuous progress of microelectric technique, the characteristic size of integrated circuit constantly reduces, and interconnection density improves constantly.The requirement of user to high-performance low power consumption simultaneously improves constantly.In this case, by reducing the live width of interconnection line further to propose the restriction that high performance mode is subject to physical characteristics of materials and apparatus and process, the resistance capacitance (RC) of two-dimentional interconnection line postpones the bottleneck becoming the raising of restriction semiconductor core piece performance gradually.Silicon perforation (Through Silicon Via, being called for short TSV) technique forms metal upright post by being combined in wafer, and be equipped with metal salient point, can to realize between wafer (chip) or direct three-dimensional interconnection between chip and substrate, the limitation of conventional semiconductor chip two dimension wiring can be made up like this.This interconnection mode and traditional Stack Technology as have compared with bonding techniques the stacking density of three-dimensional large, encapsulate the advantages such as overall dimension is afterwards little, thus greatly improve the speed of chip and reduce power consumption.TSV technology needs through series of process steps such as deep hole etching, insulating layer deposition, seed layer deposition, plating, chemico-mechanical polishings, and technique is loaded down with trivial details, and manufacturing cost is high, high to the requirement of equipment, and this is one of reason restricting its extensive use at present.
Summary of the invention
For the problems referred to above, the invention provides a kind of three-dimensional chip integrated morphology, its structure is simple, manufacture process requirement is low, decrease TSV manufacturing technology steps, reduce process costs preferably, the present invention additionally provides a kind of three-dimensional chip integrated morphology processing technology simultaneously.
Its technical scheme of the present invention is such: a kind of three-dimensional chip integrated morphology, it comprises substrate, keyset connects described substrate by soldered ball or salient point, chip connects described keyset by the first metal pad or the first salient point, described substrate is provided with metal column structures, and described chip connects described metal column structures by the second metal pad or the second salient point.
It improves further and is: multiple described keyset connects described substrate respectively by soldered ball or salient point; Described chip connects described substrate by multiple metal column structures.
A kind of three-dimensional chip integrated morphology processing technology, comprises the following steps:
(1), on silicon or glass wafer, manufacture the keyset of carries chips, forming keyset is zone line hollow out, peripheral regions wiring, the two-sided structure containing pad;
(2), chip connects described keyset by the first metal pad or the first salient point, and the peripheral regions of chip and keyset is formed and interconnects;
(3) on substrate, form metal column structures and plant soldered ball;
(4), chip by the second metal pad or the second salient point connection metal rod structure, realize substrate and chip and keyset assembly and connection.
In said structure of the present invention, because substrate and keyset are interconnected by soldered ball or bump structure, chip passes through pad or salient point and keyset and interconnects, achieve substrate and connect chip by keyset, on substrate, metal column and chip pass through pad or salient point direct interconnection simultaneously, to realize between chip or direct three-dimensional interconnection between chip and substrate, avoid TSV structure, decrease the manufacturing process such as Deep hole electroplating, physical vapour deposition (PVD), annealing, chemico-mechanical polishing that TSV machining needs, greatly reduce process costs.
Accompanying drawing explanation
Fig. 1 is three-dimensional chip integrated morphology generalized section of the present invention;
Fig. 2 is the schematic top plan view of Fig. 1;
Fig. 3 is the keyset schematic diagram manufacturing carries chips;
Fig. 4 is that chip and keyset interconnect schematic diagram;
Fig. 5 is forming metal post schematic diagram on substrate;
Soldered ball schematic diagram planted by substrate to Fig. 6;
Fig. 7 is structural representation after assembling.
Embodiment
The invention will be further described with reference to the accompanying drawings,
See Fig. 1, Fig. 2, a kind of three-dimensional chip integrated morphology, it comprises substrate 7, keyset 4 is by soldered ball or salient point 5 connection substrate 7, chip 1 connects keyset 4 by the first metal pad or the first salient point 3, substrate 7 is provided with multiple metal column structures 6, chip 1 is by the second metal pad or the second salient point 8 connection metal rod structure 6.
Two keysets 4 are respectively by soldered ball or salient point 5 connection substrate 7, achieve the interconnection of two chips and substrate, two chips 1,2 realize two chips and substrate interconnection by two keysets is have employed in the present embodiment, certainly multiple quantity chip and keyset can be adopted to interconnect, also multiple keysets of other quantity can be adopted, realize multiple chip realizes multiple chip and substrate interconnection by multiple keyset, realize multiple chip that substrate interconnects, reduce the encapsulation volume of chip and substrate further, reduce the characteristic size of integrated circuit.
A kind of three-dimensional chip integrated morphology processing technology, it comprises the following steps:
See Fig. 3, (1), shaping double-sided wiring and pad structure on Silicon Wafer or glass wafer 4, and form the structure that keyset 4 is zone line hollow out, peripheral regions wiring; See Fig. 4, (3), chip 1,2 connects keyset 4 by the first metal pad or the first salient point 3, and chip 1 is formed with the peripheral regions of keyset and interconnects;
See Fig. 5, (4), on organic substrate or glass substrate 7, form metal column structures with high-aspect-ratio;
See Fig. 6, (5), on organic substrate or glass substrate 7, plant soldered ball;
See Fig. 7, (6), chip by the second metal pad or the second salient point 8 connection metal rod structure 6, realize substrate and chip and keyset assembly and connection.
In said structure of the present invention and technique, owing to being formed in the interconnection of Silicon Wafer or glass wafer substrate and chip on organic substrate or glass substrate by keyset, without the need to TSV technology, decrease TSV manufacturing technology steps, reduce process costs preferably, the integrated technique of can avoiding of three-dimensional chip without the need to TSV technology is loaded down with trivial details, and manufacturing cost is high, to the high various problems of the requirement of equipment.
Claims (4)
1. a three-dimensional chip integrated morphology, it comprises substrate, it is characterized in that: keyset connects described substrate by soldered ball or salient point, chip connects described keyset by the first metal pad or the first salient point, described substrate is provided with metal column structures, and described chip connects described metal column structures by the second metal pad or the second salient point.
2. a kind of three-dimensional chip integrated morphology according to claim 1, is characterized in that: multiple described keyset connects described substrate respectively by soldered ball or salient point.
3. a kind of three-dimensional chip integrated morphology according to claims 1 or 2, is characterized in that: described chip connects described substrate by multiple metal column structures.
4. a three-dimensional chip integrated morphology processing technology, is characterized in that, it comprises the following steps:
(1), on silicon or glass wafer, manufacture the keyset of carries chips, forming keyset is zone line hollow out, peripheral regions wiring, the two-sided structure containing pad;
(2), chip connects described keyset by the first metal pad or the first salient point, and the peripheral regions of chip and keyset is formed and interconnects;
(3) on substrate, form metal column structures and plant soldered ball;
(4), chip by the second metal pad or the second salient point connection metal rod structure, realize substrate and chip and keyset assembly and connection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201510046297.XA CN104637909A (en) | 2015-01-30 | 2015-01-30 | Three-dimensional chip integration structure and machining process thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510046297.XA CN104637909A (en) | 2015-01-30 | 2015-01-30 | Three-dimensional chip integration structure and machining process thereof |
Publications (1)
| Publication Number | Publication Date |
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| CN104637909A true CN104637909A (en) | 2015-05-20 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201510046297.XA Pending CN104637909A (en) | 2015-01-30 | 2015-01-30 | Three-dimensional chip integration structure and machining process thereof |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109935604A (en) * | 2019-02-26 | 2019-06-25 | 厦门云天半导体科技有限公司 | A kind of integrate is routed three-dimensional chip encapsulating structure of pinboard and preparation method thereof again |
| WO2020216029A1 (en) * | 2019-04-23 | 2020-10-29 | Oppo广东移动通信有限公司 | Laminated board and terminal device |
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| US20140048928A1 (en) * | 2012-08-17 | 2014-02-20 | Cisco Technology, Inc. | Multi-Chip Module with Multiple Interposers |
| CN103824843A (en) * | 2012-11-13 | 2014-05-28 | Lsi公司 | Multi-chip module connection by way of bridging blocks |
| CN104011851A (en) * | 2011-12-22 | 2014-08-27 | 英特尔公司 | 3d integrated circuit package with window interposer |
| US20140264836A1 (en) * | 2013-03-15 | 2014-09-18 | Qualcomm Incorporated | System-in-package with interposer pitch adapter |
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2015
- 2015-01-30 CN CN201510046297.XA patent/CN104637909A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1835229A (en) * | 2005-03-16 | 2006-09-20 | 索尼株式会社 | Semiconductor device and method of manufacturing semiconductor device |
| CN102460690A (en) * | 2009-06-24 | 2012-05-16 | 英特尔公司 | Multi-chip package and method of providing die-to-die interconnects in same |
| CN104011851A (en) * | 2011-12-22 | 2014-08-27 | 英特尔公司 | 3d integrated circuit package with window interposer |
| CN103187377A (en) * | 2011-12-28 | 2013-07-03 | 美国博通公司 | Semiconductor package with a bridge interposer |
| CN103187396A (en) * | 2011-12-28 | 2013-07-03 | 美国博通公司 | Semiconductor package with ultra-thin interposer without through-semiconductor vias |
| US20140048928A1 (en) * | 2012-08-17 | 2014-02-20 | Cisco Technology, Inc. | Multi-Chip Module with Multiple Interposers |
| CN103824843A (en) * | 2012-11-13 | 2014-05-28 | Lsi公司 | Multi-chip module connection by way of bridging blocks |
| US20140264836A1 (en) * | 2013-03-15 | 2014-09-18 | Qualcomm Incorporated | System-in-package with interposer pitch adapter |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109935604A (en) * | 2019-02-26 | 2019-06-25 | 厦门云天半导体科技有限公司 | A kind of integrate is routed three-dimensional chip encapsulating structure of pinboard and preparation method thereof again |
| WO2020216029A1 (en) * | 2019-04-23 | 2020-10-29 | Oppo广东移动通信有限公司 | Laminated board and terminal device |
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Application publication date: 20150520 |
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