CN104538378A - Wafer level package structure and technological method thereof - Google Patents

Wafer level package structure and technological method thereof Download PDF

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Publication number
CN104538378A
CN104538378A CN201410827464.XA CN201410827464A CN104538378A CN 104538378 A CN104538378 A CN 104538378A CN 201410827464 A CN201410827464 A CN 201410827464A CN 104538378 A CN104538378 A CN 104538378A
Authority
CN
China
Prior art keywords
lead frame
disk
wafer
salient point
package structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201410827464.XA
Other languages
Chinese (zh)
Inventor
王亚琴
梁志忠
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
JCET Group Co Ltd
Original Assignee
Jiangsu Changjiang Electronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jiangsu Changjiang Electronics Technology Co Ltd filed Critical Jiangsu Changjiang Electronics Technology Co Ltd
Priority to CN201410827464.XA priority Critical patent/CN104538378A/en
Publication of CN104538378A publication Critical patent/CN104538378A/en
Pending legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/94Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

The invention relates to a wafer level package structure and a technological method of the wafer level package structure. The structure comprises lead frames (1), a chip (2) is inversely installed on the lead frames (1), metal protrusions (3) are arranged on the front face of the chip (2), the metal protrusions (3) are connected with the lead frames (1) through tin balls (4), the peripheries of the lead frames (1), the metal protrusions (3) and the tin balls (4) are packaged by a plastic packaging material (5), and metal layers are electroplated on the back faces of the lead frames (1). According to the wafer level package structure and the technological method of the wafer level package structure, a drawing on a wafer completely is designed to correspond to drawings on the lead frames, the aim that the whole wafer can be inversely mounted on the lead frames is achieved, then, cutting separation and packaging are carried out on the wafer, and the wafer level packaging with the size of the single chip equal to that of a single Unit of the lead frames is achieved.

Description

A kind of wafer-level package structure and process thereof
Technical field
The present invention relates to a kind of wafer-level package structure and process thereof, belong to technical field of semiconductor encapsulation.
Background technology
Existing wafer level packaging, first scribing is carried out to disk, the chip front side be separated after completing scribing is pasted onto on support plate, again plastic packaging is carried out to the side of support plate adhering chip, remove support plate, exposed chip front, carries out Fanout to chip front side electrode and reroutes and make metallic circuit and the electrical output of product.After disk scribing, single chips arrangement is pasted onto on support plate and carries out encapsulating, making Fanout metallic circuit, the efficiency of arrangements of chips contraposition is low on the one hand, and separating chips arrangement contraposition easily produces offset deviation, this will cause the skew of follow-up chip front side Fanout metallic circuit; Carry out because disk Fanout is encapsulated in encapsulation factory, but carrying out for encapsulation factory the close pitch lines that Fanout technique relates to makes, difficulty is higher, and easily occur the problem that line short, circuit are peeled off, yield is on the low side.
Summary of the invention
The object of the invention is to overcome above-mentioned deficiency, a kind of wafer-level package structure and process thereof are provided, plan design on disk is completely corresponding with the drawing of lead frame, realize the upside-down mounting of full wafer disk in lead frame, carry out cutting and separating and the encapsulation of disk again, realize the wafer-level packaging that single chips size is equal to lead frame single Unit.
The object of the present invention is achieved like this: a kind of wafer-level package structure, it comprises lead frame, on described lead frame, upside-down mounting has chip, described chip front side is provided with metal salient point, described metal salient point is connected by tin ball with between lead frame, be encapsulated with plastic packaging material around described lead frame, metal salient point and tin ball, the described leadframe back side is electroplate with metal level.
A process for wafer-level package structure, said method comprising the steps of:
Step one, get a disk, disk front line design corresponds to lead frame drawing completely, and single chips size is equal to package dimension;
Step 2, on disk front electrode, make metal salient point;
Step 3, on metal salient point, make tin ball;
Step 4, by disk by the tin ball upside-down mounting on metal salient point in lead frame, lead frame single product size is equal to single chips size;
Step 5, the disk and lead frame that complete upside-down mounting are put into solder reflow device carry out Reflow Soldering;
Step 6, the product completing Reflow Soldering to be encapsulated;
Step 7, the plating of the lead frame back side is carried out to the product completing encapsulating;
Step 8, UV film is coated to the chip back completing electroplated product;
Step 9, the product completing plating to be cut, be separated single product;
The UV film that step 10, removal chip back are coating.
Described disk front circuit carries out Fanout design according to lead frame drawing or lead frame drawing carries out matched design according to disk front circuit.
Compared with prior art, the present invention has following beneficial effect:
1, chip reroutes to make and is completed by the wafer FAB factory of being good at separately and encapsulation factory respectively with encapsulation, and product yield is higher;
2, lead frame single Unit size is equal to independent chip size, not only make use of die-attach area substantially, and can shorten product sizes, improves the utilance of lead frame, reduces material cost;
3, the upside-down mounting of full wafer disk completes, substantially increases production efficiency, reduces production cost.
Accompanying drawing explanation
Fig. 1 is the structural representation of a kind of wafer-level package structure of the present invention.
Fig. 2 ~ Figure 11 is each operation schematic diagram of a kind of wafer-level package structure of the present invention process.
Wherein:
Lead frame 1
Chip 2
Metal salient point 3
Tin ball 4
Plastic packaging material 5
Metal level 6.
Embodiment
See Fig. 1, a kind of wafer-level package structure of the present invention, it comprises lead frame 1, on described lead frame 1, upside-down mounting has chip 2, described chip 2 front is provided with metal salient point 3, described metal salient point 3 is connected by tin ball 4 with between lead frame 1, is encapsulated with plastic packaging material 5 around described lead frame 1, metal salient point 3 and tin ball 4, and described leadframe 1 back side is electroplate with metal level 6.
Its process is as follows:
Step one, see Fig. 2, get a disk, disk front line design corresponds to lead frame drawing completely, and single chips size is equal to package dimension;
Step 2, see Fig. 3, disk front electrode makes metal salient point;
Step 3, see Fig. 4, metal salient point makes tin ball;
Step 4, see Fig. 5, by disk by the tin ball upside-down mounting on metal salient point in lead frame, lead frame single product size is equal to single chips size;
Step 5, see Fig. 6, the disk and lead frame that complete upside-down mounting are put into solder reflow device and carries out Reflow Soldering;
Step 6, see Fig. 7, the product completing Reflow Soldering to be encapsulated;
Step 7, see Fig. 8, the plating of the lead frame back side is carried out to the product completing encapsulating;
Step 8, see Fig. 9, UV film is coated to the chip back completing electroplated product;
Step 9, see Figure 10, the product completing plating to be cut, be separated single product;
Step 10, see Figure 11, remove the UV film that chip back is coating.
Described disk front circuit can carry out Fanout design according to lead frame drawing; Described lead frame drawing can carry out matched design according to disk front circuit.

Claims (3)

1. a wafer-level package structure, it is characterized in that: it comprises lead frame (1), the upper upside-down mounting of described lead frame (1) has chip (2), described chip (2) front is provided with metal salient point (3), be connected by tin ball (4) between described metal salient point (3) with lead frame (1), described lead frame (1), metal salient point (3) and tin ball (4) are encapsulated with plastic packaging material (5) around, and described leadframe (1) back side is electroplate with metal level (6).
2. a process for wafer-level package structure, is characterized in that said method comprising the steps of:
Step one, get a disk, disk front line design corresponds to lead frame drawing completely, and single chips size is equal to package dimension;
Step 2, on disk front electrode, make metal salient point;
Step 3, on metal salient point, make tin ball;
Step 4, by disk by the tin ball upside-down mounting on metal salient point in lead frame, lead frame single product size is equal to single chips size;
Step 5, the disk and lead frame that complete upside-down mounting are put into solder reflow device carry out Reflow Soldering;
Step 6, the product completing Reflow Soldering to be encapsulated;
Step 7, the plating of the lead frame back side is carried out to the product completing encapsulating;
Step 8, UV film is coated to the chip back completing electroplated product;
Step 9, the product completing plating to be cut, be separated single product;
The UV film that step 10, removal chip back are coating.
3. the process of a kind of wafer-level package structure according to claim 2, is characterized in that: described disk front circuit carries out Fanout design according to lead frame drawing or lead frame drawing carries out matched design according to disk front circuit.
CN201410827464.XA 2014-12-26 2014-12-26 Wafer level package structure and technological method thereof Pending CN104538378A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201410827464.XA CN104538378A (en) 2014-12-26 2014-12-26 Wafer level package structure and technological method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201410827464.XA CN104538378A (en) 2014-12-26 2014-12-26 Wafer level package structure and technological method thereof

Publications (1)

Publication Number Publication Date
CN104538378A true CN104538378A (en) 2015-04-22

Family

ID=52853881

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410827464.XA Pending CN104538378A (en) 2014-12-26 2014-12-26 Wafer level package structure and technological method thereof

Country Status (1)

Country Link
CN (1) CN104538378A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104850692A (en) * 2015-05-07 2015-08-19 中国科学院自动化研究所 Intelligent wiring system design method used for chip design
CN107393840A (en) * 2017-06-15 2017-11-24 江苏长电科技股份有限公司 A kind of cutting method of ceramic substrate encapsulation

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050133896A1 (en) * 2003-12-19 2005-06-23 Advanced Semiconductor Engineering, Inc. Semiconductor package with a flip chip on a solder-resist leadframe
KR100891649B1 (en) * 2002-08-08 2009-04-02 삼성테크윈 주식회사 Method of manufacturing semiconductor package
CN101563756A (en) * 2005-06-09 2009-10-21 万国半导体股份有限公司 Wafer level bumpless method of making a flip chip mounted semiconductor device package
CN102222658A (en) * 2011-06-30 2011-10-19 天水华天科技股份有限公司 Multi-circle arranged IC (integrated circuit) chip packaging member and producing method thereof
CN102760664A (en) * 2011-04-29 2012-10-31 英飞凌科技股份有限公司 Semiconductor device and method of making a semiconductor device
CN103531562A (en) * 2012-07-04 2014-01-22 颀邦科技股份有限公司 Semiconductor packaging structure and lead frame thereof
CN103730429A (en) * 2013-12-05 2014-04-16 南通富士通微电子股份有限公司 Packaging structure
CN103730440A (en) * 2013-12-05 2014-04-16 南通富士通微电子股份有限公司 Packaging structure
CN204375730U (en) * 2014-12-26 2015-06-03 江苏长电科技股份有限公司 A kind of wafer-level package structure

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100891649B1 (en) * 2002-08-08 2009-04-02 삼성테크윈 주식회사 Method of manufacturing semiconductor package
US20050133896A1 (en) * 2003-12-19 2005-06-23 Advanced Semiconductor Engineering, Inc. Semiconductor package with a flip chip on a solder-resist leadframe
CN101563756A (en) * 2005-06-09 2009-10-21 万国半导体股份有限公司 Wafer level bumpless method of making a flip chip mounted semiconductor device package
CN102760664A (en) * 2011-04-29 2012-10-31 英飞凌科技股份有限公司 Semiconductor device and method of making a semiconductor device
CN102222658A (en) * 2011-06-30 2011-10-19 天水华天科技股份有限公司 Multi-circle arranged IC (integrated circuit) chip packaging member and producing method thereof
CN103531562A (en) * 2012-07-04 2014-01-22 颀邦科技股份有限公司 Semiconductor packaging structure and lead frame thereof
CN103730429A (en) * 2013-12-05 2014-04-16 南通富士通微电子股份有限公司 Packaging structure
CN103730440A (en) * 2013-12-05 2014-04-16 南通富士通微电子股份有限公司 Packaging structure
CN204375730U (en) * 2014-12-26 2015-06-03 江苏长电科技股份有限公司 A kind of wafer-level package structure

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104850692A (en) * 2015-05-07 2015-08-19 中国科学院自动化研究所 Intelligent wiring system design method used for chip design
CN104850692B (en) * 2015-05-07 2017-12-01 中国科学院自动化研究所 A kind of intelligent wiring design method for chip design
CN107393840A (en) * 2017-06-15 2017-11-24 江苏长电科技股份有限公司 A kind of cutting method of ceramic substrate encapsulation

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Application publication date: 20150422