CN104269361B - Method for packaging semiconductor chip - Google Patents
Method for packaging semiconductor chip Download PDFInfo
- Publication number
- CN104269361B CN104269361B CN201410530456.9A CN201410530456A CN104269361B CN 104269361 B CN104269361 B CN 104269361B CN 201410530456 A CN201410530456 A CN 201410530456A CN 104269361 B CN104269361 B CN 104269361B
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- pptc
- diode
- semiconductor die
- die package
- package method
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- Engineering & Computer Science (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
Abstract
The invention discloses a method for packaging a semiconductor chip. The method comprises the steps that a PPTC substrate is provided and comprises an upper surface and a lower surface opposite to the upper surface; a diode is provided and is provided with a first electrode surface and a second electrode surface opposite to the first electrode surface; the diode is electrically connected with the PPTC substrate; a mold is provided, glass fiber cloth is placed in the mold, and the diode and the PPTC substrate which are connected electrically are placed in the mold; liquid packaging materials are injected into the mold and are baked to be cured. Compared with the prior art, the glass fiber cloth is added into the mold in advance, the packaging structure with glass fibers is obtained after curing, the strength of the packaging materials is obviously improved, and surface protruding, cracking and other abnormal conditions generated by packaging under the circumstance of high and low temperature sudden changes can be avoided well.
Description
Technical field
The invention belongs to field of semiconductor manufacture, more particularly to a kind of semiconductor die package method.
Background technology
Traditional semiconductor die package mode will be at normal temperatures the encapsulating material of solid-state generally by HTHP
Thawing injection mould is simultaneously again fast curing-formed（5 ~ 50 seconds）Packaging process.This kind of packaged type is in process
In, packed product needed bears higher temperature and pressure, and if necessary to the product of encapsulation itself HTHP can not be born,
This kind of solid-state material packaged type cannot be used.Using the epoxy encapsulant under normal temperature for liquid, low pressure injects mould, and
The shortcoming of packed material non-refractory high pressure itself can be solved using baking-curing, but the epoxy encapsulant of liquid
Glass transition temperature（Tg）Relatively low, the low intensity of epoxy encapsulant, is easily mutated by high/low temperature after solidification（Such as Reflow Soldering
Connect, high/low-temperature impact etc.）Affect, the unusual conditions such as protrusion of surface, cracking occur, affect encapsulation quality.
The content of the invention
It is an object of the invention to provide a kind of semiconductor die package method for solving above-mentioned technical problem.
Wherein, the semiconductor die package method of an embodiment of the present invention, including：
A PPTC substrates are provided, it includes upper surface and the lower surface opposite with upper surface；
A diode is provided, it has first electrode surface and the second electrode table opposite with the first electrode surface
Face；
The diode is connected with the PPTC electrical property of substrate；
One mould is provided, glass fabric is put in the mold, then by two pole being electrically connected
Pipe and the PPTC substrates are put into the mould；
Liquid encapsulating material is injected in mould, baking solidifies the liquid encapsulating material.
As a further improvement on the present invention, before " being connected the diode with the PPTC electrical property of substrate " step also
Including：
Form the first insulating barrier and the second insulating barrier respectively on the upper surface of the PPTC substrates and lower surface, and in institute
State and form through hole on the first insulating barrier,
Conducting medium is formed on the through-hole wall.
As a further improvement on the present invention, described " being connected the diode with the PPTC electrical property of substrate " step tool
Body includes：
An electrical connector is provided, the first electrode surface of the diode is by the through hole and the PPTC electrical property of substrate
Connection, the second electrode surface of the diode is connected by the electrical connector and the through hole with the PPTC electrical property of substrate
Connect.
As a further improvement on the present invention, each electrode surface of the diode is by surface-pasted mode
（SMT）It is electrically connected with corresponding conductor.
As a further improvement on the present invention, under normal atmospheric pressure, baking temperature is up to 150 DEG C.
As a further improvement on the present invention, the PPTC substrates are composited by the PCT plates of multiple individual layers.
As a further improvement on the present invention, the liquid encapsulating material is liquid-state epoxy resin.
As a further improvement on the present invention, the conductive dielectric materials on the through-hole wall are copper.
As a further improvement on the present invention, the electrical connector is metal clip or wire.
As a further improvement on the present invention, the liquid-state epoxy resin has low glass state inversion temperature（Tg）.
Compared with prior art, by adding glass fabric in a mold in advance, then resolidification, obtains the present invention
Encapsulating structure with glass fibre, considerably improves the intensity of encapsulating material epoxy resin, can be good at solving encapsulation
The unusual conditions such as the protrusion of surface occurred in the case where high/low temperature is mutated, cracking.
Description of the drawings
Fig. 1 is the side structure schematic view of encapsulating structure in the embodiment of encapsulating structure of the present invention；
The step of Fig. 2 is method for packing in the embodiment of an encapsulating structure of the present invention flow chart.
Specific embodiment
Describe the present invention below with reference to specific embodiment shown in the drawings.But these embodiments are simultaneously
The present invention is not limited, structure that one of ordinary skill in the art is made according to these embodiments, method or functionally
Conversion is all contained in protection scope of the present invention.
As shown in figure 1, in an embodiment of the present invention, semiconductor chip package includes PPTC substrates 10, should
PPTC substrates 10 include upper surface and the lower surface opposite with the upper surface.The PPTC substrates 10 are answered by the PCT plates of multiple individual layers
Conjunction is formed.The first insulating barrier 11 is coated with the upper surface of the PPTC substrates 10, is coated with the lower surface of the PPTC substrates 10
Second insulating barrier 12.
Diode 20, with first electrode surface 21 and the second electrode surface opposite with the first electrode surface 21
22, diode 20 adopts surface mount（SMT）Mode be placed on the first insulating barrier 11 of PPTC substrates 10.
In order to realize the first electrode surface 21 of diode 20 and the electric connection of PPTC substrates 10, in the first insulating barrier 11
The position of upper correspondence diode 20 is provided with least one through hole 111, and the through hole 111 is faced down table by the upper table of the first insulating barrier 11
Face extends, and penetrates.Further, the inwall of through hole 111 is provided with conducting medium（Not shown in figure）, it is preferable that conduction is situated between
The material of matter is copper, and the conducting medium on inwall that the insulating barrier 11 of diode 20 and first passes through through hole 111 is realized and PPTC bases
The electric connection of plate 10.Preferably, in the present embodiment, the quantity of through hole 111 is multiple, and is not corresponding to the position of diode 20
Put and also be provided with least one identical through hole 112, opening shape of the through hole in the upper surface of the first insulating barrier 11 can be circle,
Can be square, the angle between the through-hole wall and PPTC substrates 10 can be acute angle, right angle or obtuse angle.
Electrical connector 30, preferred metal clip or wire, its one end is fitted with the second electrode surface 22 of diode 20, separately
One end is directly electrically connected with the conducting medium on the inwall of through hole 112 of the insulating barrier 11 of PPTC substrates 10 first, so realizing two
The second electrode surface 22 of pole pipe 20 and the electric connection of PPTC substrates 10.
The encapsulating structure also includes encapsulating material 40, and the encapsulating material 40 covers the on the upper surface of PPTC substrates 10
One insulating barrier 11, diode 20 and electrical connector 30.Because PPTC substrates 10 can not bear HTHP, therefore, encapsulating material 40
Mould can need to be under low pressure injected from the epoxy resin under normal temperature for liquid, this material, baking temperature is up to 150
DEG C, such encapsulation condition will not bring impact to PPTC substrates 10.Further, since the epoxy resin of liquid has low glass state
Conversion temperature（Tg）, therefore its package strength after hardening is not very high, is easily mutated by high/low temperature（Such as reflow soldering, height
Low-temperature impact etc.）Affect, the unusual conditions such as protrusion of surface, cracking occur.In order to solve the above problems, introduce in the present invention
Glass fabric 50, with the wrapping and encapsulating material 40 of glass fabric 50 and the second insulating barrier of the lower surface of the PPTC substrates 10
12, the unusual conditions such as encapsulating structure protrusion of surface, cracking can be avoided the occurrence of.
Shown in ginseng Fig. 2, flow chart the step of be method for packing in the embodiment of encapsulating structure of the present invention, it includes：
S1, one PPTC substrates of offer, it includes upper surface and the lower surface opposite with upper surface.The PPTC substrates 10 are by more
The PCT plates of individual individual layer are composited.The first insulating barrier 11 is formed in the upper surface of the PPTC substrates 10, in the PPTC substrates 10
Lower surface forms the second insulating barrier 12.
S2, one diode of offer, it has first electrode surface and the second electrode opposite with the first electrode surface
Surface.The position of correspondence diode 20 is provided with least one through hole 111 on the first insulating barrier 11, and the through hole 111 is exhausted by first
The upper table of edge layer 11 faces down surface extension, and penetrates.Further, the inwall of through hole 111 is provided with conducting medium（In figure not
Illustrate）, it is preferable that in the present embodiment, the quantity of through hole 111 is multiple, and also is provided with the position for not corresponding to diode 20
At least one identical through hole 112, opening shape of the through hole in the upper surface of the first insulating barrier 11 can be circle, alternatively square
Shape, the angle between the through-hole wall and PPTC substrates 10 can be acute angle, right angle or obtuse angle.
S3, the diode is connected with the PPTC electrical property of substrate.The insulating barrier 11 of diode 20 and first passes through through hole
Conducting medium on 111 inwall realizes the electric connection with PPTC substrates 10, there is provided an electrical connector 30, preferred metal clip or
Wire, its one end is fitted with the second electrode surface 22 of diode 20, and the other end is directly electrically connected with PPTC substrates 10 first
Conducting medium on the inwall of through hole 112 of insulating barrier 11, so realizing the second electrode surface 22 of diode 20 and PPTC bases
The electric connection of plate 10.Diode 20 each electrode surface is by surface-pasted mode（SMT）With corresponding conductor shape
Into what is be electrically connected with.
S4, a mould is provided, be put into glass fabric in the mold, then by be electrically connected described two
Pole pipe and the PPTC substrates are put into the mould.Hardness after in order to increase encapsulating material solidification, in encapsulating material mould is injected
Before tool, a glass fabric is put in a mold, glass fabric has good profit to encapsulating material liquid-state epoxy resin
It is moist, so not interfering with it in liquid-state epoxy resin injection mold process is full of whole cavity body of mould.
S5, liquid encapsulating material is injected in mould, baking solidifies the liquid encapsulating material.Liquid-state epoxy resin exists
Mould is injected under low pressure, low pressure here refers to the normal atmospheric pressure in daily life, baking-curing temperature is up to
150 DEG C, the liquid-state epoxy resin after solidification and glass fabric have it is good combine closely, can bear as reflow soldering,
The various mal-conditions such as high/low-temperature impact and there is no protrusion of surface, ftracture hierarchical phenomenon, and because glass fibre has
The characteristic of high-tensile strength so that the intensity of whole encapsulating structure is improved, using this kind of new method for packing, can cause whole
Encapsulating structure reaches the effects such as insulation, high temperature resistant, shock resistance, damping, protection against the tide, waterproof and dustproof and resistance to chemical attack.
It should be understood that, although this specification is been described by according to embodiment, but not each embodiment only includes one
Individual independent technical scheme, this narrating mode of specification is only that for clarity those skilled in the art will should say
Bright book as an entirety, the technical scheme in each embodiment can also Jing it is appropriately combined, forming those skilled in the art can
With the other embodiment for understanding.
The a series of detailed description of those listed above is only for the feasibility embodiment of the present invention specifically
Bright, they simultaneously are not used to limit the scope of the invention, all equivalent implementations made without departing from skill spirit of the present invention
Or change should be included within the scope of the present invention.
Claims (10)
1. a kind of semiconductor die package method, it is characterised in that methods described includes：
A PPTC substrates are provided, it includes upper surface and the lower surface opposite with upper surface；
A diode is provided, it has first electrode surface and the second electrode surface opposite with the first electrode surface；
The diode is connected with the PPTC electrical property of substrate；
One mould is provided, glass fabric is put in the mold, then by the diode being electrically connected and
The PPTC substrates are put into the mould；
Liquid encapsulating material is injected in mould, baking solidifies the liquid encapsulating material.
2. semiconductor die package method according to claim 1, it is characterised in that " by the diode with it is described
Also include before PPTC electrical property of substrate connection " step：
Form the first insulating barrier and the second insulating barrier respectively on the upper surface of the PPTC substrates and lower surface, and described
Through hole is formed on one insulating barrier,
Conducting medium is formed on the through-hole wall.
3. semiconductor die package method according to claim 2, it is characterised in that described " by the diode and institute
State the connection of PPTC electrical property of substrate " step specifically includes：
An electrical connector is provided, the first electrode surface of the diode is connected by the through hole with the PPTC electrical property of substrate
Connect, the second electrode surface of the diode is connected by the electrical connector and the through hole with the PPTC electrical property of substrate.
4. semiconductor die package method according to claim 3, it is characterised in that the diode each electrode surface
It is by surface-pasted mode（SMT）It is electrically connected with corresponding conductor.
5. semiconductor die package method according to claim 1, it is characterised in that under normal atmospheric pressure, baking
Temperature is up to 150 DEG C.
6. semiconductor die package method according to claim 1, it is characterised in that the PPTC substrates are by multiple individual layers
PCT plates be composited.
7. semiconductor die package method according to claim 1, it is characterised in that the liquid encapsulating material is liquid
Epoxy resin.
8. semiconductor die package method according to claim 2, it is characterised in that conductive Jie on the through-hole wall
Material is copper.
9. semiconductor die package method according to claim 3, it is characterised in that the electrical connector be metal clip or
Wire.
10. semiconductor die package method according to claim 7, it is characterised in that the liquid-state epoxy resin has
Low glass state inversion temperature（Tg）.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410530456.9A CN104269361B (en) | 2014-10-10 | 2014-10-10 | Method for packaging semiconductor chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410530456.9A CN104269361B (en) | 2014-10-10 | 2014-10-10 | Method for packaging semiconductor chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104269361A CN104269361A (en) | 2015-01-07 |
| CN104269361B true CN104269361B (en) | 2017-04-19 |
Family
ID=52160872
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410530456.9A Active CN104269361B (en) | 2014-10-10 | 2014-10-10 | Method for packaging semiconductor chip |
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| Country | Link |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1152190A (en) * | 1995-08-02 | 1997-06-18 | 国际商业机器公司 | Systems interconneted by bumps of joining material |
| CN1219767A (en) * | 1997-12-08 | 1999-06-16 | 东芝株式会社 | Package for semiconductor power device and method for assembling the same |
| CN101728368A (en) * | 2008-10-30 | 2010-06-09 | 育霈科技股份有限公司 | Semiconductor assembly packaging structure with a plurality of grains and packaging method thereof |
| CN102142417A (en) * | 2009-11-13 | 2011-08-03 | 卡西欧计算机株式会社 | Semiconductor device including semiconductor construct installed on base plate, and manufacturing method of the same |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04165636A (en) * | 1990-10-30 | 1992-06-11 | Nec Corp | Forming method for electrode of semiconductor device |
| JP2000260823A (en) * | 1999-03-12 | 2000-09-22 | Sumitomo Bakelite Co Ltd | Flexible printed wiring board for mounting semiconductor device |
| US6906425B2 (en) * | 2002-03-05 | 2005-06-14 | Resolution Performance Products Llc | Attachment of surface mount devices to printed circuit boards using a thermoplastic adhesive |
| JP2009289863A (en) * | 2008-05-28 | 2009-12-10 | Casio Comput Co Ltd | Method of manufacturing semiconductor device |
-
2014
- 2014-10-10 CN CN201410530456.9A patent/CN104269361B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1152190A (en) * | 1995-08-02 | 1997-06-18 | 国际商业机器公司 | Systems interconneted by bumps of joining material |
| CN1219767A (en) * | 1997-12-08 | 1999-06-16 | 东芝株式会社 | Package for semiconductor power device and method for assembling the same |
| CN101728368A (en) * | 2008-10-30 | 2010-06-09 | 育霈科技股份有限公司 | Semiconductor assembly packaging structure with a plurality of grains and packaging method thereof |
| CN102142417A (en) * | 2009-11-13 | 2011-08-03 | 卡西欧计算机株式会社 | Semiconductor device including semiconductor construct installed on base plate, and manufacturing method of the same |
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| Publication number | Publication date |
|---|---|
| CN104269361A (en) | 2015-01-07 |
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