CN104135790B - A kind of LED adjusting control circuit - Google Patents

Abstract

The invention discloses a kind of LED adjusting control circuit, it utilizes counting and light adjusting controller to calculate the on-off times of ON/OFF switch, uses three section type light regulating；When first paragraph is 100% brightness, when the standard basis voltage-regulation Power metal-oxide-semiconductor using reference voltage selector to provide disconnects；When second segment is 50% brightness, chronotron is used to extend the duration that Power MOS disconnects；When being 25% brightness for the 3rd section, reduce reference voltage simultaneously and extend the duration of Power MOS disconnection to reach the purpose of degree of depth light modulation.Thereby the present invention is when the degree of depth dims, and capacity of resisting disturbance is greatly reinforced, and the most general ON/OFF switch can be utilized to carry out LED segment formula light modulation, highly versatile, uses extensively.

Description

A kind of LED adjusting control circuit

Technical field

The present invention relates to LED adjusting control circuit, particularly relate to one ON/OFF switch and carry out LED segment The control circuit of formula light modulation.

Background technology

Along with the development of LED illumination, LED light regulating technology also makes rapid progress.ON/OFF switch dimming technology It is ON/OFF number of record conventional wall switch, selects different LED to export electric current, realize light modulation 's.

Referring to the LED driver in the ON/OFF switch dimming technology shown in Fig. 1, the most all use Power MOS switch source electrode series resistor detects output electric current, output current value feeds back to controller internal and electric After pressure benchmark compares, realize LED current constant.

In tradition LED dimming driver, generally change internal voltage reference and regulate LED current, from And realize light modulation.This control mode has a disadvantage in that

When A. dimming less than 25%, internal reference drops to low voltage.Now reference voltage is easily by dry Disturb, and deviation is bigger.

When B. dimming, along with internal reference voltage declines, operating frequency can increase.The increase of operating frequency, EMI interference can be increased, increase the EMC cost of application scheme.

So research and development a kind of when dimming deeper anti-interference strong, working stability LED adjusting control circuit be industry Inside need badly and solve the technical problem that.

Summary of the invention

The present invention is to solve the problems referred to above of prior art, propose a kind of when dimming deeper anti-interference strong, Working stability LED adjusting control circuit.

For solving above-mentioned technical problem, the technical scheme that the present invention proposes is a kind of LED brightness adjustment control of design Circuit, has and connects the current input terminal of LED major loop, by the electric current of gallon resistance R1 ground connection Outfan, is sequentially connected in series the second metal-oxide-semiconductor and the first metal-oxide-semiconductor between electric current input/output terminal, connects city The power conversion module of electricity, power conversion module provides lasting DC source and opens at outside ON/OFF Closing and provide working power when connecting, the gate pole of the second metal-oxide-semiconductor connects described working power；It also includes: counting And light adjusting controller, connect described working power, in order to calculate the on-off times of ON/OFF switch, according to On-off times sends time delayed signal and adjusts reference voltage signal；Zero current detector, connects the 2nd MOS Pipe and the junction point of the first metal-oxide-semiconductor, in order to detect in the TOFF time (when the first and second MOS are not turned on) L1 electric current in major loop, sends zero current signal when L1 electric current is zero；Chronotron, its input divides Other connection count and light adjusting controller and zero current detector, its outlet side connect first with door (U202) An input, first is connected described zero current signal, at time delayed signal with another input of door During with zero current signal the most effectively, chronotron sends a delay pulse by first with door；Reference voltage Selector, its input connection standard reference voltage and low reference voltage respectively, its outfan is according to described Adjust reference voltage signal and select an outputting standard reference voltage or low reference voltage；First comparator, it is anti- Connect the outfan of described reference voltage selector to input, it is defeated that its positive input connects described electric current Go out end；Rest-set flip-flop, its S end connects described delay pulse, and its R end connects described first comparator Outfan, its outfan connects the gate pole of the first metal-oxide-semiconductor by the 4th not gate.

Described counting and light adjusting controller have the second comparator, first to 3d flip-flop, Qi Zhong The in-phase input end of two comparators connects the first resistance and one end of the second resistance, another termination of the first resistance Described working power, the other end ground connection of the second resistance, the reverse input end of the second comparator connects the second ratio Relatively level, the clock end of the output termination first of the second comparator to 3d flip-flop, a D triggers The D of device terminates described working power, and the Q of the first d type flip flop terminates the D end of the second d type flip flop, the The Q of 2-D trigger terminates the D end of 3d flip-flop, and the non-end of Q of the first d type flip flop passes through first Not gate exports described time delayed signal, and the non-end of Q of the second d type flip flop exports described adjustment by the second not gate Reference voltage signal, the reset terminal of the Q non-terminated first of 3d flip-flop to 3d flip-flop.

Described zero current detector has the 3rd comparator, and its reverse input end connects the 3rd resistance and the 4th electricity One end of resistance, it inputs termination the 5th resistance and one end of the 6th resistance in the same direction, its output termination second with One input of door, second exports described zero current signal with the outfan of door, another of the 3rd resistance Terminating described second metal-oxide-semiconductor and the junction point of the first metal-oxide-semiconductor, another of the 5th resistance terminates described work Power supply, the 4th resistance and the other end ground connection of the 6th resistance, second is described with another input termination of door The outfan of rest-set flip-flop.

Charging current source that described chronotron includes being sequentially connected in series between described DC source and ground, first Electrical switch, the second electrical switch, discharge current source, wherein the control end of the first and second electrical switches Connecing the outfan of the first NAND gate, two inputs of the first NAND gate connect described time delayed signal and zero respectively Current signal, the junction point of the first and second electrical switches connects one end of the first electric capacity and the 3rd comparator Reverse input end, the other end ground connection of the first electric capacity, the in-phase input end of the 3rd comparator connects first and compares Level (V1), the input of output termination second NAND gate of the 3rd comparator, another of the second NAND gate Input terminates described time delayed signal, and the outfan of the second NAND gate exports described delay pulse.

Described reference voltage selector includes the 3rd electrical switch and the 4th electrical switch, described adjustment benchmark Voltage signal connects controlling end and being connect the control of the 3rd electrical switch by the first not gate of the 4th electrical switch End, the input of the 3rd electrical switch terminates described standard basis voltage, the input termination of the 4th electrical switch Described low reference voltage, the outfan of the third and fourth electrical switch also exports described standard basis electricity after connecing Pressure or low reference voltage.

The half of the magnitude of voltage that magnitude of voltage is standard basis voltage of described low reference voltage.

Compared with prior art, the present invention when the degree of depth dims (less than the 25% of rated power) time, both adjusted Joint internal reference voltage regulates again the turn-off time of Power MOS switch, so internal reference voltage will not Dropping to the least value, operating frequency also will not increase to the biggest value.Thus driver capacity of resisting disturbance is provided, And save the EMC cost of application scheme.And the present invention can utilize the most general ON/OFF to open Close (switch panel of metope) and carry out LED segment formula light modulation, highly versatile, use extensively.

Accompanying drawing explanation

Fig. 1 is conventional LED driver current detection circuit schematic diagram；

Fig. 2 is principle of the invention block diagram；

Work wave when Fig. 3 is first paragraph brightness；

Work wave when Fig. 4 is second segment brightness；

Work wave when Fig. 5 is the 3rd section of brightness；

Fig. 6 is the circuit diagram of chronotron in present pre-ferred embodiments；

Fig. 7 is the sequential chart of chronotron；

Fig. 8 is the circuit diagram of zero current detector in present pre-ferred embodiments；

Fig. 9 is counting and the circuit diagram of light adjusting controller in present pre-ferred embodiments；

Figure 10 is the circuit diagram of reference voltage selector in present pre-ferred embodiments.

Detailed description of the invention

In order to make the purpose of the present invention, technical scheme and advantage clearer, below in conjunction with accompanying drawing and Embodiment, is described in further detail the present invention.Should be appreciated that specific embodiment described herein It is used only for explaining the present invention, is not intended to limit the present invention.

In LED light adjusting circuit, have power conversion module, civil power be transformed into direct current, by Fig. 1 or Positive pole (LED+) and negative pole (LED-) in Fig. 2 connect LED, afterflow two of connecting between both positive and negative polarity Pole pipe (D1) and the first inductance (L1), series connected dimmer control circuit between junction point and the ground of D1 and L1. It can also be integrated chip that described adjusting control circuit can be made up of discrete component.Preferable in the present invention Adjusting control circuit is made integrated chip by embodiment.

The LED adjusting control circuit disclosed referring to Fig. 2 present invention, it has the electricity connecting LED major loop Stream input DRN, current output terminal CS by gallon resistance R1 ground connection, in electric current input and output It is sequentially connected in series the second metal-oxide-semiconductor (also referred to as Power MOS) Q2 and the first metal-oxide-semiconductor Q1 between end, connects city The power conversion module (not drawing in figure) of electricity, power conversion module provide lasting DC source VDD, And provide working power VIN (when ON/OFF switchs access failure, to work when outside ON/OFF switch connection Power supply is without electricity), the gate pole of the second metal-oxide-semiconductor connects described working power, and it also includes: counting and brightness adjustment control Device, connects described working power, in order to calculate the on-off times of ON/OFF switch, sends out according to on-off times Go out time delayed signal (CTR_TOFF) and adjust reference voltage signal (CTR_REF)；Zero current detector, Connect the junction point (FB) of the second metal-oxide-semiconductor and the first metal-oxide-semiconductor, in order to detect main circuit current size, Institute's probe current is to send zero current signal (ZCS) when zero；Chronotron, its input connection count respectively And light adjusting controller and zero current detector, its outlet side connect an input of first and door U202, First is connected described zero current signal with another input of door, same at time delayed signal and zero current signal During Shi Youxiao, chronotron sends a delay pulse by first with door；Reference voltage selector, its input End connection standard reference voltage and low reference voltage respectively, its outfan is believed according to described adjustment reference voltage Number select an outputting standard reference voltage or low reference voltage；First comparator U201, its reverse input end is even Connecing the outfan of described reference voltage selector, its positive input connects described current output terminal；RS touches Sending out device U203, its S end connects described delay pulse, and its R end connects the outfan of described first comparator, Its outfan connects the gate pole of the first metal-oxide-semiconductor by the 4th not gate U204.

This patent uses source pole driving mode, can realize syllogic ON/OFF switching buck brightness adjustment control, First paragraph is 100% brightness in the preferred embodiment, and second segment is 50% brightness, and the 3rd section is 25% brightness.

Working waveform figure when Fig. 3 shows first paragraph brightness, when 100% brightness, LED driver works At critical current mode conduction mode, LED trigger internal reference voltage is VREF.As Power MOS During (Q1 and Q2) conducting (TON device), in Fig. 2, inductance L1 electric current starts to increase:

$I_{L1}\left(t\right)=\underset{0}{\overset{T_{\mathrm{ON}}}{\∫}}\frac{V_{\mathrm{BUS}}-V_{\mathrm{LED}}}{L1}\mathrm{dt}$

Wherein VBUS is bus (DC-BUS) voltage.In the TON period, also flow through by the electric current of L1 R1.Along with the increase of L1 electric current, CS terminal voltage (R1*IR1) also increases, when VCS increases to VREF Time, Power MOS disconnects (i.e. TON terminates), and now inductive current is:

$I_{L1\_\mathrm{PEAK}}=\frac{V_{\mathrm{BUS}}-V_{\mathrm{LED}}}{L1}*T_{\mathrm{ON}}=\frac{\mathrm{VREF}}{R1}$

Owing to inductive current can not suddenly change, this electric current will flow through sustained diode 1, and reflux bus, until Electric current is reduced to zero.The zero current detector of LED driver detects inductive current to after zero, again makes Power MOS turns on, and i.e. starts next switch periods, as shown in Figure 3.Owing to LED driver works In electric current critical conduction mode, the average current of LED is the half of L1 peak point current:

$I_{\mathrm{LED}1}=\frac{1}{2}*I_{L1\_\mathrm{PEAK}1}=\frac{1}{2}*\frac{V_{\mathrm{BUS}}-V_{\mathrm{LED}}}{L1}*T_{\mathrm{ON}}=\frac{1}{2}*\frac{\mathrm{VREF}}{R1}$

It is TFB that definition inductive current flows through flyback period of sustained diode 1, and now TOFF is TFB, Operating frequency is:

$f_{\mathrm{OP}1}=\frac{1}{T_{\mathrm{ON}1}+T_{\mathrm{OFF}1}}=\frac{1}{T_{\mathrm{ON}1}+T_{\mathrm{FB}1}}$

After carrying out an ON/OFF operation, driver enters second segment luminance state.Internal reference voltage Keep VREF constant.But, TOFF control module can increase the TDEAD time so that TOFF total time increases Greatly, as shown in Figure 4, then:

T_OFF=T_DEAD+T_FB

Owing to busbar voltage, L1 inductance value and internal reference voltage do not change, TON time and first paragraph Time consistent, in the most each switch periods inductance, energy is as during first paragraph.Now, the average current of LED:

$I_{\mathrm{LED}2}=\frac{1}{2}*I_{L1\_\mathrm{PEAK}2}\frac{T_{\mathrm{ON}2}+T_{\mathrm{FB}2}}{T_{\mathrm{ON}2}+T_{\mathrm{OFF}2}}=I_{\mathrm{LED}1}*\frac{T_{\mathrm{ON}2}+T_{\mathrm{FB}2}}{T_{\mathrm{ON}2}+T_{\mathrm{OFF}2}}=I_{\mathrm{LED}1}*\frac{T_{\mathrm{ON}2}+T_{\mathrm{FB}2}}{T_{\mathrm{ON}2}+T_{\mathrm{FB}2}+T_{\mathrm{DEAD}2}}$

When TDEAD is equal to Power MOS ON time TON and TFB sum, the average current of LED is i.e. For ILED1 50%:

$I_{\mathrm{LED}2}=\frac{1}{2}*I_{\mathrm{LED}1}$

Second segment brightness is the 50% of nominal brightness.Operating frequency also drops to the one of former operating frequency fOP1 Half.

$f_{\mathrm{OP}2}=\frac{1}{T_{\mathrm{ON}2}+T_{\mathrm{FB}2}+T_{\mathrm{DEAD}2}}=\frac{1}{2*(T_{\mathrm{ON}1}+T_{\mathrm{FB}1})}=\frac{1}{2}*f_{\mathrm{OP}1}$

After ON/OFF operates again, driver enters the 3rd section of duty.Internal reference Control of Voltage It is (1/2) * VREF that device will adjust reference voltage.TDEAD is made to be Power MOS referring to Fig. 5 chronotron ON time TON and TFB sum.Half when dropping to first paragraph due to reference voltage, the peak of inductance L1 Value electric current IL1_PEAK also drop by half.Now, the average current of LED is:

$I_{\mathrm{LED}3}=\frac{1}{2}*I_{L1\_\mathrm{PEAK}3}*\frac{T_{\mathrm{ON}}+T_{\mathrm{FB}}}{T_{\mathrm{ON}}+T_{\mathrm{OFF}}}=\frac{1}{4}*I_{L1\_\mathrm{PEAK}1}*\frac{T_{\mathrm{ON}}+T_{\mathrm{FB}}}{T_{\mathrm{ON}}+T_{\mathrm{OFF}}}=\frac{1}{2}*I_{\mathrm{LED}1}*\frac{T_{\mathrm{ON}}+T_{\mathrm{FB}}}{T_{\mathrm{ON}}+T_{\mathrm{FB}}+T_{\mathrm{DEAD}}}$

Owing to TDEAD is Power MOS ON time TON and TFB sum, the average current of LED:

$I_{\mathrm{LED}3}=\frac{1}{2}*I_{\mathrm{LED}1}*\frac{T_{\mathrm{ON}}+T_{\mathrm{FB}}}{T_{\mathrm{ON}}+T_{\mathrm{FB}}+T_{\mathrm{DEAD}}}=\frac{1}{4}*I_{\mathrm{LED}1}$

Due to when reference voltage is first paragraph 1/2, then TON and TFB is reduced to original half, but TDEAD It it is just TON and TFB sum.Now operating frequency fOP3 will be consistent with first paragraph operating frequency.

$f_{\mathrm{OP}3}=\frac{1}{T_{\mathrm{ON}3}+T_{\mathrm{FB}3}+T_{\mathrm{DEAD}3}}=\frac{1}{2*(T_{\mathrm{ON}3}+T_{\mathrm{FB}3})}=\frac{1}{T_{\mathrm{ON}1}+T_{\mathrm{FB}1}}=f_{\mathrm{OP}1}$

This patent is in this three-stage dimming control circuit, during light modulation to rated power 25%: operating frequency changes Scope is little, only reduces to 50% when second segment；Internal reference change in voltage is the least, only drops to VREF Half.The shortcoming in tradition dimming mode can be effectively improved.

Referring in the preferred embodiment shown in Fig. 9 counting and the circuit diagram of light adjusting controller, described counting and Light adjusting controller have the second comparator U901, first to 3d flip-flop, wherein the second comparator In-phase input end connects the first resistance R901 and one end of the second resistance R902, another termination of the first resistance Described working power VIN, the other end ground connection of the second resistance, the reverse input end of the second comparator connects second Comparative level V2 (V2 can be obtained by VDD dividing potential drop), output termination first to the 3rd D of the second comparator The clock end of trigger, the D of the first d type flip flop U902 terminates described working power VDD, and a D touches The Q sending out device terminates the D end of the second d type flip flop U903, and Q termination the 3rd D of the second d type flip flop triggers The D end of device U904, the non-end of Q of the first d type flip flop exports described time delay by the first not gate U906 to be believed Number (CTR_TOFF), the non-end of Q of the second d type flip flop exports described adjustment base by the second not gate U905 Quasi-voltage signal (CTR_REF), Q non-terminated first the answering to 3d flip-flop of 3d flip-flop Position end.

When outside ON/OFF switch first switches on, working power VIN powers on, the second comparator U901 In-phase input end obtains a higher level, second comparator output terminal one high level of output.Now, Time delayed signal (CTR_TOFF) is low level, and chronotron is not triggered work；Reference voltage signal simultaneously (CTR_REF) it is low level, reference voltage selector outputting standard reference voltage, LED 100% brightness. When outside ON/OFF switch power-off for the first time, the power down of working power VIN, the second metal-oxide-semiconductor Q2 cut-off, LED is extinguished.

When outside ON/OFF switch second time is connected, working power VIN powers on, the second comparator U901 Again export high level so that time delayed signal (CTR_TOFF) is high level, chronotron triggering work, The time lengthening of the first metal-oxide-semiconductor Q1 cut-off；Make to adjust reference voltage signal (CTR_REF) simultaneously and be Low level, reference voltage selector outputting standard reference voltage, LED 50% brightness.As outside ON/OFF During switch second time power-off, LED is extinguished.

When outside ON/OFF switch third time is connected, working power VIN powers on, the second comparator U901 Again export high level so that time delayed signal (CTR_TOFF) is high level, chronotron triggering work, The time lengthening of the first metal-oxide-semiconductor Q1 cut-off；Make to adjust reference voltage signal (CTR_REF) simultaneously and be High level, reference voltage selector exports low reference voltage, LED 25% brightness.As outside ON/OFF During switch third time power-off, LED is extinguished.

Referring to the circuit diagram of zero current detector in the preferred embodiment shown in Fig. 8, it has the 3rd and compares Device U801, its reverse input end connects the 3rd resistance R803 and one end of the 4th resistance R804, and it is the most defeated Enter termination the 5th resistance R801 and one end of the 6th resistance R802, its output termination second and door (U802) An input, second exports described zero current signal ZCS with the outfan of door, another of the 3rd resistance Terminate described second metal-oxide-semiconductor Q2 and the junction point FB of the first metal-oxide-semiconductor Q1, another termination of the 5th resistance Described working power VIN, the 4th resistance and the other end ground connection of the 6th resistance, second is defeated with another of door Enter the outfan terminating described rest-set flip-flop.When in major loop, the electric current of L1 becomes zero, FB point voltage drops Low, U801 output high potential (i.e. ZCS high level), chronotron is triggered time delay.

Referring to the circuit diagram of chronotron in the preferred embodiment shown in Fig. 6, it includes being sequentially connected in series described Charging current source Isource between DC source VDD and ground, the first electrical switch S1, the second electronics Switch S2, discharge current source Isink, wherein the control termination first of the first and second electrical switches is with non- The outfan of door U601, two inputs of the first NAND gate connect described time delayed signal and zero current letter respectively Number, the junction point of the first and second electrical switches meets one end and the 3rd comparator U602 of the first electric capacity C1 Reverse input end, the other end ground connection of the first electric capacity, the in-phase input end of the 3rd comparator connects the first ratio Relatively level V1 (V1 can be obtained by VDD dividing potential drop), the output of the 3rd comparator terminates the second NAND gate U603 Input, the second NAND gate another input terminate described time delayed signal, the outfan of the second NAND gate Export described delay pulse.When Q1 turns on (TON), zero current signal (ZCS) is low level, the One electric capacity starts to charge up；Q1 close have no progeny, zero current detector detect L1 electric current to zero before (i.e. TFB), zero current signal (ZCS) is still low level, and the first electric capacity continues charging.Now, electric capacity powers on Pressure is more than V1 voltage, and comparator U602 is output as high level.When zero current detector detects L1 electric current To zero, zero current signal (ZCS) is when being high level, time delayed signal (CTR_TOFF) and zero current signal (ZCS) the most effectively (being all high level), NAND gate U601 output low level, control S1 Guan Bi, S2 disconnects, and the first electric capacity C1 starts electric discharge.Now the current potential of input in the same direction of comparator U602 is higher, U602 exports high level, and time delayed signal (CTR_TOFF) now is high level, through the second NAND gate U603 output low level, this signal level delivers to an input with door U202, and another of U202 is defeated Enter end and connect described zero current signal, the S end of the output termination rest-set flip-flop of U202, use Q1 to continue Turn off；U602 output low level after C1 current potential gradually decreases to V2 so that rest-set flip-flop overturns, Q1 turns on.I.e. TDEAD time discharge time of the first electric capacity C1.When Isink and Isource is equal, The TDEAD time is TON and TFB sum, as shown in Figure 7.

Referring to the circuit diagram of reference voltage selector in the preferred embodiment shown in Figure 10, it includes the 3rd electricity Son switch S3 and the 4th electrical switch S4, described adjustment reference voltage signal (CTR_REF) connects the 4th electricity What son switched is controlled end and is connect the control end of the 3rd electrical switch, the 3rd electronics by the first not gate U1001 The input of switch terminates described standard basis voltage (VREF), and the input termination of the 4th electrical switch is described low Reference voltage (1/2VREF), the outfan of the third and fourth electrical switch also exports described standard base after connecing Quasi-voltage or low reference voltage.So output mark when adjusting reference voltage signal (CTR_REF) low level Quasi-reference voltage, exports low reference voltage when adjusting reference voltage signal high level.

In the preferred embodiment, the magnitude of voltage that magnitude of voltage is standard basis voltage of described low reference voltage Half.

Above example by way of example only, non-provides constraints.Any without departing from the application spirit and model Farmland, and the equivalent modifications carrying out it or change, be intended to be limited solely by among claims hereof scope.

Claims (6)

1. a LED adjusting control circuit, have and connect the current input terminal of LED major loop, by the current output terminal of gallon resistance (R1) ground connection, the second metal-oxide-semiconductor (Q2) and the first metal-oxide-semiconductor (Q1) it is sequentially connected in series between electric current input/output terminal, connect the power conversion module of civil power, power conversion module provides lasting DC source (VDD) and provides working power (VIN) when outside ON/OFF switch connection, the gate pole of the second metal-oxide-semiconductor connects described working power, described major loop concatenates the first inductance (L1), it is characterised in that also include:

Counting and light adjusting controller, connect described working power, in order to calculate the on-off times of ON/OFF switch, sends time delayed signal according to on-off times and adjusts reference voltage signal；

Zero current detector, one input connects the second metal-oxide-semiconductor and the junction point of the first metal-oxide-semiconductor, and its another input connects the outfan of rest-set flip-flop (U203), in order to detect main circuit current size, sends zero current signal when institute's probe current is zero；

Chronotron, its input connection count respectively and light adjusting controller and zero current detector, its outlet side connect an input of first and door (U202), first is connected described zero current signal with another input of door, and when time delayed signal and zero current signal are the most effective, chronotron sends a delay pulse by first with door；

Reference voltage selector, its input connection standard reference voltage and low reference voltage respectively, its outfan selects an outputting standard reference voltage or low reference voltage according to described adjustment reference voltage signal；

First comparator (U201), its reverse input end connects the outfan of described reference voltage selector, and its positive input connects described current output terminal；

Rest-set flip-flop (U203), its S end connects described delay pulse, and its R end connects the outfan of described first comparator, and its outfan connects the gate pole of the first metal-oxide-semiconductor by the 4th not gate (U204).

null2. LED adjusting control circuit as claimed in claim 1，It is characterized in that: described counting and light adjusting controller have the second comparator (U901)、First to 3d flip-flop，Wherein the in-phase input end of the second comparator connects the first resistance (R901) and one end of the second resistance (R902)，Another of first resistance terminates described working power (VIN),The other end ground connection of the second resistance，The reverse input end of the second comparator connects the second comparative level (V2)，The output termination first of the second comparator is to the clock end of 3d flip-flop，The D of the first d type flip flop (U902) terminates described working power (VDD)，The Q of the first d type flip flop terminates the D end of the second d type flip flop (U903)，The Q of the second d type flip flop terminates the D end of 3d flip-flop (U904)，The non-end of Q of the first d type flip flop exports described time delayed signal by the first not gate (U906)，The non-end of Q of the second d type flip flop exports described adjustment reference voltage signal by the second not gate (U905)，The Q non-terminated first of 3d flip-flop is to the reset terminal of 3d flip-flop.

null3. LED adjusting control circuit as claimed in claim 2，It is characterized in that: described zero current detector has the 5th resistance (R801) and the 6th resistance (R802) being serially connected between described working power (VIN) and ground、It is serially connected in the 3rd resistance (R803) between described second metal-oxide-semiconductor (Q2) the first metal-oxide-semiconductor (Q1) junction point (FB) and ground and the 4th resistance (R804)，And the 3rd comparator (U801)，Its reverse input end connects the 3rd resistance (R803) and one end of the 4th resistance (R804)，It inputs termination the 5th resistance (R801) and one end of the 6th resistance (R802) in the same direction，Its output termination second and input for door (U802)，Second exports described zero current signal with the outfan of door，Another of 3rd resistance terminates described second metal-oxide-semiconductor (Q2) and the junction point of the first metal-oxide-semiconductor (Q1)，Another of 5th resistance terminates described working power (VIN)，4th resistance and the other end ground connection of the 6th resistance，Second with door another input terminate described rest-set flip-flop outfan.

null4. LED adjusting control circuit as claimed in claim 3，It is characterized in that: described chronotron includes the charging current source being sequentially connected in series between described DC source (VDD) and ground、First electrical switch (S1)、Second electrical switch (S2)、Discharge current source，Wherein the control of the first and second electrical switches terminates the outfan of the first NAND gate (U601)，Two inputs of the first NAND gate connect described time delayed signal and zero current signal respectively，The junction point of the first and second electrical switches connects one end and the reverse input end of the 3rd comparator (U602) of the first electric capacity (C1)，The other end ground connection of the first electric capacity，The in-phase input end of the 3rd comparator connects the first comparative level (V1)，The output of the 3rd comparator terminates the input of the second NAND gate (U603)，Another input of second NAND gate terminates described time delayed signal，The outfan of the second NAND gate exports described delay pulse.

5. LED adjusting control circuit as claimed in claim 4, it is characterized in that: described reference voltage selector includes the 3rd electrical switch (S3) and the 4th electrical switch (S4), described adjustment reference voltage signal is connect the control end of the 4th electrical switch and is connect the control end of the 3rd electrical switch by the first not gate (U1001), the input of the 3rd electrical switch terminates described standard basis voltage, the input of the 4th electrical switch terminates described low reference voltage, and the outfan of the third and fourth electrical switch also exports described standard basis voltage or low reference voltage after connecing.

6. LED adjusting control circuit as claimed in claim 5, it is characterised in that: the half of the magnitude of voltage that magnitude of voltage is standard basis voltage of described low reference voltage.