CN104062305B - A kind of analysis method of integrated circuit defect - Google Patents
A kind of analysis method of integrated circuit defect Download PDFInfo
- Publication number
- CN104062305B CN104062305B CN201410163560.9A CN201410163560A CN104062305B CN 104062305 B CN104062305 B CN 104062305B CN 201410163560 A CN201410163560 A CN 201410163560A CN 104062305 B CN104062305 B CN 104062305B
- Authority
- CN
- China
- Prior art keywords
- defect
- wafer
- signal
- integrated circuit
- analysis method
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Investigating Materials By The Use Of Optical Means Adapted For Particular Applications (AREA)
Abstract
The invention discloses a kind of analysis method of integrated circuit defect, wafer defect distribution file and wafer defect total score Butut are drawn by optical defect detection device, and defect preanalysis distribution map is generated to different types of defect characteristic signal sampling, and the quick analysis of true and false defect is carried out to defect preanalysis distribution map by electron microscope, then the morphology analysis quantity on this basis to all defect on wafer carries out specific aim selection, finally gives one and more conforms to actual defect kind distribution map.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly to a kind of analysis method of integrated circuit defect.
Background technology
In the prior art, the process that relatively advanced integrated circuit fabrication process typically all includes hundreds of steps, any link
Slight errors will all cause the failure of whole chip, in particular with the continuous diminution of circuit critical size, it is to technique control
The requirement of system is stricter, so highly sensitive for that can find and solve the problems, such as in time to be required for configure in actual production process
Spend optical defect detection device and on-line checking is carried out to product.
The basic functional principle of defects detection is to turn to the optical imagery conversion on chip to be represented by different bright dull gray ranks
Data image, Fig. 1 is that circuit optical imagery is transformed into and obtained under the schematic diagram of data gray scale image, i.e., one light microscope
Image be converted into the process of data image feature, then relatively detecting by the datagraphic feature in adjacent chips
There is abnormal defect position；The characteristic signal of equipment capture defect is a sufficiently complex algorithm, the table of each defect
Show and be not quite similar, bright dark, capture defect the passage of the position, the size of defect, defect where its specific defect on chip
Etc. it is closely related.
At present, when the defective locations obtained in process of production for inspection equipment carry out specific morphology analysis, use
Be to defects count total on wafer at random sampling observation 50~100 defects position, and be transferred under electron microscope carry out
The observation and analysis of specific pattern, finally give the distribution map of the defect kind in a wafer statistical significance, and Fig. 2 is to possess
The distribution map of the final defect kind of 1000 defects, but this method be relatively difficult to embody defect detection equipment according to defect not
The defect distribution obtained with characteristic signal, if the defect for having 60% on a wafer is generated by noise signal, then press
According to existing defect analysis method, the time for finally just having 60% when selecting 100 defects to be observed is made an uproar for analyzing
Message number, certainly will so cause the waste of resource and the increase of manufacturing cost.
Chinese patent (CN101996855B) discloses a kind of wafer defect analysis method, including：Complete special process step
After rapid, the wafer is detected, crystal grain thereon is divided into defect crystal grain and non-defective crystal grain, and by each defect crystal grain
Number of defects the defect crystal grain is classified, obtain the first testing result；After all techniques are fully completed, to above-mentioned wafer
Performance test is carried out, crystal grain thereon is divided into work crystal grain and inoperative crystal grain, the second testing result is obtained；According to described
One testing result and second testing result, subseries again is carried out to the crystal grain of the wafer；Calculate caused by every kind of defect
Defect leads to crash rate and yield loss, and wafer defect analysis method of the invention is accurately feasible, solves prior art defect
The inaccurate defect of analysis.
Although the patent refers to classifies to wafer defect, but is not directed to adopt the characteristic signal of various defects
Sample preanalysis, it is impossible to the problem of solving the above-mentioned wasting of resources.
Chinese patent (CN101738400B) discloses a kind of method for judging repeated defects on surface of wafer, including following step
Suddenly：(a) obtain the surface topography data of some crystal grain of crystal column surface to be measured, and grain morphology design data；(b) basis is treated
The design data of the grain morphology of wafer is surveyed, the division rule of sub- crystal grain is determined；(c) according to sub- crystal grain division rule, crystalline substance is utilized
Each crystal grain is divided into some sub- crystal grain by the surface topography data of grain；(d) using sub- crystal grain as basic detection unit, composition
At least one detection sequence；(e) in same detection sequence, each sub- crystal grain and at least two other sub- crystal grain are selected to carry out
Compare, to judge repeated defects.Present invention also offers a kind of device for judging repeated defects on surface of wafer.Advantages of the present invention
It is, the sub- crystal grain repeated using in each crystal grain is tested crystal column surface as basic test cell.Therefore originally
Invention can be tested the region where grain surface repeat unit, to find weight of the grain surface in above-mentioned zone
Multiple defect.
Although having carried out dividing planning to defect by the method for the patent, the feature letter to various defects is not directed to
Number carry out sampling preanalysis, it is impossible to the problem of solving the above-mentioned wasting of resources.
The content of the invention
The invention discloses a kind of analysis method of integrated circuit defect, show that wafer lacks by optical defect detection device
Distribution file and wafer defect total score Butut are fallen into, and defect preanalysis point is generated to different types of defect characteristic signal sampling
Butut, and the quick analysis by electron microscope to the true and false defect of defect preanalysis distribution map progress, then on this basis
Morphology analysis quantity to all defect on wafer carries out specific aim selection, finally gives one and more conforms to actual defect
Species distributing figure.
This invention describes a kind of analysis method of integrated circuit defect, wherein, methods described includes：
S1：One wafer for including some defects is provided；
S2：The wafer is detected by an optical defect detection device and the defect characteristic in each defect is identified
Signal obtains a wafer defect distribution file, so as to draw a wafer defect total distributed in the wafer defect distribution file
Figure；
S3：The optical defect detection device is classified by the defect characteristic signal to all defects, and
A number of prediction defect is chosen in every class defect, so as to draw a wafer defect preanalysis distribution map；
S4：The wafer defect total score Butut and the wafer defect preanalysis distribution map are transmitted to an Observation of Defects and set
In standby；
S5：It is true and false in defect that the Observation of Defects equipment show that every class is predicted according to the wafer defect preanalysis distribution map
The weight of signal；
S6：The Observation of Defects equipment is selected according to the weight of true and false signal in prediction defect in the wafer all defect
Some different classes of defects are taken to be observed, to obtain the distribution map of all defect complexion species；
Wherein, the weight of true signal is bigger in prediction defect, and the quantity that such defect is chosen is more.
The above method, wherein, it will identify that the defect in each defect is special by the wafer defect detection equipment
Reference number is written to the wafer defect distribution file.
The above method, wherein, the quantitative range that defect is predicted per class is 1~5.
The above method, wherein, it is bright that the defect characteristic signal includes defective locations signal, defect size signal, defect
Dark signal, capture defect channel signal.
The above method, wherein, the glitch is the noise signal of interference defect characteristic signal.
The above method, wherein, the true signal is defect characteristic signal.
The above method, wherein, in the S6, the quantity for choosing the defect of different defect characteristic signals accounts for all defects
The 10% of quantity.
The above method, wherein, in the S6, the defect of different defect characteristic signals is chosen in observation, first show that selection is different
The complexion classification distribution of the defect of defect characteristic signal, so as to be calculated in proportion according to quantity and draw all defect complexion species
Distribution map.
Above-mentioned technical proposal has the following advantages that or beneficial effect：
By carrying out the quick analysis of true and false defect to defect preanalysis distribution map, to the pattern of all defect on wafer
Analyze quantity and carry out specific aim selection, reduce the waste for randomly selecting the resource that rear defect analysis is brought and production cost
Increase.
Brief description of the drawings
With reference to appended accompanying drawing, more fully to describe embodiments of the invention.However, appended accompanying drawing be merely to illustrate and
Illustrate, and be not meant to limit the scope of the invention.
Fig. 1 is the schematic diagram that circuit optical imagery transforms into data gray scale image；
Fig. 2 is the distribution map for the final defect kind for possessing 1000 defects；
Fig. 3 is the inventive method flow chart；
Fig. 4 is overall defect distributed number figure on wafer of the present invention；
Fig. 5 is wafer defect preanalysis distribution map of the present invention；
Fig. 6 is that the present invention predicts the true and false signal weight subdivision Butut of defect per class；
Fig. 7 is the complexion Species distributing figure of all defect of the present invention.
Embodiment
The invention discloses a kind of analysis method of integrated circuit defect, Fig. 3 is the inventive method flow chart, such as Fig. 3 institutes
Show, S1：One wafer is provided, some defects are possessed on the wafer；S2：Pass through an optical defect detection device (not shown)
Detection wafer simultaneously identifies that the defect characteristic signal in each defect obtains a wafer defect distribution file, is examined by wafer defect
Measurement equipment will identify that the defect characteristic signal in each defect is written to wafer defect distribution file, and the defect characteristic signal is
A kind of algorithm, specifically, by the micro- sem observation wafer in optical defect detection device and the optical imagery on wafer is obtained,
Afterwards, it is the data image (shown in Fig. 1) represented as different bright dull gray ranks by the optical imagery conversion chemical conversion on wafer, then passes through
Adjacent defect characteristic signal relatively draws defect position on wafer, so that wafer defect distribution file is obtained, from
And a wafer defect total score Butut is drawn in wafer defect distribution file, as shown in Figure 4.
S3：Optical defect detection device is classified by defect characteristic signal to all defect, and in every class defect
A number of prediction defect is chosen, i.e., predicts that the quantity of defect can be with identical also difference per class, and form a wafer defect
Preanalysis distribution map；The classification for the defect characteristic signal that different wafer defect detection equipments can be recognized is different with quantity, excellent
Choosing, each defect is owned by defect characteristic signal in the present embodiment, and the defect characteristic signal includes defective locations signal, lacked
Fall into high low signal, the bright dark signal of defect, capture defect channel signal and noise signal, different wafer defect detection equipment institutes
The classification for the defect characteristic signal that can be recognized is different with quantity, it is preferred that optical defect detection device passes through defective locations signal
All defect is classified, the present embodiment is divided into optical channel 1, optical channel 2, logic area and memory block, Fig. 5 is of the invention brilliant
Discount vibram outlet falls into preanalysis distribution map, as shown in figure 5, the prediction defect that optical defect detection device is chosen in every class defect, per class
The quantitative range for predicting defect is 1~5, draws wafer defect preanalysis distribution map.
S4：Wafer defect total score Butut and wafer defect preanalysis distribution map are transmitted to an Observation of Defects equipment (in figure
Do not show)；S5：Observation of Defects equipment show that every class predicts the power of true and false signal in defect according to wafer defect preanalysis distribution map
Weight；Specifically, being carried out by Observation of Defects equipment to the prediction defect in optical channel 1, optical channel 2, logic area and memory block
The quick analysis of true and false signal, it is preferred that true signal is defect characteristic signal, glitch is the noise of interference defect characteristic signal
Signal, Fig. 6 is that the present invention predicts the true and false signal weight subdivision Butut of defect per class, as shown in fig. 6, showing that every class prediction defect is true
The weight of glitch, i.e., true and false signal ratio shared in every class predicts defect.
S6：Observation of Defects equipment according to prediction defect in true and false signal weight chosen in wafer all defect it is some not
Generic defect is observed, and the power of true signal in the defect of different defective locations signals, prediction defect is chosen in all defect
Again bigger, the quantity that such defect is chosen is more, it is preferred that the quantity for choosing the defect of different defect characteristic signals accounts for all lack
The 10% of quantity is fallen into, the complexion classification distribution for the defect for choosing different defect characteristic signals is first drawn, so that year-on-year according to quantity
Example calculates and draws the distribution map of all defect complexion species, specifically, being chosen in the present embodiment in all 1000 defects
The defect of 100 different defect characteristic signals, and observation analysis is carried out to 100 defects by Observation of Defects equipment, draw
Noise signal is 50, and bulky grain defect is 24, and little particle defect is 13, and disconnection defect is 7, and scratch defect is 6,
So as to calculate and draw the distribution map of all defect complexion species in proportion according to the quantity, Fig. 7 is all defect of the present invention
Complexion Species distributing figure.
To sum up, the present invention draws wafer defect distribution file and wafer defect total distributed by optical defect detection device
Figure, and defect preanalysis distribution map is generated to different types of defect characteristic signal sampling, and by electron microscope to defect
Preanalysis distribution map carries out the quick analysis of true and false defect, then morphology analysis on this basis to all defect on wafer
Quantity carries out specific aim selection, finally gives one and more conforms to actual defect kind distribution map
For a person skilled in the art, read after described above, various changes and modifications undoubtedly will be evident.
Therefore, appended claims should regard whole variations and modifications of the true intention and scope that cover the present invention as.In power
Any and all scope and content of equal value, are all considered as still belonging to the intent and scope of the invention in the range of sharp claim.
Claims (8)
1. a kind of analysis method of integrated circuit defect, it is characterised in that methods described includes：
S1：One wafer for including some defects is provided；
S2：The wafer is detected by an optical defect detection device and the defect characteristic signal in each defect is identified
A wafer defect distribution file is obtained, so as to draw a wafer defect total score Butut in the wafer defect distribution file；
S3：The optical defect detection device is classified by the defect characteristic signal to all defects, and every
A number of prediction defect is chosen in class defect, so as to draw a wafer defect preanalysis distribution map；
S4：The wafer defect total score Butut and the wafer defect preanalysis distribution map are transmitted to an Observation of Defects equipment
In；
S5：The Observation of Defects equipment show that every class predicts true and false signal in defect according to the wafer defect preanalysis distribution map
Weight；
S6：If the Observation of Defects equipment is chosen according to the weight of true and false signal in prediction defect in the wafer all defect
Do different classes of defect to be observed, to obtain the distribution map of all defect complexion species；
Wherein, the weight of true signal is bigger in prediction defect, and the quantity that such defect is chosen is more.
2. a kind of analysis method of integrated circuit defect as claimed in claim 1, it is characterised in that examined by the wafer defect
Measurement equipment will identify that the defect characteristic signal in each defect is written to the wafer defect distribution file.
3. a kind of analysis method of integrated circuit defect as claimed in claim 1, it is characterised in that the quantity of defect is predicted per class
Scope is 1~5.
4. a kind of analysis method of integrated circuit defect as claimed in claim 1, it is characterised in that in the defect characteristic signal
Including defective locations signal, defect size signal, the bright dark signal of defect, capture defect channel signal.
5. a kind of analysis method of integrated circuit defect as claimed in claim 1, it is characterised in that the glitch lacks for interference
Fall into the noise signal of characteristic signal.
6. a kind of analysis method of integrated circuit defect as claimed in claim 1, it is characterised in that the true signal is that defect is special
Reference number.
7. a kind of analysis method of integrated circuit defect as claimed in claim 1, it is characterised in that in the S6, chooses different
The quantity of the defect of defect characteristic signal accounts for the 10% of all defects counts.
8. a kind of analysis method of integrated circuit defect as claimed in claim 7, it is characterised in that in the S6, observation is chosen
The defect of different defect characteristic signals, first draws the complexion classification distribution for the defect for choosing different defect characteristic signals, so that root
Data bulk calculates and draws the distribution map of all defect complexion species in proportion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410163560.9A CN104062305B (en) | 2014-07-28 | 2014-07-28 | A kind of analysis method of integrated circuit defect |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410163560.9A CN104062305B (en) | 2014-07-28 | 2014-07-28 | A kind of analysis method of integrated circuit defect |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104062305A CN104062305A (en) | 2014-09-24 |
| CN104062305B true CN104062305B (en) | 2017-10-03 |
Family
ID=51550119
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410163560.9A Active CN104062305B (en) | 2014-07-28 | 2014-07-28 | A kind of analysis method of integrated circuit defect |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104062305B (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109493311B (en) * | 2017-09-08 | 2022-03-29 | 上海宝信软件股份有限公司 | Irregular defect picture pattern recognition and matching method and system |
| CN108269748A (en) * | 2018-01-23 | 2018-07-10 | 德淮半导体有限公司 | The detection method of wafer surface defects after a kind of CMP |
| CN109065468B (en) * | 2018-09-12 | 2020-12-04 | 上海华力微电子有限公司 | Defect filtering system, defect filtering method and computer storage medium |
| CN110969175B (en) * | 2018-09-29 | 2022-04-12 | 长鑫存储技术有限公司 | Wafer processing method and device, storage medium and electronic equipment |
| CN109712136B (en) * | 2018-12-29 | 2023-07-28 | 上海华力微电子有限公司 | Method and device for analyzing semiconductor wafer |
| WO2020176270A1 (en) | 2019-02-25 | 2020-09-03 | Applied Materials Israel Ltd. | System and method for detecting rare stochastic defects |
| CN113837983B (en) * | 2020-06-08 | 2023-09-15 | 长鑫存储技术有限公司 | Wafer defect analysis method, system, equipment and medium |
| CN113095438B (en) * | 2021-04-30 | 2024-03-15 | 上海众壹云计算科技有限公司 | Wafer defect classification method, device and system thereof, electronic equipment and storage medium |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3186174B2 (en) * | 1992-02-26 | 2001-07-11 | 株式会社日立製作所 | Pattern defect inspection method and apparatus |
| US7208328B2 (en) * | 2004-03-16 | 2007-04-24 | Macronix International Co., Ltd. | Method and system for analyzing defects of an integrated circuit wafer |
| JP2007003459A (en) * | 2005-06-27 | 2007-01-11 | Tokyo Seimitsu Co Ltd | Flaw inspection device of image, visual examination device and flaw inspection method of image |
| JP4776308B2 (en) * | 2005-09-05 | 2011-09-21 | 株式会社東京精密 | Image defect inspection apparatus, image defect inspection system, defect classification apparatus, and image defect inspection method |
| CN102610541A (en) * | 2012-04-20 | 2012-07-25 | 郑海鹏 | Location method for defect points of integrated circuit |
| CN102931116B (en) * | 2012-11-12 | 2015-05-06 | 上海华力微电子有限公司 | Synchronous defect detecting method for memorizer |
| CN103606529B (en) * | 2013-10-23 | 2016-08-24 | 上海华力微电子有限公司 | A kind of method and device promoting defect classification accuracy |
-
2014
- 2014-07-28 CN CN201410163560.9A patent/CN104062305B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN104062305A (en) | 2014-09-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104062305B (en) | A kind of analysis method of integrated circuit defect | |
| US7062081B2 (en) | Method and system for analyzing circuit pattern defects | |
| JP5460662B2 (en) | Region determination device, observation device or inspection device, region determination method, and observation method or inspection method using region determination method | |
| US6210983B1 (en) | Method for analyzing probe yield sensitivities to IC design | |
| JP4077951B2 (en) | Defect analysis method, recording medium, and process management method | |
| CN105702595B (en) | The yield judgment method of wafer and the changeable quantity measuring method of wafer conformity testing | |
| CN101996855B (en) | Wafer defect analysis method | |
| KR20130118822A (en) | Classifier readiness and maintenance in automatic defect classification | |
| WO2022028102A1 (en) | Testing method and testing system | |
| CN115032493A (en) | Wafer testing method and system based on tube core parameter display | |
| US20030208286A1 (en) | Method for analyzing manufacturing data | |
| JP2010231338A (en) | Apparatus and method for analyzing factor | |
| US6872582B2 (en) | Selective trim and wafer testing of integrated circuits | |
| CN102637617B (en) | Wafer quality detecting system and wafer quality detection method | |
| CN109309022A (en) | A kind of defect sampling observation method | |
| CN103606529B (en) | A kind of method and device promoting defect classification accuracy | |
| CN101738400B (en) | Method and device for judging repeated defects on surface of wafer | |
| US20090273669A1 (en) | Method and system for detecting critical defects | |
| US6539272B1 (en) | Electric device inspection method and electric device inspection system | |
| CN100375258C (en) | Method for detecting again fault | |
| CN109308395B (en) | Wafer-level space measurement parameter anomaly identification method based on LOF-KNN algorithm | |
| CN109884078A (en) | It is layered wafer inspection | |
| JP4866263B2 (en) | Electronic device quality control method and electronic device quality control system | |
| US7137085B1 (en) | Wafer level global bitmap characterization in integrated circuit technology development | |
| Liu et al. | Enhancing Good-Die-in-Bad-Neighborhood Methodology with Wafer-Level Defect Pattern Information |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |