CN103456852B - A kind of LED and preparation method - Google Patents
A kind of LED and preparation method Download PDFInfo
- Publication number
- CN103456852B CN103456852B CN201210171423.0A CN201210171423A CN103456852B CN 103456852 B CN103456852 B CN 103456852B CN 201210171423 A CN201210171423 A CN 201210171423A CN 103456852 B CN103456852 B CN 103456852B
- Authority
- CN
- China
- Prior art keywords
- layer
- substrate
- gan layer
- led
- inn
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Led Devices (AREA)
Abstract
The present invention provides a kind of LED, and including substrate, cushion, n-type GaN layer, luminescent layer and the p-type GaN layer that substrate sequentially forms, described cushion includes: be formed at the InN layer of substrate, and described InN layer is distributed the cavity exposing substrate；It is formed at the first intrinsic GaN layer on described InN layer；It is formed at the SiN on described first intrinsic GaN layerxLayer, described SiNxLayer is distributed the cavity exposing the first intrinsic GaN layer；And it is formed at described SiNxThe second intrinsic GaN layer on Ceng.This LED and preparation method thereof, can reduce the defect of epitaxial wafer, improves crystal mass.
Description
Technical field
The invention belongs to semiconductor applications, particularly relate to a kind of LED and preparation method.
Background technology
In recent years, due to the extensive application on the opto-electronic devices such as light emitting diode, the wide bandgap semiconductor GaN material in third generation semi-conducting material is extensively paid close attention to by people, and growing high-quality GaN base epitaxial wafer becomes the emphasis of people's research.
At present, be most widely used be use sapphire be backing material grow GaN base epitaxial wafer, GaN material can grow from 500 DEG C to 1100 DEG C on a sapphire substrate.Yet with differing greatly of sapphire and GaN lattice mismatch between the two and chemical property, grown epitaxial layer defect is more the most on a sapphire substrate, has a strong impact on crystal mass.For the GaN epitaxial layer obtaining smooth surface, crystal mass is higher, the method of growth GaN epitaxial layer mainly has two kinds: one, the two step epitaxial growth technologies of GaN, i.e. utilize AlN or the GaN cushion that MOCVD technology low-temperature epitaxy on a sapphire substrate is thin, then high growth temperature GaN epitaxial layer.Two, GaN laterally cover growth, the most in advance deposition mask layer on substrate, it is provided that the grain of crystallization needed for follow-up GaN epitaxy.
The two step epitaxial growth technologies of GaN, the method epitaxial layer Dislocations density is the highest, promotes crystal mass limited.GaN laterally covers growth, and the method can obtain higher GaN crystal quality, improve luminosity, but this method exists many deficiencies, such as: on substrate, substrate may be produced and pollute by deposition mask layer, adds technical process, relatively costly in addition.
Summary of the invention
The present invention solves the technical problem that LED epitaxial growth crystal is second-rate, it is provided that a kind of LED and preparation method thereof, the defect of LED can be reduced, significantly improve the crystal mass of LED.
The present invention provides a kind of LED, including substrate, cushion, n-type GaN layer, luminescent layer and the p-type GaN layer that substrate sequentially forms, and described cushion includes:
Being formed at the InN layer of substrate, described InN layer is distributed the cavity exposing substrate；
It is formed at the first intrinsic GaN layer on described InN layer；
It is formed at the SiN on described first intrinsic GaN layerxLayer, described SiNxLayer is distributed the cavity exposing the first intrinsic GaN layer；And
It is formed at described SiNxThe second intrinsic GaN layer on Ceng.
The present invention also provides for the preparation method of a kind of LED, comprises the following steps:
Substrate is provided；
There is the InN layer in the cavity exposing substrate at Grown；
The InN layer with cavity grows the first intrinsic GaN layer；
In the first intrinsic GaN layer, growth has the SiN in the cavity exposing the first intrinsic GaN layerxLayer；
At SiNxThe second intrinsic GaN layer is formed on layer；
Second intrinsic GaN layer is formed n-type GaN layer；
N-type GaN layer is formed luminescent layer；
Luminescent layer is formed p-type GaN layer.
The LED of present invention offer and preparation method, have the effect that
1, the present invention is by substrate growth InN layer, effectively reducing the stress produced because of lattice mismatch between substrate and GaN layer, thus reduce the generation of dislocation；And InN layer can play mask layer effect, the threading dislocation of substrate terminates at the interface between substrate and InN layer and is blocked.
2, the present invention has the SiN in cavity by inserting growth in cushionxLayer, it is achieved the laterally overgrown in later stage, reduces defect, and the most effective stop portions dislocation extends to n-type GaN layer or luminescent layer, and another part dislocation is concentrated on SiNxLayer hole region, thus increase epitaxial layer low dislocation region, reduce dislocation density, improve epitaxial wafer crystal mass.
3, the method that the present invention laterally covers growth compared to existing GaN, is not required to deposition mask layer on substrate in advance, but by depositing SiN during outer layer growthxLayer serves as mask layer, simplifies technique, it is to avoid substrate may be polluted by mask layer, and reduces production cost.
Accompanying drawing explanation
Fig. 1 is the structural representation of embodiment of the present invention LED；
Fig. 2 is the structural representation of LED cushion of the present invention；
Fig. 3 is the structural representation of another embodiment of the present invention LED；
Fig. 4 is SiN in LED cushion of the present inventionxThe structural representation of layer；
Fig. 5 is the design sketch of LED cushion of the present invention.
Detailed description of the invention
In order to make technical problem solved by the invention, technical scheme and beneficial effect clearer, below in conjunction with embodiment, the present invention is further elaborated.Should be appreciated that specific embodiment described herein, only in order to explain the present invention, is not intended to limit the present invention.
As shown in Figure 1 and Figure 2, the present invention provides a kind of LED, including substrate 1, the cushion 2 sequentially formed on substrate 1, n-type GaN layer 3, luminescent layer 4 and p-type GaN layer 5.
Described cushion 2 includes:
Being formed at the InN layer 21 on substrate 1, described InN layer 21 is distributed the cavity exposing substrate；
It is formed at the first intrinsic GaN layer 22 on described InN layer 21；
It is formed at the SiN on described first intrinsic GaN layer 22xLayer 23, described SiNxLayer 23 is distributed the cavity exposing the first intrinsic GaN layer 22；And
It is formed at described SiNxThe second intrinsic GaN layer 24 on layer 23.
In an embodiment of the present invention, described substrate 1 is plane or patterned substrate, preferably patterned substrate, and patterned substrate can reduce the epitaxial wafer defect of growth, improves epitaxial wafer crystal mass；The shape of described patterned substrate includes strip, column, cone-shaped or spherical cap shape.
The material of substrate 1 can be selected for sapphire, SiC or Si, it is preferred to use Sapphire Substrate.
Preferably, described first intrinsic GaN layer 22 is the intrinsic GaN layer of growth at 850～900 DEG C, and the second intrinsic GaN layer 24 is the intrinsic GaN layer of growth at 1000～1100 DEG C.The thickness of the first intrinsic GaN layer 22 is 50～100nm, and the thickness of the second intrinsic GaN layer 24 is 2～3um.
Described InN layer 21 and SiNxCavity is distributed on layer 23, and empty is in irregular shape.Preferably, the thickness of described InN layer 21 is 1～5nm, SiNxThe thickness of layer 23 is 1～5nm.
As shown in Figure 3, in another embodiment of the invention, LED also includes the AlGaN barrier layer 6 being formed between luminescent layer 4 and p-type GaN layer 5, AlGaN barrier layer 6 can effectively stop that electronics overflows from active area, thus increase the quantity of active area electronics, improve Carrier recombination efficiency in luminescent layer 4, promote LED chip luminous efficiency.
Preferably, luminescent layer 4 is multiple quantum well layer, including: it is formed at the doping multiple quantum well layer 41 on n-type GaN layer, is formed at the undoped multiple quantum well layer 42 on doping multiple quantum well layer.So, the luminous efficiency of LED chip can be effectively improved.
The present invention also provides for the preparation method of above-mentioned LED, said method comprising the steps of:
S101, offer substrate；
S102, Grown have expose substrate cavity InN layer；
S103, have cavity InN layer on grow the first intrinsic GaN layer；
S104, in the first intrinsic GaN layer growth have expose the first intrinsic GaN layer cavity SiNxLayer；
S105, at SiNxThe second intrinsic GaN layer is formed on layer；
S106, in the second intrinsic GaN layer formed n-type GaN layer；
S107, in n-type GaN layer formed luminescent layer；
S108, on luminescent layer formed p-type GaN layer.
Elaborate the preparation method of the LED of the present invention below in conjunction with the accompanying drawings, LED in the present invention and beneficial effect thereof also can be elaborated in preparation method.
The preparation method of the LED that the present invention provides uses NH3(ammonia) is as N source, TMGa(trimethyl gallium), TEGa(triethyl-gallium) as Ga source, TMIn(trimethyl indium) as In source, SiH4(silane) is as Si doped source, Cp2Mg(bis-cyclopentadienyl magnesium) as Mg doped source, and with N2(nitrogen), H2(hydrogen) is as carrier gas.
Step S101, it is provided that substrate 1.
In an embodiment of the present invention, described substrate 1 is plane or patterned substrate, preferably patterned substrate, and patterned substrate can reduce the epitaxial wafer defect of growth, improves epitaxial wafer crystal mass；The shape of described patterned substrate includes strip, column, cone-shaped or spherical cap shape.
The material of substrate 1 can be selected for sapphire, SiC or Si, it is preferred to use Sapphire Substrate.
Step S102, growth has the InN layer 21 in the cavity exposing substrate on substrate 1.
In being embodied as, MOCVD(MOCVD method can be used), specifically include following steps:
S201, on substrate 1 growth InN layer 21；
S202, InN layer 21 is carried out high-temperature process, make InN layer 21 decompose and form the cavity exposing substrate.
Specifically, in step S201, with NH3Being source with TMIn, under the conditions of 500～700 DEG C, grew for 100～200s times, deposition obtains the InN layer 21 that thickness is 1～5nm on substrate 1.
Specifically, in step S202, close TMIn and keep being passed through NH3, InN layer is carried out high-temperature process, i.e. rises high-temperature to 850～900 DEG C, 60s under the conditions of temperature is maintained 850～900 DEG C, make InN layer 21 decompose and form the cavity exposing substrate 1.
Step S103, grows the first intrinsic GaN layer on the InN layer with cavity.
Specifically, being passed through TMGa, on the InN layer 21 that the cavity that expose substrate 1 is distributed, deposition obtains the first intrinsic GaN layer 22, and the thickness of described first intrinsic GaN layer is 50～100nm.
InN layer 21 can be decomposed subregion during heating up and maintaining 850～900 DEG C, and substrate 1 surface is exposed in the region decomposed, thus obtains the InN layer 21 with cavity, and empty is in irregular shape.The InN layer 21 with cavity can play the effect of mask layer, and the threading dislocation of substrate 1 extends to be blocked during the interface between substrate 1 and InN layer 21, effectively reduces the impact of the threading dislocation pairs epitaxial layer of substrate 1.
In embodiments of the present invention, substrate 1 selects Sapphire Substrate, another effect of InN layer 21 is, alleviating the compression that Sapphire Substrate causes because of lattice mismatch with GaN layer, sapphire is 25% with the lattice mismatch of InN, and the crystal mismatch-9.9% of InN Yu GaN, tensile stress is introduced by depositing InN layer 21 on a sapphire substrate, can alleviate the compression that the lattice mismatch between sapphire and GaN layer causes, stress is effectively discharged, thus reduces the generation of dislocation.
Step S104, in the first intrinsic GaN layer 22 grow SiNxLayer 23, described SiNxLayer 23 is distributed the cavity exposing the first intrinsic GaN layer 22.
Specifically, closing TMGa and keep being passed through NH3, liter high-temperature, to 1000～1100 DEG C, then passes to SiH4, in the first intrinsic GaN layer 22, deposition growing thickness is the SiN of 1～5nmxLayer 23.
Step S105, at SiNxThe second intrinsic GaN layer 24 is formed on layer 23.
Specifically, SiH is closed4, it is passed through TMGa, at SiNxOn layer 23, deposition growing thickness is the second intrinsic GaN layer 24 of 2～3um.
As shown in Figure 4, due to the SiN of growth in the first intrinsic GaN layer 22xLayer 23 ratio are relatively thin, only 1～5nm, suitably control during deposition, and the region that can make will not deposit SiNxFilm, thus at SiNxFormed on layer 23 and expose the cavity 231 of the first intrinsic GaN layer 22, cavity 231 in irregular shape.
As it is shown in figure 5, have the SiN in cavityxLayer 23 can play mask layer effect equally, can realize GaN layer lateral growth, simultaneously SiNxLayer 23 can stop that dislocation upwardly extends.In figure, in epitaxial wafer, upwardly extending lines are dislocation line, at SiNxDuring carrying out laterally overgrown on layer 23, a part of dislocation is in the first intrinsic GaN layer 22 and SiNxInterface between layer 23 is blocked；Other are then continued up by cavity 231 from the threading dislocation that the first intrinsic GaN layer 22 extends up and extend to intrinsic GaN layer, when the cross section on the GaN island at empty 231 region growings forms trapezoidal or triangle, the inclination crystal face on dislocation line Hui GaN island turns to, extend to horizontal direction, so decrease upwardly extending threading dislocation quantity.Along with the deposition growing of the second intrinsic GaN layer 24, gradually the growing up and merge with adjacent GaN island of empty 231 Chu GaN islands, region, what the threading dislocation originally extended to horizontal direction had 241 again turns at adjacent GaN island merging, and upwardly extends.But, only 241 upwardly extend at adjacent GaN island merging due to this partial penetration dislocation so that in epitaxial layer, low dislocation region increases, and therefore improves the epitaxial wafer crystal mass of growth.
Step S106, in the second intrinsic GaN layer 24 formed n-type GaN layer 3.Described n-type GaN layer 3 is the GaN layer of doping Si, and Si doping content is 8e18cm-3, growth thickness is 2～3um.
Step S107, in n-type GaN layer 3 formed luminescent layer 4.
Step S108, on luminescent layer 4 formed p-type GaN layer 5.
In being embodied as, described p-type GaN layer 5 is mg-doped GaN layer.
In another embodiment of the invention, described luminescent layer 4 is multiple quantum well layer, including:
It is formed at the doping multiple quantum well layer 41 on n-type GaN layer；
It is formed at the undoped multiple quantum well layer 42 on doping multiple quantum well layer 41.
In being embodied as, described doping multiple quantum well layer 41 grows 5～7 cycles, and wherein the trap thickness of SQW is 2～3nm, and the thickness at base is 10～15nm；Doping material be Si, Si doping content be 1e17 ~ 1e18cm-3。
In being embodied as, described undoped multiple quantum well layer 42 grows 2～3 cycles, and the trap thickness of SQW is consistent with doping MQW 41 with barrier thickness.So, the luminous efficiency of LED chip can be improved.
After growth completes multiple quantum well layer, continuing growth AlGaN barrier layer 6 and p-type GaN layer 5 successively, AlGaN barrier layer 6 can effectively stop that electronics overflows from active area, thus increases the quantity of active area electronics, improve the Carrier recombination efficiency of multiple quantum well layer, promote LED chip luminous efficiency.
After completing the growth of p-type GaN layer 5, it is placed under the nitrogen environment of 710 ~ 740 DEG C the annealing carried out 20 minutes and completes the preparation of LED.
In sum, the present invention provides LED and preparation method are passed through, at substrate growth InN layer, can effectively reduce the stress produced because of lattice mismatch between substrate and GaN layer, thus reduce the generation of dislocation；And InN layer can play mask layer effect, the threading dislocation of substrate terminates at the interface between substrate and InN layer and is blocked.
And, the present invention has the SiN in cavity by inserting growth in cushionxLayer, it is achieved the laterally overgrown in later stage, reduces defect, and the most effective stop portions dislocation extends to n-type GaN layer or luminescent layer, and another part dislocation is concentrated on SiNxLayer hole region, thus increase epitaxial layer low dislocation region, reduce dislocation density, improve epitaxial wafer crystal mass.
Finally, the present invention laterally covers growth compared to GaN, is not required to deposition mask layer on substrate in advance, but by depositing SiN during outer layer growthxLayer serves as mask layer, simplifies technique, it is to avoid substrate may be polluted by mask layer, and reduces production cost.
The foregoing is only presently preferred embodiments of the present invention, not in order to limit the present invention, all any amendment, equivalent and improvement etc. made within the spirit and principles in the present invention, should be included within the scope of the present invention.
Claims (13)
1. a LED, including substrate, cushion, n-type GaN layer, luminescent layer and the p-type GaN layer that substrate sequentially forms, it is characterised in that described cushion includes:
Being formed at the InN layer of substrate, described InN layer is distributed the cavity exposing substrate；
It is formed at the first intrinsic GaN layer on described InN layer；
It is formed at the SiN on described first intrinsic GaN layerxLayer, described SiNxLayer is distributed the cavity exposing the first intrinsic GaN layer；And
It is formed at described SiNxThe second intrinsic GaN layer on Ceng.
2. a kind of LED as claimed in claim 1, it is characterised in that described first intrinsic GaN layer is the intrinsic GaN layer of growth at 850～900 DEG C, described second intrinsic GaN layer is the intrinsic GaN layer of growth at 1000～1100 DEG C.
3. a kind of LED as claimed in claim 1, it is characterised in that the thickness of described first intrinsic GaN layer is 50～100nm, and the thickness of the second intrinsic GaN layer is 2～3um.
4. a kind of LED as claimed in claim 1, it is characterised in that the thickness of described InN layer is 1～5nm.
5. a kind of LED as claimed in claim 1, it is characterised in that described SiNxThe thickness of layer is 1～5nm.
6. a kind of LED as claimed in claim 1, it is characterised in that also include: the AlGaN barrier layer being formed between luminescent layer and p-type GaN layer.
7. a kind of LED as claimed in claim 1, it is characterised in that described substrate is patterned substrate.
8. a kind of LED as claimed in claim 1, it is characterised in that described substrate is Si substrate, GaN substrate or Sapphire Substrate.
9. a kind of LED as claimed in claim 1, it is characterised in that described luminescent layer includes:
It is formed at the doping multiple quantum well layer on n-type GaN layer；
It is formed at the undoped multiple quantum well layer on doping multiple quantum well layer.
10. the preparation method of a LED, it is characterised in that comprise the following steps:
Substrate is provided；
At Grown InN layer, described InN layer has the cavity exposing substrate；
The InN layer with cavity grows the first intrinsic GaN layer；
First intrinsic GaN layer grows SiNxLayer, described SiNxLayer has the cavity exposing the first intrinsic GaN layer；
At SiNxThe second intrinsic GaN layer is formed on layer；
Second intrinsic GaN layer is formed n-type GaN layer；
N-type GaN layer is formed luminescent layer；
Luminescent layer is formed p-type GaN layer.
The preparation method of 11. a kind of LED as claimed in claim 10, it is characterised in that at Grown InN layer, described InN layer has the cavity exposing substrate, including:
At Grown InN layer；
InN layer is carried out high-temperature process, makes InN layer decompose and form the cavity exposing substrate.
The preparation method of 12. a kind of LED as claimed in claim 10, it is characterised in that also include: form AlGaN barrier layer between luminescent layer and p-type GaN layer.
The preparation method of 13. a kind of LED as claimed in claim 10, it is characterised in that form luminescent layer in n-type GaN layer, including:
N-type GaN layer is formed doping multiple quantum well layer；
Doping multiple quantum well layer forms undoped multiple quantum well layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210171423.0A CN103456852B (en) | 2012-05-30 | 2012-05-30 | A kind of LED and preparation method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210171423.0A CN103456852B (en) | 2012-05-30 | 2012-05-30 | A kind of LED and preparation method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103456852A CN103456852A (en) | 2013-12-18 |
| CN103456852B true CN103456852B (en) | 2016-09-07 |
Family
ID=49739015
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210171423.0A Expired - Fee Related CN103456852B (en) | 2012-05-30 | 2012-05-30 | A kind of LED and preparation method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103456852B (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104465899A (en) * | 2014-11-28 | 2015-03-25 | 西安神光皓瑞光电科技有限公司 | Preparation method for LED perpendicular structure |
| CN104485399B (en) * | 2014-12-01 | 2017-02-22 | 西安神光皓瑞光电科技有限公司 | Epitaxial growth method for improving epitaxial crystal quality |
| CN104900774B (en) * | 2015-05-07 | 2017-05-17 | 西北工业大学明德学院 | Transverse epitaxial growth method for double buffer layers for improving brightness of LED (Light Emitting Diode) |
| CN106480498B (en) * | 2016-10-12 | 2019-05-17 | 北京邮电大学 | A kind of nano graph substrate side epitaxial silicon based quantum dot laser equipment material and preparation method thereof |
| CN110767785A (en) * | 2019-11-12 | 2020-02-07 | 佛山市国星半导体技术有限公司 | High-quality epitaxial structure and manufacturing method thereof |
| CN111554785B (en) * | 2020-03-27 | 2021-10-08 | 华灿光电(苏州）有限公司 | Light emitting diode epitaxial wafer and preparation method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1560900A (en) * | 2004-03-05 | 2005-01-05 | 长春理工大学 | Method of growing low dislocation gallium nitride on silicon substrate |
| CN101931039A (en) * | 2010-08-23 | 2010-12-29 | 厦门市三安光电科技有限公司 | Gallium nitride based light emitting diode with double-layer staggered perforated holes and manufacturing process thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4088111B2 (en) * | 2002-06-28 | 2008-05-21 | 日立電線株式会社 | Porous substrate and manufacturing method thereof, GaN-based semiconductor multilayer substrate and manufacturing method thereof |
-
2012
- 2012-05-30 CN CN201210171423.0A patent/CN103456852B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1560900A (en) * | 2004-03-05 | 2005-01-05 | 长春理工大学 | Method of growing low dislocation gallium nitride on silicon substrate |
| CN101931039A (en) * | 2010-08-23 | 2010-12-29 | 厦门市三安光电科技有限公司 | Gallium nitride based light emitting diode with double-layer staggered perforated holes and manufacturing process thereof |
Non-Patent Citations (2)
| Title |
|---|
| InN材料及器件的最新研究进展;丁少锋等;《材料导报》;20070630;第21卷(第6期);全文 * |
| The Optical and Electrical Properties of GaN Epitaxial Films with SiNx Interlayers Inserted at Different Position;MA Zi-guang et al;《发光学报》;20111003;第32卷(第10期);全文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103456852A (en) | 2013-12-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3778344B2 (en) | Method for manufacturing light-emitting semiconductor device | |
| CN104919604B (en) | Nitride semiconductor luminescent element | |
| US8816322B2 (en) | Group III nitride semiconductor light-emitting device and production method therefor | |
| JP5704724B2 (en) | Manufacturing method of nitride semiconductor multilayer structure | |
| CN103456852B (en) | A kind of LED and preparation method | |
| CN1855370B (en) | Method of producing nitride-based semiconductor device, and light-emitting device produced thereby | |
| US20230006092A1 (en) | Light-emitting structure, method for producing the light-emitting structure, and light-emitting device | |
| CN103219438A (en) | Light emitting diode shallow trap growing method for improving stress release and carrier storage | |
| US9570656B2 (en) | Group III nitride semiconductor light-emitting device | |
| CN113690350B (en) | Micro light-emitting diode epitaxial wafer and manufacturing method thereof | |
| CN103996769A (en) | LED epitaxial layer structure, growing method of LED epitaxial layer structure and LED chip with the LED epitaxial layer structure | |
| CN114883460A (en) | Light emitting diode epitaxial wafer and preparation method thereof | |
| CN110473940B (en) | Epitaxial structure of ultraviolet LED | |
| JP2016072388A (en) | Method for manufacturing group iii nitride semiconductor light-emitting element | |
| TW201436281A (en) | Group III nitride semiconductor light-emitting device and method for producing the same | |
| KR100728132B1 (en) | Light-emitting diode using current spreading layer | |
| CN109786522B (en) | GaN-based light emitting diode epitaxial wafer and preparation method thereof | |
| CN109802022B (en) | GaN-based light emitting diode epitaxial wafer and preparation method thereof | |
| CN116722083A (en) | Preparation method of high-radiation light-emitting diode and light-emitting diode | |
| CN104733576A (en) | Light emitting diode epitaxial wafer and manufacturing method thereof | |
| JP7318603B2 (en) | Method for manufacturing group III nitride semiconductor device | |
| US9246051B2 (en) | Solid state lighting devices with reduced crystal lattice dislocations and associated methods of manufacturing | |
| CN102201516A (en) | LED (light emitting diode) with InGaN nanopillar array active region and fabrication method thereof | |
| CN116420238A (en) | LED device, LED structure and preparation method thereof | |
| CN110459654A (en) | Ultraviolet LED epitaxial structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20191230 Address after: 518119 1 Yanan Road, Kwai Chung street, Dapeng New District, Shenzhen, Guangdong Patentee after: SHENZHEN BYD MICROELECTRONICS Co.,Ltd. Address before: BYD 518118 Shenzhen Road, Guangdong province Pingshan New District No. 3009 Patentee before: BYD Co.,Ltd. |
|
| TR01 | Transfer of patent right | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 518119 No.1 Yan'an Road, Kuiyong street, Dapeng New District, Shenzhen City, Guangdong Province Patentee after: BYD Semiconductor Co.,Ltd. Address before: 518119 No.1 Yan'an Road, Kuiyong street, Dapeng New District, Shenzhen City, Guangdong Province Patentee before: SHENZHEN BYD MICROELECTRONICS Co.,Ltd. Address after: 518119 No.1 Yan'an Road, Kuiyong street, Dapeng New District, Shenzhen City, Guangdong Province Patentee after: BYD Semiconductor Co.,Ltd. Address before: 518119 No.1 Yan'an Road, Kuiyong street, Dapeng New District, Shenzhen City, Guangdong Province Patentee before: BYD Semiconductor Co.,Ltd. |
|
| CP01 | Change in the name or title of a patent holder | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20160907 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |