CN103218206A - Instruction branch pre-jump method and system - Google Patents
Instruction branch pre-jump method and system Download PDFInfo
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- CN103218206A CN103218206A CN2012100152876A CN201210015287A CN103218206A CN 103218206 A CN103218206 A CN 103218206A CN 2012100152876 A CN2012100152876 A CN 2012100152876A CN 201210015287 A CN201210015287 A CN 201210015287A CN 103218206 A CN103218206 A CN 103218206A
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Abstract
The invention discloses an instruction branch pre-jump method and an instruction branch pre-jump system. The method comprises the steps that when the judgment that a follow-up instruction contains a jump instruction is made according to the current instruction, whether the jump instruction executes jump or not is judged according to the result of the current instruction; if the judgment result is jump execution, the jump position and jump destination of the jump instruction are determined, the jump position and the jump destination are pushed to stack, if the judgment result is non-execution jump, the later instructions are executed according to the original sequence; when the jump position of the stack top is consistent with the address of an instruction to be executed, the jump position and the jump destination of the stack top are popped up, the pop-up jump destination is used as the address of the next instruction, and when the jump position of the stack top is inconsistent with the address of the instruction to be executed, the address of the instruction to be executed is used as the address of the next instruction; and the instruction is read and executed according to the address of the next instruction.
Description
Technical field
The present invention relates to a kind of pre-jump method and system of instructing branch, particularly a kind of pre-jump method and system based on mode stack.
Background technology
Therefore in the operational process of microprocessor, the appearance of jump instruction is very frequent, the processing mode remarkable influence of jump instruction performance with the microprocessor of pipeline system work.The general utility functions of jump instruction are: if satisfy a certain condition, then jump to a certain destination, instruction (for example comparison order CMP) produces and the condition that this condition normally generates the condition that redirect takes place by being used to before this jump instruction generates.Because the working method of streamline is: in the starting point reading command of streamline, produce the result of instruction at the terminal point of streamline, therefore, if execute instruction successively according to the natural order of instruction, such problem will appear: when condition generates the afterbody S of instruction at streamline
nWhen bearing results, jump instruction is in penultimate stage S
N-1, each bar instruction of arranging by natural order after the jump instruction also has been read out and has been in successively the S of streamline
1-S
N-2Level, at this moment, if the jump instruction result that generation is instructed according to condition judges the redirect condition and satisfies, need to take place redirect, that is to say no longer and execute instruction, but will carry out the instruction of the redirect destination of jump instruction, so according to natural order, each bar instruction of before reading just must be carried out in cancellation, has caused the waste of pipeline resource.
At present, solution to this problem mainly comprises groove technology and the jump forecasting technology of postponing.
The principle that postpones the groove technology is, jump instruction is shifted to an earlier date, the some that has nothing to do with redirect before the jump instruction (is promptly postponed slot length, be generally 2 or 3 regular length) instruction be placed on after the jump instruction, like this, regardless of the result that jump instruction is judged, be transferred to can carry out in proper order after the jump instruction with the irrelevant instruction of redirect.The subject matter that postpones the groove technology is, make not nature of call instruction ordering, and, it is very inflexible that this fixed length postpones groove, when lacking suitable interconvertible instruction near the jump instruction, can only satisfy the delay slot length by inserting blank operation NOP, in fact, can only constitute the delay groove by NOP in the time of most of, this causes the waste of pipeline resource equally.
The principle of jump forecasting technology is, according to should carrying out which bar instruction after a lot of historical records conjecture jump instructions, and according to the reading command as a result of conjecture, if the conjecture mistake, the false command cancel all that then will read.The problem of this jump forecasting technology is, its logic is very complicated, and hardware cost is remarkable, and some instruction of having read even having carried out is to be difficult to clean cancellation, can only be forced to postpone and carry out, and therefore influenced the performance of microprocessor greatly.
Summary of the invention
The present invention proposes a kind of pre-jump method and system of instructing branch, it has overcome the problems referred to above of the prior art, is not subjected to fixed length to postpone the restriction of groove, also need not to introduce cancellation and carries out, and has improved compiling dirigibility and pipeline efficiency, has reduced design complexities.The method according to this invention and system are particularly conducive to the optimization of loop nesting statement based on mode stack.
According to an aspect of the present invention, proposed a kind of pre-jump method that instructs branch, this method comprises:
Step S11:,, judge whether described jump instruction carries out redirect according to the result of present instruction when judging according to present instruction when comprising jump instruction in the subsequent instructions;
Step S12: if judged result is the execution redirect, then determine the jump location and the redirect destination of jump instruction, and described jump location and described redirect destination are pressed into stack, if judged result for not carrying out redirect, is then carried out instruction afterwards by original order;
Step S13: when the jump location of described stack top portion is consistent with pending instruction address, then eject the jump location and the redirect destination of described stack top portion, with address, the described redirect destination of ejecting as next bar instruction, when the jump location of described stack top portion and pending instruction address are inconsistent, then with the address of pending instruction address as next bar instruction;
Step S14 is according to the address read instruction fetch and the execution of described next bar instruction.
Preferably, step S12 realizes by pre-jump instruction, this pre-jump instruction is operated based on the result that condition generates instruction, if condition generates the result of instruction and is designated as the execution redirect, then determine the jump location and the redirect destination of jump instruction, and described jump location and described redirect destination be pressed into stack, if judged result is for carrying out redirect, then order is carried out instruction afterwards.
Preferably, described and jump instruction comprises condition field, jump location field and redirect destination field.
Preferably, the address of pending instruction is indicated by programmable counter.
According to a further aspect in the invention, proposed a kind of pre-jump system of instructing branch, this system comprises:
Be used to store the stack of pre-redirect data;
Pre-redirect module, the output of its input end link order processing module, its input end connects the input of described stack, when the output result of command process module indicates the jump instruction of back to carry out redirect, the jump location and the redirect destination of described jump instruction is pressed into described stack as the redirect data;
The instruction address comparison module, the jump location at the top of its more described stack and pending instruction address, when the jump location of described stack top portion is consistent with pending instruction address, then eject the output of the jump location of described stack top portion and redirect destination as the instruction address comparison module, when the jump location of described stack top portion and pending instruction address are inconsistent, then with of the output of described pending instruction address as the instruction address comparison module;
The instruction read module is according to the output reading command of instruction address comparison module;
Command process module is handled the instruction that the instruction read module reads, the output result.
Preferably, indicate described pending instruction address by programmable counter.
Preferably, the instruction processing unit module is carried out instruction decode, read operation number, arithmetic operation.
Description of drawings
Fig. 1 is the process flow diagram of a kind of pre-jump method that instructs branch according to an embodiment of the invention;
Fig. 2 is the schematic diagram of a pre-jump instruction;
Fig. 3 is the structural drawing of a kind of pre-jump system of instructing branch according to an embodiment of the invention;
Fig. 4 is a preferred embodiment of pre-jump system of the present invention.
Embodiment
The present invention proposes a kind of pre-jump method and system of instructing branch, its ultimate principle is: when judging the back and will redirect take place, with regard to the jump location and the redirect destination of definite redirect that will take place, thereby when proceeding to this jump location, instruction finishes skip operation.
In fact, the redirect with good conditionsi of any one in the program just can know when condition generates that all the back will have redirect and take place.For example " for " for standard circulates, just can know at loop start, be certain to face the judgement of whether redirect in the back, even according to the current numerical value of loop variable, just can know and want redirect future that the method according to this invention will jump to and where go learning the following where redirect that just indicates when wanting redirect, when before instruction proceeds to, estimating the position of redirect, the skip operation of estimating before just carrying out.
Pre-jump method of the present invention is based on mode stack, its ultimate principle is to prejudge some the redirects that the back will take place, with these redirects pop down in order, when arriving each jump location, these redirects are played stack one by one, this mode stack (promptly, pattern first-in last-out) mates with the pattern of nested loop, therefore be specially adapted to the multinest circulation.
Fig. 1 is the process flow diagram of a kind of pre-jump method that instructs branch according to an embodiment of the invention, and it comprises:
Step S11:,, determine whether described jump instruction carries out redirect according to the result of present instruction when judging according to present instruction when comprising jump instruction in the subsequent instructions;
Step S12: if judged result is the execution redirect, then determine the jump location and the redirect destination of jump instruction, and described jump location and described redirect destination are pressed into stack, if judged result for not carrying out redirect, is then carried out instruction afterwards by original order;
Step S13: when the jump location of described stack top portion is consistent with pending instruction address, then eject the jump location and the redirect destination of described stack top portion, with address, the described redirect destination of ejecting as next bar instruction, when the jump location of described stack top portion and pending instruction address are inconsistent, then with the address of pending instruction address as next bar instruction;
Step S14 is according to the address read instruction fetch and the execution of described next bar instruction.
Wherein, step S12 can realize by pre-jump instruction PJ, the function of this pre-jump instruction PJ is: the result who generates instruction based on condition operates, if condition generates the result of instruction and is designated as the execution redirect, then determine the jump location and the redirect destination of jump instruction, and described jump location and described redirect destination be pressed into stack, if judged result is for carrying out redirect, then order is carried out instruction afterwards.
Fig. 2 is the schematic diagram of a pre-jump instruction.Wherein this pre-jump instruction mainly comprises condition field #C, jump location field B and redirect destination field A.Condition field #C has stipulated the condition that redirect takes place, and #C is generally constant, can generate the sign position FLAG that instruction produces corresponding to condition.Jump location field B has indicated in performed instruction, and the position at " redirect " This move place promptly indicates the problem of " where redirect ", and this position is associated with the instruction address of the instruction of execution " redirect " operation.Redirect destination field A has indicated execution " redirect " when operation, and the branch address of instruction promptly indicates the problem of " redirect where ".
Step S13 can realize by the jump location of stack top portion is compared with the instruction address of programmable counter PC indication, wherein the address of program technic device PC indication is exactly the address of pending instruction, if the jump location of stack top is consistent with the instruction address of PC indication, indicate that then instruction has run to the position that redirect take place, then eject the jump location and the redirect destination of stack top portion, the instruction branch address of answering " redirect " to arrive when redirect is carried out exactly in this redirect destination, according to this instruction branch address reading command, just finished redirect this time.
Because the working mechanism of stack is " first-in last-out ", therefore in the multilayer nest recursion instruction, outer round-robin redirect pushes on earlier, pushes on after the redirect of interior loop, after this inevitable jump location that moves to interior loop earlier of instruction, thus the interior loop redirect at top is popped.When instruction operation during, outer cycling jump is popped, thereby finish whole multilayer nest circulation to outer round-robin jump location.
Double nested loop with standard is that example is described method of the present invention in detail below.
Below be the double round-robin c language codes of standard:
Wherein
*P++=q; It is schematic loop body.
The method that postpones groove according to traditional fixed length (being assumed to 3) compiles, and obtains following assembly instruction, and the number that always executes instruction is 65 (interior circulation 5x2 bar, outer circulation 16x4 bars):
MOV i，0 //i＝0
LOOPi: // outer circulation starting point
MOV j，0 //j＝0
LOOPj: // interior loop start
CMP J, 1 // relatively j and 2-1
JLT LOOPj // redirect when j=0
ST q, [p], 1 // delay groove 1:*p++=q
ADD j, 1 // delay groove 2:j++
NOP // delay groove 3:
// interior circulation terminal point
CMP i, 3 // relatively i and 4-1
JLT LOOPi // at i=0, circulation in 1,2 o'clock
ADD i, 1 // delay groove 1:i++
NOP // delay groove 2
NOP // delay groove 3
// outer circulation terminal point
Because having adopted length is that 3 fixed length postpones groove, after interior cycling jump instruction JLT, instruct ST and loop variable j to add 1 instruction ADD loop body as postponing groove 1 and postponing groove 2, owing to there are not other to be suitable as the instruction that postpones groove near the JLT, therefore insert the NOP instruction as postponing groove 3, in outer circulation, then need two NOP instructions as postponing groove 2 and postponing groove 3, caused the waste of the tediously long and pipeline resource of instruction.
The ground that compares, according to method of the present invention, as follows based on the instruction that above-mentioned c language program generates: the bar number that wherein always executes instruction is 49 (interior circulation 4x2 bar, outer circulation 12x4 bars):
MOV i，0 //i＝0
LOOPi: // outer circulation starting point
CMP i, 3 // relatively i and 4-1
PJ [LT] ENDi, LOOPi // at i=0, circulation in 1,2 o'clock
MOV j，0 //j＝0；
LOOPj: // interior loop start
CMP j, 1 // relatively j and 2-1
PJ [LT] ENDj, LOOPj // when j=0, circulate
ST q，[p]，1 //*p++＝q；
ADD j，1 //j++；
ENDj: // interior circulation terminal point
ADD i，1 //i++；
ENDj: // outer circulation terminal point
Loop start place outside, because i=0, the CMP instruction is judged at the outer circulation destination county redirect will be taken place, jump to the outer circulation starting point, here the effect that condition generates instruction is played in CMP instruction, " outer circulation terminal point " is exactly jump location, " outer circulation starting point " is exactly the redirect destination, therefore, insert a pre-jump instruction PJ in CMP instruction back, its effect is (to be meant i=0 here when satisfying condition [LT], 1,2), with jump location " outer circulation terminal point " ENDi and redirect destination " outer circulation starting point " LOOPi pop down.
At interior loop start place, because j=0, the CMP instruction is judged at interior circulation destination county redirect will be taken place, jump to interior loop start, therefore, insert a pre-jump instruction PJ in CMP instruction back, its effect is (to be meant j=0 here) when satisfying condition [LT], with jump location " interior circulation terminal point " ENDj and redirect destination outer circulation starting point LOOPj pop down.
Meanwhile, programmable counter PC compares the indicated pending instruction address and the jump location of stack top point in real time, in proceeding to during circulation terminal point ENGj, the pending instruction address of PC indication is corresponding to ENGj, and the jump location of stack top is also corresponding to ENGj, the two unanimity, therefore with ENGj and LOOPj bullet stack, instruction process system reads this redirect destination, promptly instructs branch address LOOPj, instruction sequence jumps to interior loop start, has finished a redirect in the interior circulation.
At this moment, because interior cycling jump position ENGj and interior cycling jump destination LOOPj have played stack, the data that stack top is deposited are outer circulation jump location ENGi and outer circulation redirect destination LOOPi.
Next, because j=1 no longer satisfies the condition of pre-jump instruction, so no longer carries out push operation, instruction sequences proceeds to the outer circulation terminal point, at this moment, the instruction address of programmable counter PC indication is outer circulation terminal point ENDi, and is consistent with the jump location ENGi of stack top, instruction process system reads this redirect destination, promptly instruct branch address LOOPi, instruction sequence jumps to the outer circulation starting point, has finished a redirect in the outer circulation.
Next, at i=1,2 o'clock repeat above-mentioned outer circulation process, up to i=3, no longer satisfy the condition of pre-jump instruction PJ, therefore push operation do not take place, and instruction sequences is carried out, and finish up to whole nested loop.
Compiler can be selected the position of pre-jump instruction freely according to the prediction to redirect.Thisly be beneficial to very much the optimization of this common circulation pattern of nested loop, thereby improve the efficient of instruction greatly based on the mechanism of stack.The method according to this invention has been equivalent to use the delay groove of selectable length, delay groove with respect to regular length, brought great dirigibility to program, redirect condition judgment and actual branch place needn't be adjacent, and need not to introduce the cancellation execution fully and the increase design difficulty.Under the situation of not using traditional jump forecasting technology, pre-jump method of the present invention just can obtain very high efficient, simultaneously, pre-redirect technology of the present invention and traditional jump forecasting technology be contradiction not, according to the needs of using, also can introduce further optimization of mechanism work that cancellation is carried out.
Fig. 3 is the structural drawing of a kind of pre-jump system of instructing branch according to an embodiment of the invention, and it comprises:
Be used to store the stack 301 of pre-redirect data;
Instruction address comparison module 305, the jump location at the top of its more described stack and pending instruction address 306, when the jump location of described stack top portion is consistent with pending instruction address, then eject the output of the jump location at described stack 301 tops and redirect destination as instruction address comparison module 305, when the jump location at described stack 301 tops and pending instruction address 306 are inconsistent, then with of the output of described pending instruction address 306 as the instruction address comparison module;
Instruction read module 307 is according to the output reading command of instruction address comparison module 305;
Fig. 4 is a preferred embodiment of pre-jump system of the present invention, under typical microprocessor architecture design, instruction address by the pending instruction of programmable counter PC indication, then this instruction address is kept among the address register ITCM, order register INS reads pending instruction according to this instruction address, and in instruction process system, decipher accordingly, the read operation number, operations such as computing, and acquisition result, if this result indicates the back can carry out the skip operation of jump instruction, the then pre-module PJM of redirect branch just is pressed into the jump location JD and the redirect destination JA of described jump instruction among the stack STA, when the instruction address comparison module compares the instruction address of programmable counter PC indication consistent with the jump location JD at the top of stack the time, then with the jump location JD and the redirect destination JA bullet stack of stack top portion, redirect destination JA wherein, be that instruction address after the redirect enters address register ITCM, the address read instruction fetch of order register after according to this redirect, and in follow-up instruction processing unit system, handle.
The foregoing description is to be used for illustrative principle of the present invention and effect thereof, but not is used to limit the present invention.Any those skilled in the art all can make amendment to the foregoing description under spirit of the present invention and category.So protection scope of the present invention, should be listed as claims of the present invention.
Claims (7)
1. one kind is instructed the pre-jump method of branch, and this method comprises:
Step S11:,, judge whether described jump instruction carries out redirect according to the result of present instruction when judging according to present instruction when comprising jump instruction in the subsequent instructions;
Step S12: if judged result is the execution redirect, then determine the jump location and the redirect destination of jump instruction, and described jump location and described redirect destination are pressed into stack, if judged result for not carrying out redirect, is then carried out instruction afterwards by original order;
Step S13: when the jump location of described stack top portion is consistent with pending instruction address, then eject the jump location and the redirect destination of described stack top portion, with address, the described redirect destination of ejecting as next bar instruction, when the jump location of described stack top portion and pending instruction address are inconsistent, then with the address of pending instruction address as next bar instruction;
Step S14 is according to the address read instruction fetch and the execution of described next bar instruction.
2. the pre-jump method of instruction according to claim 1 branch, wherein, step S12 realizes by pre-jump instruction, this pre-jump instruction is operated based on the result that condition generates instruction, if condition generates the result of instruction and is designated as the execution redirect, then determine the jump location and the redirect destination of jump instruction, and described jump location and described redirect destination are pressed into stack, if judged result is not for carrying out redirect, then order is carried out instruction afterwards.
3. the pre-jump method of instruction according to claim 2 branch wherein saidly comprises condition field, jump location field and redirect destination field with jump instruction.
4. the pre-jump method of instruction according to claim 1 branch, the address of wherein pending instruction is indicated by programmable counter.
5. one kind is instructed the pre-jump system of branch, and this system comprises:
Be used to store the stack of pre-redirect data;
Pre-redirect module, the output of its input end link order processing module, its input end connects the input of described stack, when the output result of command process module indicates the jump instruction of back to carry out redirect, the jump location and the redirect destination of described jump instruction is pressed into described stack as the redirect data;
The instruction address comparison module, the jump location at the top of its more described stack and pending instruction address, when the jump location of described stack top portion is consistent with pending instruction address, then eject the output of the jump location of described stack top portion and redirect destination as the instruction address comparison module, when the jump location of described stack top portion and pending instruction address are inconsistent, then with of the output of described pending instruction address as the instruction address comparison module;
The instruction read module is according to the output reading command of instruction address comparison module;
Command process module is handled the instruction that the instruction read module reads, the output result.
6. the pre-jump system of instruction according to claim 5 branch is wherein indicated described pending instruction address by programmable counter.
7. the pre-jump system of instruction according to claim 5 branch, wherein the instruction processing unit module is carried out instruction decode, read operation number, arithmetic operation.
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| CN107665169A (en) * | 2016-07-29 | 2018-02-06 | 龙芯中科技术有限公司 | The method of testing and device of processor program |
| CN109614146A (en) * | 2018-11-14 | 2019-04-12 | 西安翔腾微电子科技有限公司 | A kind of part jump instruction fetching method and device |
| CN111061512A (en) * | 2019-12-06 | 2020-04-24 | 湖北文理学院 | Method, device and equipment for processing branch instruction and storage medium |
| CN111898120A (en) * | 2020-06-29 | 2020-11-06 | 中国科学院信息工程研究所 | Control flow integrity protection method and device |
| CN113110879A (en) * | 2021-03-31 | 2021-07-13 | 北京中科晶上科技股份有限公司 | Instruction processing method and device |
| CN113946540A (en) * | 2021-10-09 | 2022-01-18 | 深圳市创成微电子有限公司 | DSP processor and processing method for judging jump instruction |
| CN113946539A (en) * | 2021-10-09 | 2022-01-18 | 深圳市创成微电子有限公司 | DSP processor and processing method of loop jump instruction thereof |
| CN117850881A (en) * | 2024-01-18 | 2024-04-09 | 上海芯联芯智能科技有限公司 | Instruction execution method and device based on pipelining |
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| CN107665169A (en) * | 2016-07-29 | 2018-02-06 | 龙芯中科技术有限公司 | The method of testing and device of processor program |
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| CN111061512A (en) * | 2019-12-06 | 2020-04-24 | 湖北文理学院 | Method, device and equipment for processing branch instruction and storage medium |
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| CN113110879A (en) * | 2021-03-31 | 2021-07-13 | 北京中科晶上科技股份有限公司 | Instruction processing method and device |
| CN113946540A (en) * | 2021-10-09 | 2022-01-18 | 深圳市创成微电子有限公司 | DSP processor and processing method for judging jump instruction |
| CN113946539A (en) * | 2021-10-09 | 2022-01-18 | 深圳市创成微电子有限公司 | DSP processor and processing method of loop jump instruction thereof |
| CN113946539B (en) * | 2021-10-09 | 2024-02-13 | 深圳市创成微电子有限公司 | DSP processor and processing method of circulation jump instruction thereof |
| CN113946540B (en) * | 2021-10-09 | 2024-03-22 | 深圳市创成微电子有限公司 | DSP processor and processing method for judging jump instruction thereof |
| CN117850881A (en) * | 2024-01-18 | 2024-04-09 | 上海芯联芯智能科技有限公司 | Instruction execution method and device based on pipelining |
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