CN103107161B - Pinboard structure using conducting resin as signal return plane and preparation method thereof - Google Patents
Pinboard structure using conducting resin as signal return plane and preparation method thereof Download PDFInfo
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- CN103107161B CN103107161B CN201310038716.6A CN201310038716A CN103107161B CN 103107161 B CN103107161 B CN 103107161B CN 201310038716 A CN201310038716 A CN 201310038716A CN 103107161 B CN103107161 B CN 103107161B
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- 238000002360 preparation method Methods 0.000 title claims description 12
- 239000011347 resin Substances 0.000 title abstract 10
- 229920005989 resin Polymers 0.000 title abstract 10
- 239000002184 metal Substances 0.000 claims abstract description 62
- 229910052751 metal Inorganic materials 0.000 claims abstract description 62
- 239000000758 substrate Substances 0.000 claims abstract description 45
- 238000009413 insulation Methods 0.000 claims abstract description 6
- 239000004020 conductor Substances 0.000 claims abstract description 5
- 239000012790 adhesive layer Substances 0.000 claims description 57
- 239000010410 layer Substances 0.000 claims description 37
- 239000003989 dielectric material Substances 0.000 claims description 21
- 239000007769 metal material Substances 0.000 claims description 17
- 230000004888 barrier function Effects 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 10
- 239000003292 glue Substances 0.000 claims description 9
- 239000011159 matrix material Substances 0.000 claims description 8
- 238000001259 photo etching Methods 0.000 claims description 7
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 238000004528 spin coating Methods 0.000 claims description 5
- 239000004642 Polyimide Substances 0.000 claims description 4
- 239000003822 epoxy resin Substances 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 229910052759 nickel Inorganic materials 0.000 claims description 4
- 229920000647 polyepoxide Polymers 0.000 claims description 4
- 229920001721 polyimide Polymers 0.000 claims description 4
- 229910052709 silver Inorganic materials 0.000 claims description 4
- 230000005611 electricity Effects 0.000 claims description 2
- 239000000428 dust Substances 0.000 claims 2
- 230000000149 penetrating effect Effects 0.000 abstract 1
- 238000000034 method Methods 0.000 description 11
- 239000010949 copper Substances 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 239000002365 multiple layer Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- PGLIUCLTXOYQMV-GHVWMZMZSA-N 2-[2-[4-[(r)-(4-chlorophenyl)-phenylmethyl]piperazine-1,4-diium-1-yl]ethoxy]acetic acid;dichloride Chemical compound Cl.Cl.C1CN(CCOCC(=O)O)CCN1[C@@H](C=1C=CC(Cl)=CC=1)C1=CC=CC=C1 PGLIUCLTXOYQMV-GHVWMZMZSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005253 cladding Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- YPZRWBKMTBYPTK-BJDJZHNGSA-N glutathione disulfide Chemical group OC(=O)[C@@H](N)CCC(=O)N[C@H](C(=O)NCC(O)=O)CSSC[C@@H](C(=O)NCC(O)=O)NC(=O)CC[C@H](N)C(O)=O YPZRWBKMTBYPTK-BJDJZHNGSA-N 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- -1 organosilicon Polymers 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/06181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
Landscapes
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
The invention provides a pinboard structure using conducting resin as a signal return plane. The pinboard structure using the conducting resin as the signal return plane comprises a substrate and through holes penetrating through the substrate, an insulating medium layer is formed on the front surface and/or the back surface of the substrate, metal interconnection structures are distributed in the insulating medium layer, each metal interconnection structures comprise at least one layer of horizontal interconnection structure, the metal interconnection structures are connected with the conducting materials inside the through holes, at least one conducting resin layer is arranged inside the insulating medium layer, and primary through holes are formed in the conducting resin layer for the metal interconnection structures to penetrate through the conducting resin layer without contacting with the conducting resin layer. The conducting resin layer and the horizontal interconnection structure of the metal interconnection structures are in different layers, and the conducting resin layer is in electric insulation with the metal interconnection structures. The pinboard structure using the conducting resin as the signal return plane is used for providing signal return paths of the pinboard.
Description
Technical field
The present invention relates to a kind of adapter plate structure and preparation method, especially a kind of signal returns plane for the adapter plate structure of system-level three-dimension packaging and preparation method.
Background technology
Along with integrated circuit high density, miniaturized development, technology difficulty sharply increases, and signal delay problem becomes day by day serious, and the continuity of " Moore's Law " receives serious restriction.By high frequency, at a high speed, the tight demand of multi-functional, high-performance, small size, high reliability and multifunction electronic device and promoted the development of three dimensional integrated circuits.Integrated by three-dimensional, the stacking of multi-chip can be realized in xyz all directions.
And three-dimension packaging key technology utilizes the keyset containing silicon through hole (TSV) to realize the system in package (SiP) of multiple chip, the shortest perpendicular interconnection path can be provided for chip-stacked, thus reduce circuit delay and power consumption, reduce the restriction to I/O Pin locations, improve I/O bandwidth chahnel.
Along with developing rapidly of communications industry, digital transmission rate is more and more higher, and the requirement of people to signal quality is also more and more higher, and signal integrity has become the problem of can not ignore, and this application of also connecting up again at high speed signal for keyset proposes challenge.
According to the character of transmission line, if two HW High Way are closely arranged, crosstalk serious between holding wire can be caused, thus cause distorted signals.Therefore, need for holding wire provides return path.Due to the particularity of adapter plate structure, signal cannot be used as at its surperficial large area paving copper and return plane, solution conventional is at present that cloth distribution power/ground wire, as return path, forms common GS, GSG and GSSG structure near the key signal cabling of keyset RDL layer.This mode can play the effect of signal isolation to a certain extent, but return path can not be provided for all holding wires, and the introducing of power/ground occupies a large amount of signal line wiring passages, the keyset that wiring density is higher may cause wiring block.Shown by the research in early stage, additionally increase ground wire, be not very remarkable to signal isolation effect, in some cases, in fact protection cabling may cause crosstalk to aggravate.
Summary of the invention
The problem of difficulty is set to solve existing keyset signal return flow path, the invention provides a kind of conducting resinl returns plane three-dimensional adapter plate structure and preparation method as signal, described adapter plate structure can provide effective, complete signal to return plane (i.e. return path) for whole holding wire comprises HW High Way.The technical solution used in the present invention is:
As shown in Fig. 8,9,10,11, a kind of conducting resinl returns the adapter plate structure of plane as signal, comprise substrate, run through the through hole of substrate, insulating medium layer is formed in the front of substrate and/or the back side, metal interconnect structure is distributed in insulating medium layer, metal interconnect structure comprises the interconnection structure of at least one deck horizontal direction, metal interconnect structure is connected with the electric conducting material in through hole, at least one deck conductive adhesive layer is set in insulating medium layer, conductive adhesive layer is provided with a via hole, passes conductive adhesive layer for metal interconnect structure and do not contact with conductive adhesive layer; The interconnection structure different layers of the horizontal direction of conductive adhesive layer and metal interconnect structure; Conductive adhesive layer and metal interconnect structure electric insulation.
The material that described conductive adhesive layer adopts is the structural conductive glue or filled conductive glue that are conducted electricity by self structure.Described filled conductive glue is the polymeric matrix being doped with the metal dusts such as Cu, Ag, Au or Ni; Described polymeric matrix comprises epoxy resin, organosilicon or polyimides etc.
The thickness of described conductive adhesive layer is 1-20 micron.
Conducting resinl returns a preparation method for the adapter plate structure of plane as signal, comprise the following steps,
Step (a), substrate is provided, substrate is formed vertical blind hole, and form a layer insulating at blind hole inwall and substrate top surface (front), on the insulating barrier of blind hole inwall, deposit one deck barrier layer, fills conductive metal material in blind hole;
Step (b), forms the first dielectric sublayer at insulating barrier and the upper surface of the blind hole being filled with conductive metal material;
Step (c), the first dielectric sublayer covers one deck conductive adhesive layer; Described conductive adhesive layer is formed by being covered on the first dielectric sublayer with spin coating, CVD or PVD mode by conducting resinl;
Step (d), conductive adhesive layer forms a via hole by photoetching; One time via hole penetrates conductive adhesive layer and does not contact with the blind hole on substrate, and one time via hole is positioned at directly over blind hole, and the aperture of a via hole is greater than the aperture of the blind hole on substrate;
Step (e), conductive adhesive layer covers insulating dielectric materials, forms the second dielectric sublayer; The insulating dielectric materials of the second dielectric sublayer covers conductive adhesive layer and fills a via hole;
Step (f), in the first dielectric sublayer and the second dielectric sublayer, a corresponding via hole place, forms secondary via hole by photoetching; Described secondary via hole penetrates the first dielectric sublayer and the second dielectric sublayer, contact, and the aperture of secondary via hole is less than the aperture of a via hole with the blind hole on substrate; Secondary via hole and conductive adhesive layer completely cut off by the insulating dielectric materials around secondary via hole;
Step (g), on the second dielectric sublayer forming secondary via hole, form the metal interconnect structure comprising the interconnection structure of at least one deck horizontal direction, metal interconnect structure covers insulating dielectric materials, metal interconnect structure is made to be distributed in insulating medium layer, metal interconnect structure, through secondary via hole, is connected with the conductive metal material in blind hole;
Step (h), at making front, keyset front salient point, front salient point is electrically connected with metal interconnect structure; Substrate back is thinning, expose the blind hole in substrate, make it to become through hole; At the making back side, keyset back side salient point, back side salient point is connected with the conductive metal material in through hole.
Advantage of the present invention: have good adhesiveness between conducting resinl and insulating dielectric materials, the conducting resinl material selected has good conductivity, can meet requirement on electric performance when returning plane as signal.The technique covering conducting resinl is simple, and the techniques such as available traditional spin coating and CVD, PVD realize the covering on substrate, without the need to plating.Conducting resinl material can realize graphical by existing photoetching process.Conductive adhesive layer by with power supply, be directly connected, form complete ground plane, can well for signal provides return path.The preparation method of described structure is simple, can realize by existing equipment and technique.
Accompanying drawing explanation
Fig. 1 is the structural representation after having made blind hole.
Fig. 2 is the structural representation behind formation first dielectric sublayer.
Fig. 3 is the structural representation after covering conductive adhesive layer.
Fig. 4 is the structural representation after formation via hole.
Fig. 5 is the structural representation behind formation second dielectric sublayer.
Fig. 6 is the structural representation after forming secondary via hole.
Fig. 7 is the structural representation forming metal interconnect structure.
Fig. 8 is the adapter plate structure schematic diagram made.
Fig. 9 is adapter plate structure of the present invention citing two.
Figure 10 is adapter plate structure of the present invention citing three.
Figure 11 is adapter plate structure of the present invention citing four.
Embodiment
Below in conjunction with concrete drawings and Examples, the invention will be further described.
As Fig. 8, 9, 10, shown in 11, a kind of conducting resinl returns the adapter plate structure of plane as signal, comprise substrate 101, run through the through hole 1061 of substrate 101, insulating medium layer 102 is formed in the front of substrate 101 and/or the back side, metal interconnect structure 104 is distributed in insulating medium layer 102, metal interconnect structure 104 comprises the interconnection structure of at least one deck horizontal direction, metal interconnect structure 104 is connected with the electric conducting material in through hole 1061, at least one deck conductive adhesive layer 103 is set in insulating medium layer 102, conductive adhesive layer 103 is provided with a via hole 108, pass conductive adhesive layer 103 for metal interconnect structure 104 and do not contact with conductive adhesive layer 103, the interconnection structure different layers of the horizontal direction of conductive adhesive layer 103 and metal interconnect structure 104, conductive adhesive layer 103 and metal interconnect structure 104 electric insulation.
Conducting resinl returns a preparation method for the adapter plate structure of plane as signal, comprise the following steps,
Step (a), as shown in Figure 1, provides substrate 101, form vertical blind hole 106 on the substrate 101, this substrate 101 thickness is 300-700 micron, and the degree of depth of blind hole 106 is 20-200 micron, diameter is 5-150 micron, and backing material is the carrier such as silicon chip, glass.Then form a layer insulating 201 at blind hole 106 inwall and substrate 101 upper surface (front), described insulating barrier 201 is formed by the technique such as thermal oxidation, deposition, and its material is silicon dioxide, silicon nitride etc.Continue by CVD or other method deposit one deck barrier layer 202 on the insulating barrier 201 of blind hole 106 inwall, described barrier layer 202 is the materials such as Ti, Ta.Finally by plating, plant the modes such as ball fills the conductive metal material such as copper, tin blind hole 106 in, the insulating barrier 201 grinding substrate 101 upper surface makes its planarization with blind hole 106 upper surface being filled with conductive metal material.
Step (b), as shown in Figure 2, covers insulating dielectric materials at insulating barrier 201 and the upper surface of the blind hole 106 being filled with conductive metal material, forms the first dielectric sublayer 1021.Described insulating dielectric materials can be the SiO2 by thermal oxide growth, or by dielectrics such as PBO, PI, SiN of the deposit of the method such as spin coating, PVD or CVD, the first dielectric sublayer 1021 thickness is 1-20 micron.
Step (c), as shown in Figure 3, the first dielectric sublayer 1021 covers one deck conductive adhesive layer 103; In this example, the material of conductive adhesive layer 103 adopts filled conductive glue, is specially the polymeric matrix being doped with the metal dusts such as Cu, Ag, Au, Ni; Polymeric matrix can adopt the materials such as epoxy resin, organosilicon, polyimides; Filled conductive glue covers on the first dielectric sublayer 1021 by the mode such as spin coating, CVD, PVD, and the thickness of the conductive adhesive layer 103 of formation is 1-20 micron; Conducting resinl possesses good viscosity.
Step (d), as shown in Figure 4, conductive adhesive layer 103 forms a via hole 108 by photoetching; One time via hole 108 penetrates conductive adhesive layer 103 and does not contact with the blind hole 106 on substrate 101, and one time via hole 108 is positioned at directly over blind hole 106, and the aperture of a via hole 108 is greater than blind hole 106 aperture on substrate 101; The effect of a via hole 108 is passed conductive adhesive layer 103 for the metal interconnect structure 104 formed below and do not contact with conductive adhesive layer 103.
Step (e), as shown in Figure 5, conductive adhesive layer 103 covers insulating dielectric materials, forms the second dielectric sublayer 1022; The insulating dielectric materials of the second dielectric sublayer 1022 covers conductive adhesive layer 103 and fills a via hole 108; The insulating dielectric materials of the second dielectric sublayer 1022 can be identical with the insulating dielectric materials of the first dielectric sublayer 1021; The thickness of the second dielectric sublayer 1022 is 1-20 micron.So far, the insulating medium layer 102 in the present invention comprises: the first dielectric sublayer 1021 and the second dielectric sublayer 1022;
Step (f), as shown in Figure 6, in the first dielectric sublayer 1021 and the second dielectric sublayer 1022, corresponding via hole 108 place, forms secondary via hole 109 by photoetching; Described secondary via hole 109 penetrates the first dielectric sublayer 1021 and the second dielectric sublayer 1022, contact with the blind hole 106 on substrate 101, and the aperture of secondary via hole 109 is less than the aperture of a via hole 108, secondary via hole 109 and conductive adhesive layer 103 are completely cut off by the insulating dielectric materials around secondary via hole 109, reaches the object of insulation;
Step (g), on the second dielectric sublayer 1022 forming secondary via hole 109, form the metal interconnect structure 104 comprising the interconnection structure of at least one deck horizontal direction, metal interconnect structure 104 covers insulating dielectric materials, metal interconnect structure 104 is made to be distributed in insulating medium layer 102, metal interconnect structure 104, through secondary via hole 109, is connected with the conductive metal material in blind hole 106;
Specifically as shown in Figure 7, on the second dielectric sublayer 1022 forming secondary via hole 109, cover layer of metal electric conducting material by techniques such as plating, and this conductive metal material is filled in secondary via hole 109, is connected with the conductive metal material in the blind hole 106 on substrate 101; Get rid of unwanted metal material by chemical wet etching, define the metal interconnect structure 104 of the interconnection structure comprising one deck horizontal direction; If the metal interconnect structure 104 comprising the interconnection structure of one deck horizontal direction has met the needs of keyset, then can cover insulating dielectric materials and form top layer dielectric sublayer on metal interconnect structure 104, adapter plate structure of the present invention is close to having prepared.Multilayer insulation medium sublayer (now having comprised the first dielectric sublayer 1022, dielectric sublayer 1021, second, top layer dielectric sublayer) just constitutes total insulating medium layer 102.
Due to the common technique means that the preparation technology comprising the metal interconnect structure 104 of multiple-layer horizontal direction interconnection structure is this area, and be not the emphasis (preparing conductive adhesive layer 103 as returning plane) that the present invention will propose, the preparation technology therefore for the metal interconnect structure 104 comprising multiple-layer horizontal direction interconnection structure does not do deep expansion description.Further, if need the metal interconnect structure 104 comprising multiple-layer horizontal direction interconnection structure, then can after defining the metal interconnect structure 104 of the interconnection structure comprising one deck horizontal direction, insulating dielectric materials is covered on metal interconnect structure 104, and repeatedly electroplate, lithographic etch process is formed has the metal interconnect structure 104 of multiple-layer horizontal direction interconnection structure, on metal interconnect structure 104, finally cover insulating dielectric materials form top layer dielectric sublayer.Metal interconnect structure 104 can provide path for Signal transmissions.
The conductive metal material of metal interconnect structure 104 can select Cu, and cladding thickness can be 1-10 micron, and the routing line width degree of metal interconnect structure 104 can be 5-100 micron in the horizontal direction.
Step (h), as shown in Figure 8, at making front, keyset front salient point 105, front salient point 105 is electrically connected with metal interconnect structure 104; By substrate 101 thinning back side, expose the blind hole 106 in substrate 101, make it to become through hole 1061; At the making back side, keyset back side salient point 107, back side salient point 107 is connected with the conductive metal material in through hole 1061.Finally realize interconnection structure complete in keyset vertical direction.
Adopt the method similar with above-mentioned steps, the adapter plate structure of analog structure can be prepared, as shown in Fig. 9, Figure 10, Figure 11, conductive adhesive layer 103 can be arranged in the front of substrate 101 or the insulating medium layer 102 at the back side, conductive adhesive layer 103 also can arrange multilayer, can be arranged at any position having electrical property to need in the front of described substrate 101 or the insulating medium layer 102 at the back side.
In Fig. 9, conductive adhesive layer 103 is arranged in the insulating medium layer 102 in the front of described substrate 101, is positioned at the centre of the two-layer horizontal direction interconnection structure of metal interconnect structure 104.
In Figure 10, in the insulating medium layer 102 in the front of substrate 101, be provided with two-layer conductive adhesive layer 103, lay respectively at centre and the below of the two-layer horizontal direction interconnection structure of metal interconnect structure 104.
In Figure 11, conductive adhesive layer 103 is arranged in the insulating medium layer 102 at the back side of described substrate 101.
In actual applications, signal transmits in metal interconnect structure 104, arrange conductive adhesive layer 103 in the application can with power supply, be directly connected, form complete ground plane, (positive pole of DC power supply equals AC earth in signal communication analysis), thus can well for signal provides return path.
Above-described specific embodiment; object of the present invention, technical scheme and beneficial effect are further described; be understood that; the foregoing is only specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (6)
1. one kind returns the adapter plate structure of plane as signal with conducting resinl, comprise substrate (101), run through the through hole (1061) of substrate (101), insulating medium layer (102) is formed in the front of substrate (101) and/or the back side, metal interconnect structure (104) is distributed in insulating medium layer (102), metal interconnect structure (104) comprises the interconnection structure of at least one deck horizontal direction, metal interconnect structure (104) is connected with the electric conducting material in through hole (1061)
It is characterized in that: at least one deck conductive adhesive layer (103) is set in insulating medium layer (102), conductive adhesive layer (103) is provided with a via hole (108), does not contact with conductive adhesive layer (103) through conductive adhesive layer (103) for metal interconnect structure (104); The interconnection structure different layers of the horizontal direction of conductive adhesive layer (103) and metal interconnect structure (104); Conductive adhesive layer (103) and metal interconnect structure (104) electric insulation.
2. conducting resinl as claimed in claim 1 returns the adapter plate structure of plane as signal, it is characterized in that: the material that described conductive adhesive layer (103) adopts is the structural conductive glue or filled conductive glue that are conducted electricity by self structure.
3. conducting resinl as claimed in claim 2 returns the adapter plate structure of plane as signal, it is characterized in that: described filled conductive glue is the polymeric matrix being doped with Cu, Ag, Au or Ni metal dust; Described polymeric matrix comprises epoxy resin, organosilicon or polyimides.
4. conducting resinl as claimed in claim 1 returns the adapter plate structure of plane as signal, it is characterized in that: the thickness of described conductive adhesive layer (103) is 1-20 micron.
5. return a preparation method for the adapter plate structure of plane with conducting resinl as signal, it is characterized in that: comprise the following steps,
Step (a), substrate (101) is provided, in the blind hole (106) that the upper formation of substrate (101) is vertical, and form a layer insulating (201) at blind hole (106) inwall and substrate (101) upper surface, on the upper deposit one deck barrier layer (202) of the insulating barrier (201) of blind hole (106) inwall, in blind hole (106), fill conductive metal material;
Step (b), forms the first dielectric sublayer (1021) at the upper surface of insulating barrier (201) and the blind hole (106) that is filled with conductive metal material;
Step (c), upper covering one deck conductive adhesive layer (103) in the first dielectric sublayer (1021); By being covered with spin coating, CVD or PVD mode by conducting resinl, the first dielectric sublayer (1021) is upper to be formed described conductive adhesive layer (103);
Step (d), conductive adhesive layer (103) forms a via hole (108) by photoetching; One time via hole (108) penetrates conductive adhesive layer (103) and does not contact with the blind hole (106) on substrate (101), one time via hole (108) is positioned at directly over blind hole (106), and the aperture of a via hole (108) is greater than the aperture of the blind hole (106) on substrate (101);
Step (e), conductive adhesive layer (103) covers insulating dielectric materials, forms the second dielectric sublayer (1022); The insulating dielectric materials of the second dielectric sublayer (1022) covers conductive adhesive layer (103) and fills a via hole (108);
Step (f), in the first dielectric sublayer (1021) and the second dielectric sublayer (1022), corresponding via hole (108) place, forms secondary via hole (109) by photoetching; Described secondary via hole (109) penetrates the first dielectric sublayer (1021) and the second dielectric sublayer (1022), contact with the blind hole (106) on substrate (101), and the aperture of secondary via hole (109) is less than the aperture of a via hole (108); Secondary via hole (109) and conductive adhesive layer (103) completely cut off by secondary via hole (109) insulating dielectric materials around;
Step (g), on the second dielectric sublayer (1022) forming secondary via hole (109), form the metal interconnect structure (104) comprising the interconnection structure of at least one deck horizontal direction, metal interconnect structure (104) covers insulating dielectric materials, metal interconnect structure (104) is made to be distributed in insulating medium layer (102), metal interconnect structure (104), through secondary via hole (109), is connected with the conductive metal material in blind hole (106);
Step (h), in making front, keyset front salient point (105), front salient point (105) is electrically connected with metal interconnect structure (104); By substrate (101) thinning back side, expose the blind hole (106) in substrate (101), make it to become through hole (1061); At the making back side, keyset back side salient point (107), back side salient point (107) is connected with the conductive metal material in through hole (1061).
6. conducting resinl as claimed in claim 5 returns the preparation method of the adapter plate structure of plane as signal, it is characterized in that: the material that described conductive adhesive layer (103) adopts is filled conductive glue, is specially the polymeric matrix being doped with Cu, Ag, Au or Ni metal dust; Described polymeric matrix comprises epoxy resin, organosilicon or polyimides; The thickness of described conductive adhesive layer (103) is 1-20 micron.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310038716.6A CN103107161B (en) | 2013-01-31 | 2013-01-31 | Pinboard structure using conducting resin as signal return plane and preparation method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310038716.6A CN103107161B (en) | 2013-01-31 | 2013-01-31 | Pinboard structure using conducting resin as signal return plane and preparation method thereof |
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| Publication Number | Publication Date |
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| CN103107161A CN103107161A (en) | 2013-05-15 |
| CN103107161B true CN103107161B (en) | 2015-04-01 |
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| CN103681619B (en) * | 2013-12-18 | 2016-09-07 | 中国电子科技集团公司第五十八研究所 | A kind of silica-based hermetic sealing structure and manufacture method thereof |
| CN108615772B (en) * | 2018-05-17 | 2020-05-12 | 中国科学院微电子研究所 | Packaging structure of sensor and manufacturing method thereof |
| CN110767554A (en) * | 2019-11-15 | 2020-02-07 | 上海先方半导体有限公司 | Silicon-based adapter plate structure for reducing equivalent dielectric constant and preparation method thereof |
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| CN102569032A (en) * | 2012-01-16 | 2012-07-11 | 中国科学院上海微系统与信息技术研究所 | Method for manufacturing inductance element by overlapping multiple layers of metalized thin films |
| CN102856278A (en) * | 2012-09-17 | 2013-01-02 | 中国科学院微电子研究所 | Adapter plate structure and manufacturing method thereof |
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| CN102569032A (en) * | 2012-01-16 | 2012-07-11 | 中国科学院上海微系统与信息技术研究所 | Method for manufacturing inductance element by overlapping multiple layers of metalized thin films |
| CN102856278A (en) * | 2012-09-17 | 2013-01-02 | 中国科学院微电子研究所 | Adapter plate structure and manufacturing method thereof |
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