CN103096613A - Printed circuit board and manufacture method thereof - Google Patents
Printed circuit board and manufacture method thereof Download PDFInfo
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- CN103096613A CN103096613A CN201110347851XA CN201110347851A CN103096613A CN 103096613 A CN103096613 A CN 103096613A CN 201110347851X A CN201110347851X A CN 201110347851XA CN 201110347851 A CN201110347851 A CN 201110347851A CN 103096613 A CN103096613 A CN 103096613A
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Abstract
The invention provides a printed circuit board and a manufacture method of the printed circuit board. The printed circuit board comprises a first wiring layer, a second wiring layer, a first plane layer and a second plane layer, wherein the first plane layer and the second plane layer are arranged between the first wiring layer and the second wiring layer. The printed circuit board further comprises a penetrating hole structure which penetrates through the first wiring layer, the first plane layer, the second plane layer and the second wiring layer. The penetrating hole structure comprises a through hole, a first conductor layer arranged on the inner wall of the through hole, a first insulating layer arranged on the ring surface of the first conductor layer, and a second conductor layer arranged on the ring surface of the first insulating layer, wherein the first conductor layer is electrically connected with the first plane layer or the second plane layer, and is connected with the first wiring layer and the second wiring layer in an electric insulation mode, and the second conductor layer is electrically connected with the first wiring layer and the second wiring layer, and serves as a signal carrier to transmit a signal produced by the first wiring layer to the second wiring layer.
Description
Technical field
Content of the present invention relates to a kind of printed circuit board (PCB), and particularly relevant for the improved printed circuit board (PCB) of a kind of via structure and method thereof.
Background technology
Along with the raising day by day that in practical application, digital information processing system is required, the raising of signal transmission characteristics has become the problem that the high-speed figure printed circuit board designer must be concerned about.When signal integrity refers to circuit transmissioning signal to the fidelity of signal waveform.After good signal integrity referred to that signal passes through transmission circuit, the waveform of signal receiving end and the waveform of signal sending end were consistent in the tolerance scope, and influencing each other between the signal transmission of spatial neighbor also will be within the scope that error is allowed.Can the quality that signal integrity is processed be directly connected to system and work.The problem of bringing due to the delay of signal, the signal transmission such as reflect, crosstalk can cause signal quality to degenerate, can cause the signal logic mistake when serious, therefore guarantee coupling and the uniform continuity of signal transmssion line characteristic impedance, to guarantee certain signal quality of receiving terminal, it is the key of high-speed figure PCB design.And theory and practice all proves, HW High Way need to realize that it is a key factor that causes signal transmssion line impedance discontinuity, signal integrity distortion that layer printed circuit board is connected with the signal of interlayer by via hole.
Many-sided and cause the reason of via hole place impedance discontinuity, such as diameter, the degree of depth (STUB), pad (PAD) size and anti-pad (ANTI-PAD) size etc. of via hole.Current, thus be mainly to coordinate to optimize via hole to reduce high speed signal through the impedance discontinuity situation at via hole place to the size of via hole and with the size of anti-pad.
With reference to Fig. 1, Fig. 1 has illustrated the generalized section of the printed circuit board (PCB) with existing via hole.As shown in Figure 1, printed circuit board (PCB) 1 comprises four layers of L1, L2, L3 and L4, and high speed signal switches to the 4th layer of L4 by via hole from ground floor L1.Ground floor L1 and the 4th layer of L4 are wiring layer, have on ground floor L1 and have cabling 17 and pad 18 on cabling 11 and 12, the four layers of L4 of pad.Second layer L2 and the 3rd layer of L3 are plane layer, and wherein, the Copper Foil 14 that second layer L2 is provided with ground connection (GND) is provided with 15, the three layers of L3 of anti-pad the Copper Foil 16 and anti-pad 15 that connects power supply (POWER).Filled dielectric 29 between four layers of L1, L2, L3 and L4.
As shown in Figure 1, existing via hole comprises pad 12, through hole 13 and pad 18.And as seen from the figure, be discontinuous owing to making the reference planes of through hole 13 being separated by of three-layer insulated medium.Therefore, at this moment, can not calculate at the resistance value at through hole 13 places with the experience formula of impedance.
Specifically, in the prior art, only consider that making certain Coordination Treatment aspect the size of via hole and anti-pad big or small does little optimization, and do not do the most effectively optimization from basic reference planes.
In view of this, how designing a kind of printed circuit board (PCB) with via structure, so that the reference planes of via structure are continuous, thereby make via hole place's impedance more continuous, is the technical problem that needs to be resolved hurrily of person skilled in the industry.
Summary of the invention
In order to solve the problems of the technologies described above.The present invention proposes a kind of printed circuit board (PCB), comprise one first wiring layer, one second wiring layer and one first plane layer between described the first wiring layer and described the second wiring layer and one second plane layer, described printed circuit board (PCB) also comprises through a via structure of described the first wiring layer, described the first plane layer, described the second plane layer and described the second wiring layer, and described via structure comprises: a through hole; One first conductor layer is positioned on the inwall of described through hole; One first insulating barrier is positioned on the ring surface of described the first conductor layer; And one second conductor layer, be positioned on the ring surface of described the first insulating barrier; Wherein, described the first conductor layer is electrically connected and is electrically insulated with described the first wiring layer and described the second wiring layer with described the first plane layer or described the second plane layer and is connected, described the second conductor layer and described the first wiring layer and described the second wiring layer are electrically connected, as signal vehicle to transmit the signal that produced in described the first wiring layer to described the second wiring layer.
Preferably, during as the reference plane layer, described the first conductor layer and described the first plane layer are electrically connected, and described the second plane layer is provided with one first anti-pad to isolate described the first conductor layer and described the second plane layer when described the first plane layer.
Preferably, during as the reference plane layer, described the first conductor layer and described the second plane layer are electrically connected, and described the first plane layer is provided with one second anti-pad to isolate described the first conductor layer and described the first plane layer when described the second plane layer.
Preferably, described the first conductor layer has dielectric respectively and between described the first wiring layer and described the second wiring layer, so that described the first conductor layer and described the first wiring layer and described the second wiring layer are electrically insulated.
Preferably, described the first wiring layer be provided with one first pad and with at least one first cabling of its electric connection; And described the second wiring layer is provided with, and one second pad reaches and at least one second cabling of its electric connection; Wherein, described the first pad and described the second pad are electrically connected mutually with the two ends of described the second conductor layer respectively, and the described signal in described the first cabling sees through described the first pad, described the second conductor layer and described the second pad and is passed to described the second cabling.
Preferably, described the first plane layer is ground plane layer.
Preferably, described the second plane layer is the power plane layer
Another aspect of the present invention has proposed a kind of manufacture method of printed circuit board (PCB), comprises to form a via structure, forms described via structure and comprises: a) form a through hole in described printed circuit board (PCB); B) form one first conductor layer on the inwall of described through hole; C) form an insulating barrier on the ring surface of described the first conductor layer; And d) form one second conductor layer on the ring surface of described insulating barrier; Wherein, described the first conductor layer and a reference planes layer are electrically connected, described the second conductor layer as signal vehicle to transmit a signal.
Preferably, described step b and described steps d by plating mode to realize.
Preferably, described step c comprises: fill up dielectric in the described through hole that forms described the first metal layer; And hole to form described insulating barrier in filling up the described through hole of described dielectric.
As from the foregoing, based on the printed circuit board (PCB) of via structure proposed by the invention, the place has continuous reference planes at its via hole, therefore makes through hole impedance more continuous, and then has improved signal integrity.
Description of drawings
Fig. 1 has illustrated the generalized section of the printed circuit board (PCB) with existing via hole;
Fig. 2 has illustrated the generalized section of the printed circuit board (PCB) of an embodiment of the present invention;
Fig. 3 has illustrated via structure shown in Figure 2 along the cross sectional representation of A-A ' line; And
Fig. 4 has illustrated the flow chart of manufacture method of the via structure of another embodiment of the present invention.
Embodiment
Hereinafter to coordinate appended graphic elaborating for embodiment, but the embodiment that provides limits the scope that the present invention is contained, and the description of structure running is non-in order to limit the order of its execution, any structure that is reconfigured by element, the device with impartial effect that produces is all the scope that the present invention is contained.In addition, graphic only for the purpose of description, do not map according to life size.
About " approximately " used herein, " approximately " generally typically refer to " roughly " error of numerical value or scope in percentage 20 in, be preferably in percentage ten in, be more preferably in percentage five in.Wen Zhongruo is without offering some clarification on, and its mentioned numerical value is all regarded as approximation, namely as " approximately ", " approximately " or " roughly " represented error or scope.
Please refer to Fig. 2 and Fig. 3, Fig. 2 has illustrated the generalized section of the printed circuit board (PCB) of an embodiment of the present invention, and Fig. 3 has illustrated via structure shown in Figure 2 along the cross sectional representation of A-A ' line.
As shown in Figure 2, in the present embodiment, printed circuit board (PCB) 2 is four laminates, namely comprises four layers of L1, L2, L3 and L4.In the present embodiment, ground floor (top layer) L1 and the 4th layer of (bottom) L4 are wiring layer, and second layer L2 and the 3rd layer of L3 are plane layer.In the present embodiment, high speed signal switches to the 4th layer of L4 by via hole from ground floor L1.
It should be noted that, describe as an example of four laminates example in the present embodiment, still, in some other embodiment, printed circuit board (PCB) 2 can be six laminates, eight laminates, ten laminates and Floor 12 plate etc., that is, do not limit printed circuit board (PCB) 2 and be several laminates.And, in these execution modes, for the configuration of each layer in printed circuit board (PCB) 2, i.e. laying-out and wiring layer or plane layer, reasonable disposition, might not be configured according to the configuration mode in present embodiment as required.
As shown in Figure 2, have on ground floor L1 on cabling 21 and 22, the four layers of L4 of pad and have cabling 28 and pad 29, in the present embodiment, cabling 21 and 28 quantity do not limit.25, the three layers of L3 of Copper Foil that second layer L2 is provided with ground connection (GND) are provided with the Copper Foil 26 and anti-pad 27 that connects power supply (POWER), and in other words, plane layer L2 is ground plane layer, and plane layer L3 is the power plane layer.In the present embodiment, four layers of each interlayer of L1, L2, L3 and L4 have all been filled dielectric 30.
As shown in Fig. 2,3, via structure (not indicating) comprises through hole (boring) 23, the first conductor layer 24A, insulating barrier 24B and the second conductor layer 24C.Wherein, through hole 23 is opened in printed circuit board (PCB) 2, and two ends extend to respectively wiring layer L1 and wiring layer L4, namely through four layers of L1 to L4; Conductor layer 24A is positioned on the inwall of through hole 23, and insulating barrier 24B is positioned on the ring surface of conductor layer 24A, and conductor layer 24C is positioned on the ring surface of insulating barrier 24; Conductor layer 24A can be used for be electrically connected the reference planes layer, and insulating barrier 24B can be used for spaced conductors layer 24A and conductor layer 24C, prevents that both are electrically connected, 24C can be used as signal vehicle with the high speed signal in transmission wiring layer L1 to wiring layer L4.
In the present embodiment, plane layer L2 as the reference plane layer, namely is reference planes take ground, at this moment, conductor layer 24A will be electrically connected with the copper foil 25 that is arranged in plane layer L2.And, in the present embodiment, be provided with anti-pad 27 in plane layer L3, be arranged on copper foil 26 and conductor layer 24A in plane layer L3 in order to isolation, in case copper foil 26 is electrically connected with conductor layer 24A.In addition, conductor layer 24A adopts the buried-hole structure design, namely is provided with dielectric between itself and wiring layer L1 and wiring layer L4, so that be electrically insulated between conductor layer 24A and wiring layer L1 and wiring layer L4.
In the present embodiment, due to conductor layer 24A and reference planes layer L2 electric connection, namely be reference planes take ground, making the via hole in printed circuit board (PCB) 2 is all ground in whole reference planes on vertically, namely, via hole has continuous reference planes, so through hole impedance is also more continuous, and then has improved the Signal integrity of the via hole of flowing through.
In some other execution mode, as the reference plane layer, namely take power plane as reference planes, at this moment, conductor layer 24A will be electrically connected with the copper foil 26 that is arranged in plane layer L3 with plane layer L3.On the contrary, in these execution modes, be provided with anti-pad 27 in plane layer L2, be arranged on copper foil 25 and conductor layer 24A in plane layer L2 in order to isolation, in case copper foil 25 is electrically connected with conductor layer 24A.
In the present embodiment, via structure can also comprise the pad 22 that is arranged in wiring layer L1, is arranged on the pad 29 in wiring layer L4 and is arranged on anti-pad 27 in plane layer L3.
In the present embodiment, pad 22 and pad 29 are electrically connected mutually with the two ends of conductor layer 24C respectively, and at this moment, the high speed signal in cabling 21 sees through pad 22, conductor layer 24C and pad 29 and is passed to cabling 28.
As shown in Figure 3, through hole 23, conductor layer 24A, insulating barrier 24B and conductor layer 24C are circular along the figure of the cross section of A-A ' line, but not as limit, in some other embodiment, the shape of through hole 23, conductor layer 24A, insulating barrier 24B and conductor layer 24C can be other shape, such as oval or other.
In the present embodiment, can also respectively have an insulating barrier (not illustrating) at the upper surface of wiring layer L1 and at the lower surface of wiring layer L4, to cover respectively wiring layer L1 and wiring layer L4.
In the present embodiment, the material of conductor layer 24A and conductor layer 24C comprises metal or other electric conducting material for the material of conduction, preferably, is copper, but not as limit.Size for conductor layer 24A and conductor layer 24C can be about 0.5mm, but not as limit, can rationally arrange according to demand.
In the present embodiment, the material of insulating barrier 24B and dielectric 30 is insulating material, preferably, is polypropylene, but not as limit.
With reference to Fig. 4, Fig. 4 has illustrated the flow chart of manufacture method of the printed circuit board (PCB) of another embodiment of the present invention.
The below please refer to Fig. 2, Fig. 3 and shown in Figure 4, and in the present embodiment, the printed circuit board (PCB) of made need to form a via structure, can be namely that half-finished printed circuit board (PCB) is made its via structure to form aforementioned printed circuit board (PCB) to one.It is as described below that its via structure is made flow process.
At first, in step 410, form through hole 23 in printed circuit board (PCB) 2, this through hole 23 is through printed circuit board (PCB) 2.
Then, enter step 420, form the first conductor layer 24A on the inwall of through hole 23, this conductor layer 24A and reference planes layer are electrically connected, and in the present embodiment, the reference planes layer can be plane layer L2 (as Fig. 2), be that conductor layer 24A and plane layer L2 are electrically connected, the reference planes layer can be also other plane layer, take other as the plane of reference, as plane layer L3.
Afterwards, enter step 430, form insulating barrier 24B on the ring surface of the first conductor layer 24A.
Then, enter step 440, form the second conductor layer 24C on the ring surface of insulating barrier 24B, in the present embodiment, conductor layer 24C can be used as signal vehicle to transmit signal in wiring layer L1 to wiring layer L4, and this signal especially, is high speed signal.
In the present embodiment, for step 420 and 440, can adopt plating mode to form conductor layer 24A and conductor layer 24C.
In the present embodiment, for step 430, can realize in the following way:
At first, fill up dielectric in the through hole 23 that forms conductor layer 24C, as fill up polypropylene.
Secondly, hole to form insulating barrier 24B in the through hole 23 that fills up dielectric.
As from the foregoing, based on the printed circuit board (PCB) of via structure proposed by the invention, the place has continuous reference planes at its via hole, therefore makes through hole impedance more continuous, and then has improved signal integrity.
Above, describe the specific embodiment of the present invention with reference to the accompanying drawings.But those skilled in the art can understand, in the situation that without departing from the spirit and scope of the present invention, can also do various changes and replacement to the specific embodiment of the present invention.These changes and replacement all drop in claims limited range of the present invention.
Claims (10)
1. printed circuit board (PCB), comprise one first wiring layer, one second wiring layer and one first plane layer between described the first wiring layer and described the second wiring layer and one second plane layer, described printed circuit board (PCB) also comprises through a via structure of described the first wiring layer, described the first plane layer, described the second plane layer and described the second wiring layer, it is characterized in that, described via structure comprises:
One through hole;
One first conductor layer is positioned on the inwall of described through hole;
One first insulating barrier is positioned on the ring surface of described the first conductor layer; And
One second conductor layer is positioned on the ring surface of described the first insulating barrier;
Wherein, described the first conductor layer is electrically connected and is electrically insulated with described the first wiring layer and described the second wiring layer with described the first plane layer or described the second plane layer and is connected, described the second conductor layer and described the first wiring layer and described the second wiring layer are electrically connected, as signal vehicle to transmit the signal that produced in described the first wiring layer to described the second wiring layer.
2. printed circuit board (PCB) according to claim 1, it is characterized in that, when described the first plane layer during as the reference plane layer, described the first conductor layer and described the first plane layer are electrically connected, and described the second plane layer is provided with one first anti-pad to isolate described the first conductor layer and described the second plane layer.
3. printed circuit board (PCB) according to claim 1, it is characterized in that, when described the second plane layer during as the reference plane layer, described the first conductor layer and described the second plane layer are electrically connected, and described the first plane layer is provided with one second anti-pad to isolate described the first conductor layer and described the first plane layer.
4. according to claim 2 or 3 described printed circuit board (PCB)s, it is characterized in that, described the first conductor layer has dielectric respectively and between described the first wiring layer and described the second wiring layer, so that described the first conductor layer and described the first wiring layer and described the second wiring layer are electrically insulated.
5. printed circuit board (PCB) according to claim 1 is characterized in that:
Described the first wiring layer be provided with one first pad and with at least one first cabling of its electric connection; And
Described the second wiring layer be provided with one second pad and with at least one second cabling of its electric connection;
Wherein, described the first pad and described the second pad are electrically connected mutually with the two ends of described the second conductor layer respectively, and the described signal in described the first cabling sees through described the first pad, described the second conductor layer and described the second pad and is passed to described the second cabling.
6. printed circuit board (PCB) according to claim 1, is characterized in that, described the first plane layer is ground plane layer.
7. printed circuit board (PCB) according to claim 1, is characterized in that, described the second plane layer is the power plane layer
8. the manufacture method of a printed circuit board (PCB), comprise formation one via structure, it is characterized in that, forms described via structure and comprise:
A) form a through hole in described printed circuit board (PCB);
B) form one first conductor layer on the inwall of described through hole;
C) form an insulating barrier on the ring surface of described the first conductor layer; And
D) form one second conductor layer on the ring surface of described insulating barrier;
Wherein, described the first conductor layer and a reference planes layer are electrically connected, described the second conductor layer as signal vehicle to transmit a signal.
9. manufacture method according to claim 8, is characterized in that, described step b and described steps d by plating mode to realize.
10. manufacture method according to claim 8, is characterized in that, described step c comprises:
Fill up dielectric in the described through hole that forms described the first metal layer; And
Hole to form described insulating barrier in filling up the described through hole of described dielectric.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110347851XA CN103096613A (en) | 2011-11-07 | 2011-11-07 | Printed circuit board and manufacture method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110347851XA CN103096613A (en) | 2011-11-07 | 2011-11-07 | Printed circuit board and manufacture method thereof |
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| CN103096613A true CN103096613A (en) | 2013-05-08 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201110347851XA Pending CN103096613A (en) | 2011-11-07 | 2011-11-07 | Printed circuit board and manufacture method thereof |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103442513A (en) * | 2013-05-27 | 2013-12-11 | 浪潮集团有限公司 | Method for achieving continuous characteristic impedance of high-frequency lines |
| CN104023474A (en) * | 2014-06-24 | 2014-09-03 | 浪潮电子信息产业股份有限公司 | Method for alleviating influence of impedance mutation on signal transmission line quality |
| CN104470203A (en) * | 2013-09-25 | 2015-03-25 | 深南电路有限公司 | HDI circuit board and interlayer interconnection structure and machining method thereof |
| CN104582236A (en) * | 2013-10-17 | 2015-04-29 | 北大方正集团有限公司 | PCB (printed circuit board) and manufacturing method |
| CN104636525A (en) * | 2013-11-14 | 2015-05-20 | 英业达科技有限公司 | Checking method and device of printing circuit |
| CN107041073A (en) * | 2017-05-27 | 2017-08-11 | 郑州云海信息技术有限公司 | A kind of wiring method for reducing high speed signal crosstalk |
| CN108445299A (en) * | 2018-03-16 | 2018-08-24 | 生益电子股份有限公司 | A kind of insertion loss test-strips |
| CN109246926A (en) * | 2017-07-10 | 2019-01-18 | 中兴通讯股份有限公司 | A kind of PCB distribution method and device |
| WO2023000464A1 (en) * | 2021-07-20 | 2023-01-26 | 长鑫存储技术有限公司 | Semiconductor structure |
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| US20040070957A1 (en) * | 2002-10-10 | 2004-04-15 | Ronald Martin | Board impedance management |
| CN1913744A (en) * | 2005-08-12 | 2007-02-14 | 鸿富锦精密工业（深圳）有限公司 | Printed circuit board with improved hole |
| US20080314631A1 (en) * | 2007-01-10 | 2008-12-25 | Hsu Hsiuan-Ju | Novel via structure for improving signal integrity |
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Patent Citations (3)
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| US20040070957A1 (en) * | 2002-10-10 | 2004-04-15 | Ronald Martin | Board impedance management |
| CN1913744A (en) * | 2005-08-12 | 2007-02-14 | 鸿富锦精密工业（深圳）有限公司 | Printed circuit board with improved hole |
| US20080314631A1 (en) * | 2007-01-10 | 2008-12-25 | Hsu Hsiuan-Ju | Novel via structure for improving signal integrity |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103442513A (en) * | 2013-05-27 | 2013-12-11 | 浪潮集团有限公司 | Method for achieving continuous characteristic impedance of high-frequency lines |
| CN104470203A (en) * | 2013-09-25 | 2015-03-25 | 深南电路有限公司 | HDI circuit board and interlayer interconnection structure and machining method thereof |
| CN104582236A (en) * | 2013-10-17 | 2015-04-29 | 北大方正集团有限公司 | PCB (printed circuit board) and manufacturing method |
| CN104582236B (en) * | 2013-10-17 | 2019-03-12 | 北大方正集团有限公司 | A kind of printing board PCB and production method |
| CN104636525A (en) * | 2013-11-14 | 2015-05-20 | 英业达科技有限公司 | Checking method and device of printing circuit |
| CN104636525B (en) * | 2013-11-14 | 2017-12-19 | 英业达科技有限公司 | Printed circuit inspection method and device |
| CN104023474A (en) * | 2014-06-24 | 2014-09-03 | 浪潮电子信息产业股份有限公司 | Method for alleviating influence of impedance mutation on signal transmission line quality |
| CN107041073A (en) * | 2017-05-27 | 2017-08-11 | 郑州云海信息技术有限公司 | A kind of wiring method for reducing high speed signal crosstalk |
| CN109246926A (en) * | 2017-07-10 | 2019-01-18 | 中兴通讯股份有限公司 | A kind of PCB distribution method and device |
| CN108445299A (en) * | 2018-03-16 | 2018-08-24 | 生益电子股份有限公司 | A kind of insertion loss test-strips |
| WO2023000464A1 (en) * | 2021-07-20 | 2023-01-26 | 长鑫存储技术有限公司 | Semiconductor structure |
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Application publication date: 20130508 |