CN103077749A - Redundant fault-tolerant built-in self-repairing method suitable for static stage random access memory - Google Patents
Redundant fault-tolerant built-in self-repairing method suitable for static stage random access memory Download PDFInfo
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Abstract
The invention provides a redundant fault-tolerant built-in self-repairing method suitable for static stage random access memory, the method provides an improvement to traditional built-in self-repairing arithmetic, a redundant test module and a lapse redundant address screening module are added, and the defect that in the traditional built-in self-repairing arithmetic, when the redundant address lapses, the reparation cannot be rightly performed is solved. Firstly, redundant test module tests the redundant address, if the tested redundant address is invalid, the invalidation flag bit is 1 and the acquiescence is 0. When the redundant test finishes; and every redundant address gets the invalidation flag bit. At the moment, an invalid redundant address screening module works and analyzes the redundant addresses; if the redundant address invalidation flag bit is 0, the redundant address is write in an effective redundant address register, otherwise, the redundant address is screened and not to be written. Through the screening of the invalid redundant addresses, all replaced redundant addresses are guaranteed to be valid when the self-repairing addresses are replaced.
Description
[technical field]
The present invention relates to the built-in selfreparing algorithm field of storer, particularly a kind of built-in self-repair method of redundancy fault-tolerant that is applicable to static RAM.
[background technology]
Embedded static RAM (SRAM) is owing to its high speed performance is widely used among the SOC.According to International Technology Roadmap for Semiconductors (ITRS) prediction, embedded SRAM area occupied ratio will constantly become greatly in the SOC system, will rise to 94% by 2014.
Owing to reasons such as defective workmanships, cause the yield of SRAM to reduce.The built-in selfreparing of SRAM (BISR) is a kind of effective restorative procedure.The self-repair function of BISR is by the main address of the part of SRAM is used as redundant address, and when main address failure, BISR realizes with redundant address replacement fail address.Traditional BI SR directly tests main address, if lost efficacy in main address, namely replaces to reach the purpose of reparation by redundant address.Yet, when itself occurring losing efficacy, by the address of making a mistake of routine is replaced with redundant address, can not repair inefficacy when redundant, because the redundant address that is replaced, remain inefficacy.Therefore, there is defective in traditional built-in selfreparing algorithm, is limited to the Yield lmproved of SRAM.
Therefore, designing a kind of built-in selfreparing algorithm that redundancy is had fault tolerance, to improving the yield of embedded SRAM, is very significant.
[summary of the invention]
The object of the invention is to propose a kind of built-in self-repair method of redundancy fault-tolerant that is applicable to static RAM, to solve the problems of the technologies described above.The inventive method has proposed improvement to traditional built-in selfreparing algorithm, has added redundancy testing module and inefficacy redundant address shroud module, has solved traditional built-in selfreparing algorithm when redundant address lost efficacy, the defective that can't correctly repair.
To achieve these goals, the present invention adopts following technical scheme:
A kind of built-in self-repair method of redundancy fault-tolerant that is applicable to static RAM may further comprise the steps:
1), at first, carries out reset operation, to all initialization of register in the built-in selfreparing algorithm of SRAM;
2), enter redundancy testing, to SRAM redundant address execution March C-algorithm; Obtain redundant address inefficacy zone bit.
3), analyze the inefficacy zone bit of redundant address, the redundant address that shielding was lost efficacy is stored effective redundant address.
The present invention further improves and is:
4), lead test, to SRAM master address execution March C-algorithm; In main test, the main address of inefficacy that storage detects, and counting; Do not lose efficacy, then finished test; Inefficacy is arranged, and overflow, then finish test; Inefficacy is arranged, but do not overflow, then enter and repair and test;
5), in reparation and test, with the main address of replacement inefficacy, active redundancy address, again to March C-algorithm of main address execution; If wrong, then to point out wrongly, test finishes; If there is not mistake, then prompting does not have mistake, and test finishes.
The present invention further improves and is: step 2) specifically may further comprise the steps: the SRAM redundant address is carried out March C-algorithm, each redundant address is tested, judged according to test result whether it lost efficacy, if lost efficacy, then the inefficacy mark position with this address is 1, otherwise is set to 0; Then, judge whether March C-algorithm finishes, if finish, then redundancy testing finishes, otherwise, jump to next address, next address is tested, until March C-algorithm finishes.
The present invention further improves and is: step 3) specifically may further comprise the steps: whether judge current redundant address less than the redundant address degree of depth, if be not less than, then with inefficacy redundant address shielding complement mark position 1, the shielding of inefficacy redundant address finishes; Otherwise whether with inefficacy redundant address shielding complement mark position 0, and to detect this redundant address inefficacy zone bit be 0, if 0, then this redundant address being deposited in the active redundancy address register, active redundancy allocation index i adds 1, and redundant address adds 1; If this redundant address inefficacy zone bit is 1, then redundant address directly adds 1; No matter whether current redundant address lost efficacy, and all entered the analysis to next redundant address, until after all redundant address analyses are finished, finish.
The present invention further improves and is: in the step 3) redundant address analyzed, if this redundant address inefficacy zone bit is 0, then this redundant address deposited in the active redundancy address register, otherwise, it is masked, do not deposit in.
With respect to prior art, the present invention has the following advantages: the invention provides a kind of built-in self-repair method of redundancy fault-tolerant that is applicable to static RAM, the method has proposed improvement to traditional built-in selfreparing algorithm, redundancy testing module and inefficacy redundant address shroud module have been added, solved traditional built-in selfreparing algorithm when redundant address lost efficacy, the defective that can't correctly repair.The redundancy testing module to the redundant address test, if tested redundant address lost efficacy, is 1 with its inefficacy mark position then first, is defaulted as 0.When treating that redundancy testing finishes, each redundant address obtains its inefficacy zone bit.The redundant address shroud module work of losing efficacy this moment is analyzed redundant address, if this redundant address inefficacy zone bit is 0, then this redundant address deposited in the active redundancy address register, otherwise, it is masked, do not deposit in.After the redundant address that lost efficacy was shielded, in the time of just can guaranteeing that the selfreparing address is replaced, each redundant address that is replaced was effective.
[description of drawings]
Fig. 1 is the example flow chart according to a built-in self-repair method of redundancy fault-tolerant of the invention process.
Fig. 2 is the process flow diagram of redundancy testing.
Fig. 3 is the process flow diagram of inefficacy redundant address shielding.
Fig. 4 is the hard-wired block diagram of example illustrated.
Fig. 5 is the hard-wired limited free state machine of example illustrated.
[embodiment]
Below in conjunction with accompanying drawing embodiments of the present invention are described further.
See also shown in Figure 1ly, Fig. 1 is according to the built-in self-repair method example of a redundancy fault-tolerant of the invention process.The inventive method may further comprise the steps:
1), at first, carries out reset operation, to all initialization of register in the built-in selfreparing algorithm of SRAM;
2), then, enter redundancy testing, the redundancy testing module is carried out March C-algorithm to the SRAM redundant address.In redundancy testing, obtain redundant address inefficacy zone bit.
3), then, enter the shielding of inefficacy redundant address, inefficacy redundant address shroud module is by analyzing the inefficacy zone bit of redundant address, and the redundant address that shielding was lost efficacy is stored effective redundant address.
4), then, enter main test, main test module is carried out March C-algorithm to SRAM master address.In main test, the main address of inefficacy that storage detects, and counting.Do not lose efficacy, then finished test.Inefficacy is arranged, and overflow, then finish test.Inefficacy is arranged, but do not overflow, then enter and repair and test.
5), repair and test in, repair with test module and replace the main address of losing efficacy with the active redundancy address, again a March C-algorithm is carried out in main address.If wrong, then to point out wrongly, test finishes.If there is not mistake, then prompting does not have mistake, and test finishes.
See also shown in Figure 2ly, Fig. 2 is the process flow diagram of redundancy testing.Concrete steps are as follows: at first, carry out reset operation, to all initialization of register, algorithm begins.Then, the SRAM redundant address is carried out the MarchC-algorithm, each redundant address is tested, judge according to test result whether it lost efficacy, if lost efficacy, then the inefficacy mark position with this address is 1, otherwise is set to 0.Then, judge whether March C-algorithm finishes, if finish, then redundancy testing finishes, otherwise, jump to next address, next address is tested, until March C-algorithm finishes.When redundancy testing finished, each redundant address all obtained one zone bit, for next step inefficacy redundant address shields ready.
See also shown in Figure 3ly, Fig. 3 is the process flow diagram of inefficacy redundant address shielding.Concrete steps are as follows, at first, carry out reset operation, and to all initialization of register, algorithm begins.Then, whether judge current redundant address less than the redundant address degree of depth, if be not less than, then with inefficacy redundant address shielding complement mark position 1, the shielding of inefficacy redundant address finishes; Otherwise, with inefficacy redundant address shielding complement mark position 0, whether and to detect this redundant address inefficacy zone bit be 0, if 0, then this redundant address is deposited in the active redundancy address register, active redundancy allocation index i(is 0 when resetting) add 1, redundant address (being 0 when resetting) adds 1; If this redundant address inefficacy zone bit is 1, then redundant address directly adds 1.No matter whether current redundant address lost efficacy, and all entered the analysis to next redundant address, until after all redundant address analyses are finished, finish.
See also shown in Figure 4ly, Fig. 4 is the hard-wired block diagram of example illustrated.BISR represents the hardware of the built-in self-repair method of redundancy fault-tolerant among the figure, and SRAM represents static RAM to be measured.The direction of arrow represents data flow.BISR is by redundancy testing, the shielding of inefficacy redundant address, main test, limited free state machine, and built-in adress analysis and 3 selects 1 selector switch to form.The input signal of BISR comprises test signal test_h, reset signal rst_l, repair signal bisr_h, clock signal clk, the original chip selection signal cen_0 of SRAM, original enable signal wen_0, original address signal a_0, original data d_0, the read data q of writing of writing; Output signal comprises test settling signal test_done, spill over over_h, disablement signal fail_h, SRAM chip selection signal cen, writes enable signal wen, address signal a and write data d.The redundancy testing input comprises SRAM read data q, test_phase, test_h, rst_l, clk; It provides redundant address inefficacy zone bit redun_a_flag for the shielding of inefficacy redundant address, for limited free state machine provides redundancy testing end mark position test_redun_done, select 1 selector switch to provide redundant chip selection signal cen_redun, redundancy to write enable signal wen_redun, redundant address signal a_redun, redundant data signal d_redun for 3.Inefficacy redundant address shielding input comprises SRAM read data q, test_phase, test_h, rst_l, clk; It provides effective redundant address quantity ava_redun_a_num, inefficacy redundant address shielding complement mark position def_redun_a_mask_done for limited free state machine, for built-in adress analysis provides effective redundant address.Main test input comprises test_phase, test_h, rst_l, clk; It finishes zone bit test_main_done, main test failure zone bit fail_h_main, recovery test complement mark position test_repair_done, recovery test inefficacy zone bit fail_h_repair and the main number of addresses def_main_a_num that lost efficacy for limited free state machine provides main test; For built-in adress analysis provides the main address def_main_a that lost efficacy; Select 1 selector switch to provide main leaf to select signal cen_main, the main enable signal wen_main that writes for 3, main redundant address a_main and the main data d_main that writes.Limited free state machine input comprises test_h, rst_l, clk, bisr_h, test_redun_done, ava_redun_a_num, def_redun_a_mask_done, test_main_done, fail_h_main, test_repair_done, fail_h repair, def_main_a_num; For other five modules provide test_phase, be whole BISR output over_h, fail_h and test_done.3 select the input of 1 selector switch to comprise bisr_h, test_phase, cen_0, wen_0, a_0, d_0, cen_redun, wen_redun, a_redun, d_redun, cen_main, wen_main, a_main, d_main; It provides built-in selfreparing address bisr_a for built-in adress analysis; For SRAM provides cen, wen, d.Built-in adress analysis input comprises test_h, rst_l, clk, bisr_h, test_phase, ava_redun_a, def_main_a, bisr_a; For SRAM provides address a.The BISR principle of work describes in detail in connection with Fig. 5.
See also shown in Figure 5ly, Fig. 5 is the hard-wired limited free state machine of example illustrated.The hard-wired principle of work of built-in self-repair method of describing redundancy fault-tolerant in conjunction with Fig. 4 in detail is as follows.When reset signal rst_l=0, all states are jumped and all will be forwarded " test beginning test_start " state to, and " test beginning " state is the reset mode of this state machine.When " test beginning " state, if test signal test_h=1, then the next state of test_phase is " redundancy testing " test_redun state.
In " redundancy testing " state, the SRAM redundant address is carried out March C-algorithm.Its principle is as follows, and redundancy testing produces cen_redun, wen_redun, a_redun, d_redun; 3 select 1 selector switch to detect current test_phase=test_redun, cen_redun, wen_redun, d_redun gating are inputted cen, wen, d to SRAM, a_redun is exported to built-in adress analysis input bisr_a, and built-in adress analysis is directly given bisr_a SRAM input a.SRAM feeds back to redundancy testing with read data q, if q is identical with desired value, then this redundant address is effective, otherwise loses efficacy, and is 0 when the inefficacy zone bit redun_a_flag that this redundant address is corresponding is labeled as 1(and resets).After executing the March C-algorithm to redundant address, be 0 when redundancy testing complement mark position test_redun_done is set to 1(and resets).In " redundancy testing " state, if test_h=1 and test_redun_done=1, then the NextState of test_phase is " shielding of inefficacy redundant address " def_redun_a_mask state.
In " shielding of inefficacy redundant address " state, each redundant address is analyzed, if its inefficacy zone bit is 0, then it is deposited among the active redundancy address register ava_redun_a, and active redundancy number of addresses ava_redun_a_num is added 1; If its inefficacy zone bit is 1, then this redundant address is discarded, do not deposit among the ava_redun_a.After the analysis of finishing all redundant address, be 0 when inefficacy redundant address shielding complement mark position def_redun_a_mask_done is set to 1(and resets).In " shielding of inefficacy redundant address " state, if test_h=1 and def_redun_a_mak_done=1, then the NextState of test_phase is " main test " test_main state.
In " main test " state, March C-algorithm is carried out in SRAM master address.Its principle is as follows, main test generation cen_main, wen_main, a_main, d_main; 3 select 1 selector switch to detect current test_phase=test_main, cen_main, wen_main, d_main gating are inputted cen, wen, d to SRAM, a_main is exported to built-in adress analysis input bisr_a, and built-in adress analysis is directly given bisr_a SRAM input a.SRAM feeds back to main test with read data q, if q is not identical with desired value, then main test was lost efficacy, be 0 when main test errors zone bit fail_h_main is set to 1(and resets), and the main address of losing efficacy deposited among the main address register def_main_a that lost efficacy, and the main number of addresses def_main_a_num that will lose efficacy adds 1.After executing the March C-algorithm to main address, be 0 in the time of will leading test and finish zone bit test_main_done and be set to 1(and reset).If the main number of addresses def_main_a_num that makes a mistake greater than active redundancy number of addresses ava_redun_a_num, then is set to 1(with Overflow flag over_h when resetting is 0).
In " main test " state, if test_h=1 and test_main_done=1, and fail_h_main=0, fail_h=0 then, test_done=0, the main test of expression is finished, and does not have mistake, and then the NextState of test_phase is " test is finished " state.In " main test " state, if test_h=1 and test_main_done=1, and fail_h_main=1, and over_h=1, the main test of expression is finished, and the main number of addresses of inefficacy is overflowed greater than the quantity of active redundancy address, unrepairable, then the NextState of test_phase is " test is finished " state.In " main test " state, if test_h=1 and tst_main_done=1, and fail_h_main=1 and over_h=0, and bisr_h=1, the main test of expression is finished, and is wrong, but the main number of addresses that lost efficacy is less than the quantity of active redundancy address, can repair, and repair, then the NextState of test_phase is " repairing and test " test_repair state.
In " repairing and test " state, SRAM master address is repaired (if necessary) and carried out March C-algorithm.Its principle is as follows, main test generation cen_main, wen_main, a_main, d_main; 3 select 1 selector switch to detect current test_phase=test_repair, and cen_main, wen_main, d_main gating are inputted cen, wen, d to SRAM, and a_main is exported to built-in adress analysis input bisr_a.Built-in adress analysis measures current test_phase=test_repair, each address in bisr_a and the def_main_a register is compared, if hit, then with giving SRAM input a behind the replacement bisr_a in active redundancy address among the ava_redun_a; If do not hit, directly bisr_a is given SRAM input a.SRAM feeds back to main test with read data q, if q is not identical with desired value, then repairs and tests and lost efficacy, and will repair when being set to 1(and resetting with test errors zone bit fail_h_repair is 0).Execute after the reparation of main address and the test, will repair and test is 0 when finishing state flag bit test_repair_done and being set to 1(and resetting).
In " repairing and test " state, if test_h=1 and test_repair_done=1 and fail_h_repair=0, then fail_h=0, test_done=0, expression is repaired successfully, and prompting is repaired successfully, reparation is finished, and then the NextState of test_phase is " test is finished " state; If test_h=1 and test_repair_done=1 and fail_h_repair=1, fail_h=1 then, test_done=0 represents repairing failure, the prompting repairing failure, reparation is finished, and then the NextState of test_phase is " test is finished " state.
At " test is finished " state, if rst_l=0, then the NextState of test_phase is " test beginning test_start " state.
Claims (5)
1. the built-in self-repair method of redundancy fault-tolerant that is applicable to static RAM is characterized in that, may further comprise the steps:
1), at first, carries out reset operation, to all initialization of register in the built-in selfreparing algorithm of SRAM;
2), enter redundancy testing, to SRAM redundant address execution March C-algorithm; Obtain redundant address inefficacy zone bit;
3), analyze the inefficacy zone bit of redundant address, the redundant address that shielding was lost efficacy is stored effective redundant address.
2. a kind of built-in self-repair method of redundancy fault-tolerant that is applicable to static RAM as claimed in claim 1 is characterized in that, described method is further comprising the steps of:
4), lead test, to SRAM master address execution March C-algorithm; In main test, the main address of inefficacy that storage detects, and counting; Do not lose efficacy, then finished test; Inefficacy is arranged, and overflow, then finish test; Inefficacy is arranged, but do not overflow, then enter and repair and test;
5), in reparation and test, with the main address of replacement inefficacy, active redundancy address, again to March C-algorithm of main address execution; If wrong, then to point out wrongly, test finishes; If there is not mistake, then prompting does not have mistake, and test finishes.
3. a kind of built-in self-repair method of redundancy fault-tolerant that is applicable to static RAM as claimed in claim 1, it is characterized in that, step 2) specifically may further comprise the steps: the SRAM redundant address is carried out the MarchC-algorithm, each redundant address is tested, judge according to test result whether it lost efficacy, if lost efficacy, then the inefficacy mark position with this address is 1, otherwise is set to 0; Then, judge whether March C-algorithm finishes, if finish, then redundancy testing finishes, otherwise, jump to next address, next address is tested, until March C-algorithm finishes.
4. a kind of built-in self-repair method of redundancy fault-tolerant that is applicable to static RAM as claimed in claim 1, it is characterized in that, step 3) specifically may further comprise the steps: judge that whether current redundant address is less than the redundant address degree of depth, if be not less than, then with inefficacy redundant address shielding complement mark position 1, the shielding of inefficacy redundant address finishes; Otherwise whether with inefficacy redundant address shielding complement mark position 0, and to detect this redundant address inefficacy zone bit be 0, if 0, then this redundant address being deposited in the active redundancy address register, active redundancy allocation index i adds 1, and redundant address adds 1; If this redundant address inefficacy zone bit is 1, then redundant address directly adds 1; No matter whether current redundant address lost efficacy, and all entered the analysis to next redundant address, until after all redundant address analyses are finished, finish.
5. a kind of built-in self-repair method of redundancy fault-tolerant that is applicable to static RAM as claimed in claim 1, it is characterized in that, in the step 3) redundant address is analyzed, if this redundant address inefficacy zone bit is 0, then this redundant address is deposited in the active redundancy address register, otherwise, it is masked, do not deposit in.
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| CN116612805A (en) * | 2023-07-19 | 2023-08-18 | 芯天下技术股份有限公司 | Redundancy replacement method and device for flash, register and memory chip |
| US11776654B2 (en) | 2020-09-11 | 2023-10-03 | Changxin Memory Technologies, Inc. | Fail bit repair solution determination method and device |
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| US11776654B2 (en) | 2020-09-11 | 2023-10-03 | Changxin Memory Technologies, Inc. | Fail bit repair solution determination method and device |
| CN116612805A (en) * | 2023-07-19 | 2023-08-18 | 芯天下技术股份有限公司 | Redundancy replacement method and device for flash, register and memory chip |
| CN116612805B (en) * | 2023-07-19 | 2023-11-10 | 芯天下技术股份有限公司 | Redundancy replacement method and device for flash, register and memory chip |
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Application publication date: 20130501 |