CN102736289B - Display panel - Google Patents
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- CN102736289B CN102736289B CN201110091857.5A CN201110091857A CN102736289B CN 102736289 B CN102736289 B CN 102736289B CN 201110091857 A CN201110091857 A CN 201110091857A CN 102736289 B CN102736289 B CN 102736289B
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- substrate
- display panel
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- conductive layer
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Abstract
The invention discloses a display panel, comprising a first base substrate, a pixel array, a peripheral circuit, a second substrate, frame glue and a display medium, wherein the second substrate is arranged above the first substrate. The first substrate is provided with a first display region and a periphery region. The pixel array is arranged in the display region. The peripheral circuit is arranged in the peripheral region and electrically connected with the pixel array. The peripheral circuit comprises an inside conductor, an outside conductor and a transmission conductive layer. The inside conductor is electrically connected with the pixel array. The outside conductor is arranged around the periphery of the inside conductor. The transmission conductive layer is electrically connected with inside conductor and the outside conductor. The outside conductor is electrically connected with the pixel array through the transmission conductive layer and the inside conductor. The frame glue and the display medium are arranged between the first substrate and the second substrate. The frame glue is arranged on partial peripheral circuit and surrounds the pixel array. The display medium is surrounded by the frame glue.
Description
Technical field
The invention relates to a kind of display device, and relate to especially a kind of display panel.
Background technology
In many flat-panel screens, have that high image quality, space utilization efficiency are good, Thin Film Transistor-LCD (the Thin Film Transistor Liquid Crystal Display of low consumpting power, the advantageous characteristic such as radiationless, TFT LCD), become the main flow in field of display.Thin Film Transistor-LCD is made up of active assembly array substrate, colored optical filtering substrates and the liquid crystal layer that is sandwiched between this two substrates.
Complete after the processing procedure of active assembly array substrate; conventionally can carry out electrical detection to the pel array on active assembly array substrate; or complete after panel processing procedure, the counter plate detection of lighting a lamp easily, to judge that pel array or panel could normal operations.In the time that pel array or panel cannot normal operations, just can repair for bad assembly (as thin film transistor (TFT) or pixel electrode etc.) or circuit.But, in order to detect for pel array or panel, on the surrounding zone of active assembly array substrate, just need to produce testing circuit (Examining circuit).In addition, also need to produce common electric voltage signal wire in the perimeter circuit district of active assembly array substrate, it is for inputing to common electric voltage on the common electrode layer of colored optical filtering substrates.If configuration detection circuit in face, common electrode wiring region is by compressed.If while adopting the mode of cross-line to configure common electrode layer, can additionally increase the resistance capacitance load (RC loading) of common electric voltage.But in the time of the deficiency of the wiring region of common electric voltage signal wire, the common electric voltage that inputs to the common electrode layer of colored optical filtering substrates just may be not enough, and then affect the display quality of display.
Summary of the invention
The invention provides a kind of display panel with better display quality.
The invention provides a kind of display panel, it comprises a first substrate, a pel array, a perimeter circuit, a second substrate, a frame glue and a display medium.First substrate has a viewing area and a neighboring area around viewing area.Pixel array configuration is in the viewing area of first substrate.Perimeter circuit is disposed in the neighboring area of first substrate, and is electrically connected with pel array.Perimeter circuit comprises an inside conductor, an outer conductor and a transmission conductive layer.Inside conductor and pel array are electrically connected.Outer conductor is around the periphery configure of inside conductor.Transmission conductive layer is electrically connected inside conductor and outer conductor.Outer conductor is electrically connected with pel array by transmission conductive layer, inside conductor.Second substrate is disposed at the top of first substrate.Frame glue is disposed between first substrate and second substrate, and frame glue is positioned on part perimeter circuit and ring pixel array.Display medium between first substrate and second substrate, and by frame glue institute around.
In one embodiment of this invention, above-mentioned frame glue comprises colloid and multiple conductive gap thing being distributed in colloid.Second substrate has a shared electrode layer thereon.Transmission conductive layer sees through conductive gap thing and is electrically connected with shared electrode layer.
In one embodiment of this invention, the material of above-mentioned conductive gap thing comprises metal.
In one embodiment of this invention, above-mentioned transmission conductive layer has an opening, between inside conductor and outer conductor.Outer conductor sequentially sees through transmission conductive layer, conductive gap thing, shared electrode layer, conductive gap thing, transmission conductive layer and is electrically connected with inside conductor.
In one embodiment of this invention, above-mentioned transmission conductive layer is a continuous rete.
In one embodiment of this invention, above-mentioned pel array comprises pixel cell and many signal line of multiple arrayed.Signal wire and pixel cell are electrically connected.Inside conductor is connected with segment signal line, and inside conductor, outer conductor and signal wire belong to same rete.
In one embodiment of this invention, above-mentioned display panel also comprises at least one driving chip, is disposed in the neighboring area of first substrate, and wherein signal wire, inside conductor and driving chip are electrically connected.
In one embodiment of this invention, above-mentioned display panel also comprises a flexible circuit board, is disposed in the neighboring area of first substrate, and is electrically connected with outer conductor and driving chip.
In one embodiment of this invention, the material of above-mentioned transmission conductive layer comprises indium tin oxide (indium tin oxide, ITO) or indium-zinc oxide (indium zinc oxide, IZO).
In one embodiment of this invention, above-mentioned first substrate is an active assembly array substrate, and second substrate is a colored optical filtering substrates.
Based on above-mentioned, the design of display panel of the present invention is that the inside conductor of perimeter circuit and pel array are electrically connected, and the outer conductor of perimeter circuit is electrically connected with pel array by transmission conductive layer, inside conductor, therefore can stablize the common electric voltage in viewing area.In other words, compared to known technology, display panel of the present invention can have larger wiring region, and can additionally not increase the resistance capacitance load (RC loading) of common electric voltage, and then has preferably display quality.
For above-mentioned feature and advantage of the present invention can be become apparent, special embodiment below, and coordinate appended graphic being described in detail below.
Brief description of the drawings
Figure 1A is the schematic diagram of a kind of display panel of one embodiment of the invention.
Figure 1B is the schematic top plan view of the display panel of Figure 1A.
Fig. 1 C is the diagrammatic cross-section along the line I-I of Figure 1B.
Fig. 2 A is the schematic top plan view of a kind of display panel of another embodiment of the present invention.
Fig. 2 B is the diagrammatic cross-section along the line II-II of Fig. 2 A.
Embodiment
Figure 1A is the schematic diagram of a kind of display panel of one embodiment of the invention.Figure 1B is the schematic top plan view of the display panel of Figure 1A.Fig. 1 C is the diagrammatic cross-section along the line I-I of Figure 1B.Should be noted that at this, for convenience of description for the purpose of, in Figure 1B, omit and illustrate second substrate and partial component.Please also refer to Figure 1A, Figure 1B and Fig. 1 C, in the present embodiment, display panel 100a comprises a first substrate 110, a pel array 120, a perimeter circuit 130a, a second substrate 140, a frame glue 150 and a display medium 160.
Specifically, first substrate 110, for example, be a driving component (as thin film transistor (TFT) (Thin Film Transistor, TFT)) array base palte, and it has a viewing area 112 and a neighboring area 114 around viewing area 112.Pel array 120 is disposed in the viewing area 112 of first substrate 110, wherein pel array 120 comprises pixel cell 122 and many signal line (comprising data line 124a and gate line 113) of multiple arrayed, and these data lines 124a, these gate lines 113 and pixel cell 122 are electrically connected.In the present embodiment, each pixel cell 122 comprises the pixel electrode 125 of a thin film transistor (TFT) 123 and setting corresponding to thin film transistor (TFT) 123, wherein thin film transistor (TFT) 123 is made up of grid 123a, source electrode 123b and drain electrode 123c tri-parts, in affiliated technical field, have and conventionally know that the knowledgeable should know the structure of thin film transistor (TFT) 123 bottom-gate (bottom gate) or the structure of top grid (top gate), only deliberately do not limit in order to explanation at this.
Perimeter circuit 130a is disposed in the neighboring area 114 of first substrate 110, and perimeter circuit 130a and pel array 120 are electrically connected.The perimeter circuit 130a of the present embodiment comprises an inside conductor 132, an outer conductor 134 and a transmission conductive layer 136a, wherein inside conductor 132 is electrically connected with pel array 120, outer conductor 134 is around the periphery configure of inside conductor 132, and transmission conductive layer 136a is electrically connected inside conductor 132 and outer conductor 134.Particularly, in the present embodiment, outer conductor 134 can be electrically connected with pel array 120 by transmission conductive layer 136a, inside conductor 132.In this, transmission conductive layer 136a is for example a continuous rete, and inside conductor 132 is connected with segment data line 124a, part of grid pole line 113 and common electrode wire 118, and inside conductor 132, outer conductor 134 and data line 124a belong to same rete.In addition, the material of transmission conductive layer 136a comprises indium tin oxide or indium-zinc oxide.
More particularly; on first substrate 110, also there is these gate lines 113, a lock insulation course 115 and a protective seam 117; wherein lock insulation course 115 covers these gate lines 113; and inside conductor 132 is positioned on lock insulation course 115 with outer conductor 134, and inside conductor 132, outer conductor 134 see through lock insulation course 115 and are electrically insulated with these gate lines 113.In addition, protective seam 117 have in multiple opening 117a(Fig. 1 C only schematically illustrate two), wherein transmit that conductive layer 136a sees through opening 117a and inside conductor 132 and outer conductor 134 is electrically connected.
Second substrate 140, for example, be a colored optical filtering substrates, is disposed at the top of first substrate 110, and meaning is disposed at the subtend of active assembly array substrate 110.Generally speaking, on colored optical filtering substrates, mainly comprise a black matrix layer (black matrix, BM) (do not illustrate), a color filter film (not illustrating) and a shared electrode layer 142 etc., wherein black matrix layer is as light shield layer (light shield layer) use, and black matrix layer must have good shaded effect and the characteristic of low reflection.
Frame glue 150 is disposed between first substrate 110 and second substrate 140, and frame glue 150 is positioned at the upper also ring pixel array 120 of part perimeter circuit 130a.In the present embodiment, frame glue 150 comprises colloid 152 and multiple conductive gap thing 154 being distributed in colloid 152, wherein transmits conductive layer 136a and can see through these conductive gap things 154 and be electrically connected with the shared electrode layer 142 of second substrate 140.The transmission conductive layer 136a that thus, can make to be positioned on first substrate 110 is electrically connected and has identical common electric voltage with the shared electrode layer 142 being positioned on second substrate 140.In addition the macromolecular material that, the material of these conductive gap things 154 is comprehensive covered with metal layer.
Display medium 160 between first substrate 110 and second substrate 140, and by 150, frame glue around.Should be noted that at this, the present invention does not limit the kenel of display panel 100a, and wherein, along with the difference of display medium 160, display panel 100a has different mechanism of action.For example, display medium 160 can be liquid crystal material, and display panel 100a is display panels.
In addition, the display panel 100a of the present embodiment more can comprise at least one driving chip 170(Figure 1B illustrate one) an and flexible circuit board 180.Drive chip 170 to be disposed on the neighboring area 114 of first substrate 110, wherein these data lines 124a, these gate lines 113, inside conductor 132 can be electrically connected with driving chip 170 respectively.Flexible circuit board 180 is disposed in the neighboring area 114 of first substrate 110, and is electrically connected with outer conductor 134 and driving chip 170.
Because the design of the display panel 100a of the present embodiment is that the inside conductor of perimeter circuit 130a 132 and pel array 120 are electrically connected, and the outer conductor 134 of perimeter circuit 130a is electrically connected with pel array 120 by transmission conductive layer 136a, inside conductor 132, and the shared electrode layer 142 that sees through these conductive gap things 154 in frame glue 150 and electrically conduct on transmission conductive layer 136a and second substrate 140, please refer to the direction of arrow in Fig. 1 C.Thus, can stablize the common electric voltage in the viewing area 112 of display panel 100a, and can additionally not increase the resistance capacitance load (RC loading) of common electric voltage, and then make display panel 100a there is preferably display quality.Moreover owing to driving the not wiring of below of chip 170, therefore display panel 100a can have more greatly and the region of connecting up more flexibly.
To the design of display panel 100b be described with a different embodiment more below.Should be noted that at this, following embodiment continues to use assembly label and the partial content of previous embodiment, wherein adopts identical label to represent identical or approximate assembly, and has omitted the explanation of constructed content.Explanation about clipped can be with reference to previous embodiment, and it is no longer repeated for following embodiment.
Fig. 2 A is the schematic top plan view of a kind of display panel of another embodiment of the present invention.Fig. 2 B is the diagrammatic cross-section along the line II-II of Fig. 2 A.Should be noted that at this, for convenience of description for the purpose of, in Fig. 2 B, omit and illustrate second substrate and partial component.Please also refer to Fig. 2 A and Fig. 2 B, the display panel 100b of the present embodiment is similar to the display panel 100a of above-described embodiment, its difference is: the transmission conductive layer 136b of the perimeter circuit 130b in Fig. 2 A and Fig. 2 B has an opening 137, its split shed 137 is between inside conductor 132 and outer conductor 134, and outer conductor 134 can sequentially see through transmission conductive layer 136b, these conductive gap things 154, shared electrode layer 142 on second substrate 140, these conductive gap things 154, transmit conductive layer 136b and be electrically connected with inside conductor 132, please refer to the direction of arrow of Fig. 2 B.Thus, can stablize the common electric voltage in the viewing area 112 of display panel 100b, and can additionally not increase the resistance capacitance load (RC loading) of common electric voltage, and then make display panel 100b there is preferably display quality.
In sum, the design of display panel of the present invention is that the inside conductor of perimeter circuit and pel array are electrically connected, and the outer conductor of perimeter circuit is electrically connected with pel array by transmission conductive layer, inside conductor, therefore can stablize the common electric voltage in viewing area.In other words, compared to known technology, display panel of the present invention can have larger wiring region, and can additionally not increase the resistance capacitance load (RC loading) of common electric voltage, and then has preferably display quality.
Although the present invention with embodiment openly as above; so it is not in order to limit the present invention; under any, in technical field, have and conventionally know the knowledgeable; without departing from the spirit and scope of the present invention; when doing a little change and retouching, therefore protection scope of the present invention is when being as the criterion depending on the aforesaid claim scope person of defining.
Claims (9)
1. a display panel, is characterized in that, comprising:
One first substrate, has a viewing area and a neighboring area around this viewing area;
One pel array, is disposed in this viewing area of this first substrate;
One perimeter circuit, is disposed in this neighboring area of this first substrate, and is electrically connected with this pel array, and this perimeter circuit comprises:
One inside conductor, is electrically connected with this pel array;
One outer conductor, around the periphery configure of this inside conductor;
One transmission conductive layer, is electrically connected this inside conductor and this outer conductor, wherein this outer conductor by this transmission conductive layer, this inside conductor and with this pel array electric connection;
One second substrate, is disposed at the top of this first substrate;
One frame glue, be disposed between this first substrate and this second substrate, this frame glue is positioned on this perimeter circuit of part and around this pel array, and this frame glue comprises colloid and multiple conductive gap thing being distributed in this colloid, this second substrate has a shared electrode layer thereon, and this transmission conductive layer sees through those conductive gap things and is electrically connected with this shared electrode layer; And
One display medium, between this first substrate and this second substrate, and by this frame glue institute around.
2. display panel as claimed in claim 1, is characterized in that, the material of this conductive gap thing comprises metal.
3. display panel as claimed in claim 1, it is characterized in that, this transmission conductive layer has an opening, between this inside conductor and this outer conductor, this outer conductor sequentially sees through this transmission conductive layer, those conductive gap things, this shared electrode layer, those conductive gap things, this transmission conductive layer and is electrically connected with this inside conductor.
4. display panel as claimed in claim 1, is characterized in that, this transmission conductive layer is a continuous rete.
5. display panel as claimed in claim 1, is characterized in that, this pel array comprises:
The pixel cell of multiple arrayed; And
Many signal line, are electrically connected with those pixel cells, it is characterized in that, this inside conductor is connected with those signal wires of part, and this inside conductor, this outer conductor and those signal wires belong to same rete.
6. display panel as claimed in claim 5, is characterized in that, also comprises at least one driving chip, is disposed in this neighboring area of this first substrate, and wherein those signal wires, this inside conductor and this driving chip are electrically connected.
7. display panel as claimed in claim 6, is characterized in that, also comprises a flexible circuit board, is disposed in this neighboring area of this first substrate, and is electrically connected with this outer conductor and this driving chip.
8. display panel as claimed in claim 1, is characterized in that, the material of this transmission conductive layer comprises indium tin oxide or indium-zinc oxide.
9. display panel as claimed in claim 1, is characterized in that, this first substrate is an active assembly array substrate, and this second substrate is a colored optical filtering substrates.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110091857.5A CN102736289B (en) | 2011-04-13 | 2011-04-13 | Display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110091857.5A CN102736289B (en) | 2011-04-13 | 2011-04-13 | Display panel |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102736289A CN102736289A (en) | 2012-10-17 |
| CN102736289B true CN102736289B (en) | 2014-11-19 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110091857.5A Expired - Fee Related CN102736289B (en) | 2011-04-13 | 2011-04-13 | Display panel |
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Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112396981B (en) * | 2020-01-14 | 2023-10-17 | 友达光电股份有限公司 | display panel |
Citations (6)
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|---|---|---|---|---|
| EP1055960A2 (en) * | 1999-05-25 | 2000-11-29 | Sharp Kabushiki Kaisha | Liquid crystal display device |
| CN101387801A (en) * | 2007-09-10 | 2009-03-18 | 中华映管股份有限公司 | Liquid crystal display panel |
| CN101714039A (en) * | 2008-03-18 | 2010-05-26 | 友达光电股份有限公司 | Touch-control device |
| CN201556010U (en) * | 2009-12-17 | 2010-08-18 | 华映视讯（吴江）有限公司 | Liquid crystal display device |
| CN101900917A (en) * | 2010-07-12 | 2010-12-01 | 友达光电股份有限公司 | Bistable display and detection method thereof |
| CN201788340U (en) * | 2010-05-26 | 2011-04-06 | 福州华映视讯有限公司 | Active component array substrate |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3502833B2 (en) * | 2000-12-20 | 2004-03-02 | 京セラ株式会社 | Liquid crystal display device and portable terminal or display device provided with this liquid crystal display device |
| JP4096520B2 (en) * | 2001-04-26 | 2008-06-04 | カシオ計算機株式会社 | Liquid crystal display element |
| TWI250352B (en) * | 2003-09-08 | 2006-03-01 | Chunghwa Picture Tubes Ltd | Liquid crystal display panel |
-
2011
- 2011-04-13 CN CN201110091857.5A patent/CN102736289B/en not_active Expired - Fee Related
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1055960A2 (en) * | 1999-05-25 | 2000-11-29 | Sharp Kabushiki Kaisha | Liquid crystal display device |
| CN101387801A (en) * | 2007-09-10 | 2009-03-18 | 中华映管股份有限公司 | Liquid crystal display panel |
| CN101714039A (en) * | 2008-03-18 | 2010-05-26 | 友达光电股份有限公司 | Touch-control device |
| CN201556010U (en) * | 2009-12-17 | 2010-08-18 | 华映视讯（吴江）有限公司 | Liquid crystal display device |
| CN201788340U (en) * | 2010-05-26 | 2011-04-06 | 福州华映视讯有限公司 | Active component array substrate |
| CN101900917A (en) * | 2010-07-12 | 2010-12-01 | 友达光电股份有限公司 | Bistable display and detection method thereof |
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| CN102736289A (en) | 2012-10-17 |
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