CN102569251B - Intermetallic compound filled vertical through-hole interconnecting structure for three-dimensional package and preparation method thereof - Google Patents

Intermetallic compound filled vertical through-hole interconnecting structure for three-dimensional package and preparation method thereof Download PDF

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CN102569251B
CN102569251B CN201210041014.9A CN201210041014A CN102569251B CN 102569251 B CN102569251 B CN 102569251B CN 201210041014 A CN201210041014 A CN 201210041014A CN 102569251 B CN102569251 B CN 102569251B
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hole
substrate
vertical
layer
filled
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CN102569251A (en
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于大全
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National Center for Advanced Packaging Co Ltd
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National Center for Advanced Packaging Co Ltd
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Abstract

The invention relates to an intermetallic compound filled vertical through-hole interconnecting structure for three-dimensional package and a preparation method thereof. The vertical through-hole interconnecting structure comprises a substrate, wherein at least one through hole which vertically penetrates through the substrate is formed in the substrate; an insulating layer grows on the inner wall of the through hole; an intermetallic compound layer is filled in the through hole of the grown insulating layer; and an adhesion layer is arranged between the intermetallic compound layer and the insulating layer. At least one through hole which vertically penetrates through the substrate is formed in the substrate; the insulating layer grows on the inner wall of the through hole; the intermetallic compound layer is filled in the through hole; the adhesion layer is arranged between the intermetallic compound layer and the insulating layer; by the intermetallic compound layer, electric connection required in three-dimensional stacking can be finished, the vertical through-hole interconnecting structure is convenient to form and manufacture, and process complexity and manufacturing cost are reduced; and therefore, the vertical interconnecting structure can be manufactured on an integrated circuit, an adapter plate can be manufactured on a passive substrate, the yield is improved, and the vertical through-hole interconnecting structure is safe and reliable.

Description

Vertical through hole interconnection structure and preparation method that three-dimension packaging is filled with intermetallic compound
Technical field
The present invention relates to a kind of vertical interconnecting structure and preparation method, vertical through hole interconnection structure and preparation method that especially a kind of three-dimension packaging is filled with intermetallic compound, belong to microelectronics Packaging three-dimensional integration technology field.
Background technology
System in package (SiP) is one of microelectronics key technology, has met the requirement of the high-frequency high-speed of electronic device, multi-functional, high-performance, small size and high reliability, is the direction of electronic technology development.Along with integrated circuit characteristic size reaches nanoscale, transistor is to high density more, higher clock frequency development, and encapsulation is also to more highdensity future development, and integrated circuit (IC) products is also from two dimension to Three-dimensional Development.
The three-dimensional integration technology of silicon through hole (TSV) is one of key technology realizing 3D-SiP, is the new core technology with very big impact, has extremely wide application prospect; Therefore receive the very big concern of each industrial country, important enterprise and academia, also continued now to drop into ample resources and researched and developed.Silicon through hole technology has a lot of technological challenges, particularly its manufacturing process complexity, comprises silicon hole etching, insulating barrier/barrier/seed layers deposition, filling through hole, cmp, wafer bonding, tears bonding open, wafer attenuate, metal connect up making, Solder bumping etc. again.
The subject matter that TSV technology exists in application aspect is still complex process, and cost is high.For packing material and the mode of silicon through hole, roughly have several as follows: (1), plating filling perforation; (2), chemical meteorology deposition (CVD); (3), liquid solder is filled; (4), conducting resinl is filled.Utilizing and electroplate filling perforation, is mainly take copper plating as main, and its advantage is that copper has good conductivity, and shortcoming is to electroplate to need good Seed Layer to make, and electroplating time is longer, electroplating technology complexity, and cost is high; And the hole that is less than 5 microns for aperture, electroplate filling perforation and be difficult to realize.The main material of chemical vapour deposition (CVD) is tungsten, can realize the filling of small-bore through hole, and subject matter is complex process, and the filling time is long, and cost is high, and conductivity is slightly poor.Solder is filled, and is to utilize low melting point solder to fill micropore under liquid state, has fast the advantages such as low cost.(list of references Ko Y.-K., Fujii H.T., Sato Y.S., Lee C.-W., and Yoo S.Microelectron Eng 2012; 89:62-64.) but shortcoming is that solder conductivity is poor, differ larger with the CTE (Coefficient of thermal expansion, thermal coefficient of expansion) of silicon materials, bring stress problem, and solder fusing point is low, in subsequent technique processing procedure process, can bring a lot of problems.Utilize conducting resinl to fill, also can simplify fill process, but conductivity is very poor, be difficult to fill the hole that diameter is less.
Summary of the invention
The object of the invention is to overcome the deficiencies in the prior art, the vertical through hole interconnection structure and the preparation method that provide a kind of three-dimension packaging intermetallic compound to fill, it can effectively reduce cost of manufacture, simplifies processing step, improves qualification rate, safe and reliable.
According to technical scheme provided by the invention, the vertical through hole interconnection structure that described three-dimension packaging is filled with intermetallic compound, comprises substrate, is provided with at least one vertical through hole that penetrates substrate that connects in described substrate; In described through hole, filled by the continuous intermetallic compound of vertical direction, between described intermetallic compounds layer and substrate, be provided with adhesion layer.
Described substrate and adhesion layer comprise insulating barrier, and adhesion layer adheres on the inwall of through hole by insulating barrier.
Between described intermetallic compounds layer and adhesion layer, also comprise residual metal layer, intermetallic compounds layer is connected with adhesion layer by residual metal layer.
Described intermetallic compounds layer forms by the high-temperature metal layer and the thermal diffusion of low melting point solder obturator that are filled in through hole.
Described high-temperature metal layer is one or more of material in Cu, Ni, Ag, Pd, Au or Fe; Low melting point solder obturator is one or more of material in Sn, In, SnAg, SnIn, SnBi, SnPb, SnAgCu, InAg, InSn.
Described intermetallic compounds layer is one or more in Cu-Sn, Ni-Sn, Cn-In, Ni-In, Ag-Sn, Au-Sn, Ag-In, Au-In etc.
In described intermetallic compounds layer, comprise high-temperature metal phase, the fusing point of high-temperature metal phase is higher than 300 degree.
The material of described insulating barrier is SiO 2, Si xn 1-xin one or more.
The vertical through hole interconnection structure preparation method that three-dimension packaging is filled with intermetallic compound, described vertical interconnecting structure preparation method comprises the steps:
A, provide substrate, and in substrate, form required vertical perforation and penetrate the through hole of substrate;
B, on the surface of above-mentioned substrate deposit adhesion layer, described adhesion layer is covered in the surface of substrate and is covered in the inner wall surface of through hole;
C, arrange on the surface of above-mentioned substrate and the high-temperature metal layer of insulated substrate, described high-temperature metal layer covers the surface of substrate and is covered in the surface of corresponding adhesion layer in through hole;
D, in above-mentioned through hole, fill low melting point solder, to form low melting point solder obturator in through hole;
E, smoothening substrate surface to above-mentioned formation low melting point solder obturator, the surface that polished substrate is corresponding, to make the low melting point solder obturator in through hole concordant with the surface of polishing back substrate;
F, at required temperature, low melting point solder obturator and high-temperature metal layer are carried out to heat diffusion treatment, until low melting point solder obturator all melt after with high-temperature metal layer formation intermetallic compounds layer.
In described steps d, by substrate being inserted to the low melting point solder of the low melting point solder molten bath of melting or embedding melting under vacuum environment, to form required low melting point solder obturator in through hole.
The material of described substrate comprises silicon, GaAs, gallium nitride or glass.
In described step f, in through hole, comprise residual metal layer or high-temperature metal phase,
The fusing point of described high-temperature metal phase is higher than 300 degree, and high-temperature metal comprises Ag mutually 3sn, Cu 6sn 5, rich Pb phase or rich Bi phase.
In described step b, when substrate is conductor or Semiconductor substrate, at substrate surface deposition insulating layer, described insulating barrier is covered in the surface of substrate and covers the inner wall surface of through hole; When forming after insulating barrier in substrate and through hole, adhesion layer covers the surface of substrate and through hole inner insulating layer.
The material of described insulating barrier is SiO 2, Si xn 1-xin one or more.
Described high-temperature metal layer is one or more of material in Cu, Ni, Ag, Pd, Au or Fe.
Low melting point solder obturator is one or more of material in Sn, In, SnAg, SnIn, SnBi, SnPb, SnAgCu, InAg, InSn.
The material of described adhesion layer is Ti, TiN or Ta.
Advantage of the present invention: be provided with at least one vertical through hole connecting in substrate, on the inwall of through hole, growth has insulating barrier, and fills intermetallic compounds layer in through hole, has adhesion layer between intermetallic compounds layer and insulating barrier; By intermetallic compounds layer can complete three-dimensional stacked in required electrical connection, whole formation manufacturing process is convenient, has reduced process complexity and cost of manufacture; Thereby can on integrated circuit, make vertical interconnecting structure, also can on passive base board, make keyset, improve qualification rate, safe and reliable.
Accompanying drawing explanation
Fig. 1 is structural representation of the present invention.
Fig. 2 is the structural representation that the present invention has kish layer and residue gold symbolic animal of the birth year.
Fig. 3 is that the present invention makes the use state diagram after keyset.
Fig. 4～Figure 10 is concrete technology step cutaway view of the present invention, wherein:
Fig. 4 is that growth obtains the cutaway view after insulating barrier in through hole.
Fig. 5 is that deposit obtains the cutaway view after adhesion layer in through hole.
Fig. 6 is the cutaway view obtaining in through hole after high-temperature metal layer.
Fig. 7 fills the cutaway view obtaining after low melting point solder obturator in through hole.
Fig. 8 is the structural representation after flat polish.
Fig. 9 forms the cutaway view after intermetallic compound after high-temperature metal and the thermal diffusion of low melting point solder obturator.
Figure 10 has the cutaway view after residual metal layer after high-temperature metal and the thermal diffusion of low melting point solder obturator.
Description of reference numerals: 10-substrate, 12-through hole, 20-insulating barrier, 24-high-temperature metal layer, 26-low melting point solder obturator, 30-adhesion layer, 32-residual metal layer, 36-high-temperature metal phase and 40-intermetallic compounds layer.
Embodiment
Below in conjunction with concrete drawings and Examples, the invention will be further described.
As shown in Figure 1, Figure 2, shown in Fig. 9 and Figure 10: the vertical interconnecting structure in the present invention comprises substrate 10, and the material of described substrate 10 is silicon, GaAs, and gallium nitride or glass are provided with at least one vertical through hole 12 that penetrates substrate 10 that connects in substrate 10.In order to realize interconnect package, in the time that substrate 10 is conductor or semi-conducting material, on the inwall of through hole 12, growth has insulating barrier 20, and described insulating barrier 20 is SiO 2, Si xn 1-xin one or more.Grow to have in the through hole 12 of insulating barrier 20 at inwall and be filled with intermetallic compounds layer 40, between described intermetallic compounds layer 40 and insulating barrier 20, be provided with adhesion layer 30, can make intermetallic compounds layer 40 in forming process, can effectively be filled in through hole 12 by adhesion layer 30, intermetallic compounds layer 40 is filled full whole through hole 12.The material of adhesion layer 30 is Ti, TiN or Ta.In the time that substrate 10 is insulating material, through hole 12 is interior can not arrange insulating barrier 20, at the interior adhesion layer 30 that directly arranges of through hole 12.
Intermetallic compounds layer 40 is that the high-temperature metal layer 24 in through hole 12 is forming after required thermal diffusion with low melting point solder obturator 26; Form in the process of intermetallic compounds layer 40, due to differences such as the thickness of high-temperature metal layer 24, between adhesion layer 30 and intermetallic compounds layer 40, also remain residual metal layer 32; Due to the difference that arranges of low melting point solder obturator 26, may there is high-temperature metal mutually 36 intermetallic compounds layer 40 is interior; For example high-temperature metal layer 24 is Cu, and low melting point solder obturator 26 adopts SnBi, and when Sn and Cu diffusion reaction, Sn exhausts rear rich Bi and meets and remain, and in intermetallic compounds layer 40, obtains rich Bi phase.Described high-temperature metal layer 24 is one or more in Cu, Ni, Ag, Pd, Au or Fe; Low melting point solder obturator 26 is one or more in Sn, In, SnAg, SnIn, SnBi, SnPb, SnAgCu, InAg, InSn.Described intermetallic compounds layer 40 is one or more in Cu-Sn, Ni-Sn, Cn-In, Ni-In, Ag-Sn, Au-Sn, Ag-In, Au-In.Described high-temperature metal phase 36 comprises Ag 3sn, Cu 6sn 5, rich Pb phase or rich Bi phase.
As shown in Fig. 4～Figure 10: above-mentioned vertical interconnection structure can be realized by following concrete technology step, is in particular:
A, provide substrate 10, and penetrate the through hole 12 of substrate 10 in the required vertical perforation of the interior formation of substrate 10;
In the embodiment of the present invention, substrate 10 is selected 8 cun of Silicon Wafers, and by the reduced thickness to 300 of described Silicon Wafer micron; In Silicon Wafer, form through hole 12 by common process, the aperture of described through hole 12 is generally 30 microns;
B, on the surface of above-mentioned substrate 10 deposit adhesion layer 30, described adhesion layer 30 is covered in the surface of substrate 10 and is covered in the inner wall surface of through hole 12;
When substrate 10 is conductor or Semiconductor substrate as shown in Figure 4, at substrate 10 surface deposition insulating barriers 20, described insulating barrier 20 is covered in the surface of substrate 10 and covers the inner wall surface of through hole 12; When after substrate 10 and the interior formation insulating barrier 20 of through hole 12, adhesion layer 30 covers the surface of substrate 10 and through hole 12 inner insulating layers 20; In the Film by Thermal Oxidation oxide layer of Silicon Wafer, obtain being positioned at the insulating barrier 20 on substrate 10 surfaces and through hole 12 inwalls;
As shown in Figure 5: in the embodiment of the present invention, by deposit Ti on substrate 10 surfaces, the thickness of described Ti layer, can be set, using this as adhesion layer 30 and barrier layer between hundreds of micron as required tens; In the process of deposit Ti, can cover the interior corresponding insulating barrier 20 of through hole 12 simultaneously;
C, the high-temperature metal layer 24 of isolating in the setting of the surface of above-mentioned substrate 10 and substrate 10 insulation, described high-temperature metal layer 24 covers the surface of substrate 10 and is covered in the surface of the interior corresponding adhesion layer 30 of through hole 12;
As shown in Figure 6: first plated metal on above-mentioned adhesion layer 30 of the forming process of described high-temperature metal layer 24, then electroplating or extremely required thickness of chemical plating; When the present invention specifically implements, high-temperature metal layer 24 adopts Cu, first, by physical vapour deposition (PVD) Cu, is then being electroplated to 6 microns; In the time having insulating barrier 20 in through hole 12, high-temperature metal layer 24 is by the isolation of insulating mutually of insulating barrier 24 and substrate 10;
D, at the interior filling low melting point of above-mentioned through hole 12 solder, with at the interior formation low melting point of through hole 12 solder obturator 26;
As shown in Figure 7: in the time of the interior filling low melting point of through hole 12 solder, substrate 10 can be inserted in the low melting point solder molten bath of melting, or under vacuum environment embedding melting low melting point solder; Due to capillary effect, at short notice, just can complete filling; In specific embodiment of the invention, low melting point solder is Sn, and the temperature in filling process is higher than the fusing point of Sn, such as can be at 260 degree;
E, substrate 10 surfacings to above-mentioned formation low melting point solder obturator 26, the surface of polished substrate 10 correspondences, to make the low melting point solder obturator 26 in through hole 12 concordant with the surface of polishing back substrate 10;
As shown in Figure 8: in through hole 12, form after low melting point solder obturator 26 by filling low melting point solder, the two ends of low melting point solder obturator 26 can form salient point, and the height of described salient point is higher than the surface of substrate 10; Therefore by leveling polishing operation, some material layers on salient point and substrate 10 surfaces are removed; Described leveling can adopt chemical mechanical polishing (CMP) or other planarization process;
F, at required temperature, low melting point solder obturator 26 and high-temperature metal layer 24 are carried out to heat diffusion treatment, until low melting point solder obturator 26 all melt after and high-temperature metal layer 24 form intermetallic compounds layer 40.
In order to form required intermetallic compounds layer 40, need at required temperature, carry out heat diffusion treatment; The time of heat diffusion treatment is with till can making 26 diffusions of low melting point solder obturator melt; In the time adopting in that the present invention aforesaid material, intermetallic compounds layer 40 is Cu 6sn 5, Cu 3sn or Cu 6sn 5, Cu 3both mixing of Sn.When high-temperature metal layer 24 exceedes certain thickness, after thermal diffusion, just have remnants, as the residual metal layer 32 in Fig. 2 and Figure 10.
Fig. 3 is the structural representation of making keyset after vertical interconnecting structure of the present invention when forming.There is two layers of wiring and dimpling point in the front of keyset, there is overleaf one deck wiring and dimpling point, can complete the encapsulation of integrated circuit by keyset.
In substrate 10 of the present invention, be provided with at least one vertical through hole 12 connecting, in through hole 12 by vertical direction on continuous intermetallic compounds layer 40 fill, between intermetallic compounds layer 40 and substrate 10, there is adhesion layer 30; By intermetallic compounds layer 40 can complete three-dimensional stacked in required electrical connection, whole formation manufacturing process is convenient, has reduced process complexity and cost of manufacture; Thereby can on integrated circuit, make vertical interconnecting structure, also can on passive base board, make keyset, improve qualification rate, safe and reliable.
The foregoing is only specific embodiments of the invention; not in order to limit the present invention; in the present embodiment, material therefor and process conditions only limit to the present embodiment; within the spirit and principles in the present invention all; any modification of doing, be equal to replacement, improvement etc., within protection scope of the present invention all should be included in.

Claims (14)

1. the vertical through hole interconnection structure that three-dimension packaging is filled with intermetallic compound, comprises substrate (10), is provided with at least one vertical through hole (12) that penetrates substrate (10) that connects in described substrate (10); It is characterized in that: in described through hole (12), filled by the continuous intermetallic compound of vertical direction (40), between described intermetallic compounds layer (40) and substrate (10), be provided with adhesion layer (30);
Described intermetallic compounds layer (40) forms with low melting point solder obturator (26) thermal diffusion by the high-temperature metal layer (24) being filled in through hole (12);
Described high-temperature metal layer (24) is one or more of material in Cu, Ni, Ag, Pd, Au or Fe; Low melting point solder obturator (26) is one or more of material in Sn, In, SnAg, SnIn, SnBi, SnPb, SnAgCu, InAg, InSn.
2. the vertical through hole interconnection structure that three-dimension packaging according to claim 1 is filled with intermetallic compound, it is characterized in that: described substrate (10) comprises insulating barrier (20) with adhesion layer (30), and adhesion layer (30) adheres on the inwall of through hole (12) by insulating barrier (20).
3. the vertical through hole interconnection structure that three-dimension packaging according to claim 1 and 2 is filled with intermetallic compound, it is characterized in that: between described intermetallic compounds layer (40) and adhesion layer (30), also comprise residual metal layer (32), intermetallic compounds layer (40) is connected with adhesion layer (30) by residual metal layer (32).
4. the vertical through hole interconnection structure that three-dimension packaging according to claim 1 and 2 is filled with intermetallic compound, is characterized in that: described intermetallic compounds layer (40) is one or more in Cu-Sn, Ni-Sn, Cn-In, Ni-In, Ag-Sn, Au-Sn, Ag-In, Au-In etc.
5. the vertical through hole interconnection structure that three-dimension packaging according to claim 1 and 2 is filled with intermetallic compound, is characterized in that: in described intermetallic compounds layer (40), comprise high-temperature metal phase (36), the fusing point of high-temperature metal phase (36) is higher than 300 degree.
6. the vertical through hole interconnection structure that three-dimension packaging according to claim 2 is filled with intermetallic compound, is characterized in that: the material of described insulating barrier (20) is SiO 2, Si xn 1-xin one or more.
7. the vertical through hole interconnection structure preparation method that three-dimension packaging is filled with intermetallic compound, is characterized in that, described vertical interconnecting structure preparation method comprises the steps:
(a), substrate (10) is provided, and in substrate (10), form required vertical perforation and penetrate the through hole (12) of substrate (10);
(b), on the surface of above-mentioned substrate (10) deposit adhesion layer (30), described adhesion layer (30) is covered in the surface of substrate (10) and is covered in the inner wall surface of through hole (12);
(c) the high-temperature metal layer (24), in the setting of the surface of above-mentioned substrate (10) with substrate (10) insulation, described high-temperature metal layer (24) covers the surface of substrate (10) and is covered in the surface of the interior corresponding adhesion layer (30) of through hole (12);
(d), in above-mentioned through hole (12), fill low melting point solder, to form low melting point solder obturator (26) in through hole (12);
(e) substrate (10) surfacing, to above-mentioned formation low melting point solder obturator (26), the surface that polished substrate (10) is corresponding, to make the low melting point solder obturator (26) in through hole (12) concordant with the surface of polishing back substrate (10);
(f), at required temperature, low melting point solder obturator (26) and high-temperature metal layer (24) are carried out to heat diffusion treatment, until low melting point solder obturator (26) all melt after with high-temperature metal layer (24) formation intermetallic compounds layer (40);
Described high-temperature metal layer (24) is one or more of material in Cu, Ni, Ag, Pd, Au or Fe;
Low melting point solder obturator (26) is one or more of material in Sn, In, SnAg, SnIn, SnBi, SnPb, SnAgCu, InAg, InSn.
8. the vertical through hole interconnection structure preparation method that three-dimension packaging according to claim 7 is filled with intermetallic compound, it is characterized in that: in described step (d), by substrate (10) is inserted to the low melting point solder molten bath of melting or the low melting point solder of embedding melting under vacuum environment, to form required low melting point solder obturator (26) in through hole (12).
9. the vertical through hole interconnection structure preparation method that three-dimension packaging according to claim 7 is filled with intermetallic compound, is characterized in that: the material of described substrate (10) comprises silicon, GaAs, gallium nitride or glass.
10. the vertical through hole interconnection structure preparation method that three-dimension packaging according to claim 8 is filled with intermetallic compound, is characterized in that: in described step (f), comprise residual metal layer (32) or high-temperature metal phase (36) in through hole (12).
The vertical through hole interconnection structure preparation method that 11. three-dimension packaging according to claim 10 are filled with intermetallic compound, is characterized in that: the fusing point of described high-temperature metal phase (36) is higher than 300 degree, and high-temperature metal phase (36) comprises Ag 3sn, Cu 6sn 5, rich Pb phase or rich Bi phase.
The vertical through hole interconnection structure preparation method that 12. three-dimension packaging according to claim 7 are filled with intermetallic compound, it is characterized in that: in described step (b), when substrate (10) is conductor or Semiconductor substrate, at substrate (10) surface deposition insulating barrier (20), described insulating barrier (20) is covered in the surface of substrate (10) and covers the inner wall surface of through hole (12); When forming in substrate (10) and through hole (12) after insulating barrier (20), adhesion layer (30) covers the surface of substrate (10) and through hole (12) inner insulating layer (20).
The vertical through hole interconnection structure preparation method that 13. three-dimension packaging according to claim 12 are filled with intermetallic compound, is characterized in that: the material of described insulating barrier (20) is SiO 2, Si xn 1-xin one or more.
The vertical through hole interconnection structure preparation method that 14. three-dimension packaging according to claim 7 are filled with intermetallic compound, is characterized in that: the material of described adhesion layer (30) is Ti, TiN or Ta.
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