CN102427307B - Three-phase four-wire three-level inverter - Google Patents
Three-phase four-wire three-level inverter Download PDFInfo
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- CN102427307B CN102427307B CN201110326742.XA CN201110326742A CN102427307B CN 102427307 B CN102427307 B CN 102427307B CN 201110326742 A CN201110326742 A CN 201110326742A CN 102427307 B CN102427307 B CN 102427307B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/483—Converters with outputs that each can have more than two voltages levels
- H02M7/487—Neutral point clamped inverters
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Abstract
The invention discloses a three-phase four-wire three-level inverter, which comprises four topological units. The four topological units at least comprise the following two topological units: any one of a first topological unit and a second topological unit, and any one of a 1-shaped topological unit and a T-shaped topological unit, wherein a first switching device, a second switching device and a fourth switching device in the first topological unit are serially connected between the two ends of a direct-current power supply, the second end of a third switching device is connected with the central voltage dividing point of the direct-current power supply, and the first end of the third switching device is connected with the second end of the first switching device and the first end of the second switching device; and a first switching device, a third switching device and a fourth switching device in the second topological unit are serially connected between the two ends of the direct-current power supply, the first end of the second switching device is connected with the central voltage dividing point of the direct-current power supply, and the second end of the second switching device is connected with the second end of the third switching device and the first end of the fourth switching device. By using the three-phase four-wire three-level inverter, the loss can be reduced and the conversion efficiency is improved.
Description
Technical field
The present invention relates to voltage transitions technical field, be specifically related to a kind of three-phase four-wire system three-level inverter.
Background technology
Inverter refers to the effect that turns on and off by semiconductor power switch device, direct current energy is converted to a kind of converter of AC energy.In recent years, three-level inverter, owing to having the advantages such as output capacity is large, output voltage is high, current harmonic content is little, is widely used in high-power ac motor speed control by variable frequency field.
Owing to being subject to power device capacity, neutral line current, the requirement of electrical network load balance and with the restriction of the character (as three-phase AC asynchronous motor etc.) of electric loading, single-phase inverter capacity is generally lower, jumbo inverter adopts three-phase form more.
Each phase topology unit of existing three-phase tri-level inverter topology mainly contains two classes, respectively: 1 font topological structure and T font topological structure.
As shown in Figure 1, be the schematic diagram of 1 font topological structure in prior art.
In this 1 font topological structure, by connecting between direct current positive and negative busbar voltage, two equal electric capacity (being capacitor C 1 and the capacitor C 2 in Fig. 1) of capacitive reactance obtain three level: positive bus-bar level, two capacitances in series contact level, negative busbar level.Single phase half bridge inverter exchanges a binding post of output and draws from the contact n of above-mentioned two series capacitances, and another ac output end a point from figure is drawn.
The course of work of every phase topology unit is as follows:
When semiconductor switch pipe T1, T2 conducting, when semiconductor switch pipe T3, T4, diode D3, D4, D5, D6 cut-off, the level of output node a equals positive bus-bar level.When outlet side electric current flows out to inductance L 1 from a point, diode D1, D2 cut-off, current circuit is T1-T2-L1-V
g-L2-C1-T1; When outlet side electric current flows to a point from L1, diode D1, D2 conducting, current circuit is D2-D1-C1-L2-V
g-L1-D2.
When semiconductor switch pipe T2, T3 conducting, when semiconductor switch pipe T1, T4, diode D1, D2, D3, D4 cut-off, the level of output node a equals two capacitances in series contact level.When outlet side electric current flows out to L1 from a point, diode D5 conducting, diode D6 cut-off, current circuit is D5-T2-L1-V
g-L2-D5; When outlet side electric current flows to a point from L1, diode D6 conducting, diode D5 cut-off, current circuit is T3-D6-L2-V
g-L1-T3.
When semiconductor switch pipe T3, T4 conducting, when semiconductor switch pipe T1, T2, diode D1, D2, D5, D6 cut-off, the level of output node a equals negative busbar level.When outlet side electric current flows out to L1 from a point, diode D3, D4 conducting, current circuit is D4-D3-L1-V
g-L2-C2-D4; When outlet side electric current flows to a point from L1, diode D3, D4 cut-off, current circuit is T3-T4-C2-L2-V
g-L1-T3.
From the above-mentioned course of work, four groups of semiconductor switch pipes (T1 and D1 of 1 font three-level inverter, T2 and D2, T3 and D3, T4 and D4) maximum voltage that bears is half of the total input voltage of direct current, therefore, can select the semiconductor switch pipe that rated voltage is less and then reduce its switching loss.But in this topology, need two clamping diode D5, D6, increased device number and its loss, also increased the on-state loss of semiconductor switch pipe T2, T3 simultaneously.
As shown in Figure 2, be the schematic diagram of T font topological structure in prior art.
In this T font topological structure, by connecting between direct current positive and negative busbar voltage, two equal electric capacity (being capacitor C 1 and the capacitor C 2 in Fig. 2) of capacitive reactance obtain three level: positive bus-bar level, two capacitances in series contact level, negative busbar level, single phase half bridge inverter exchanges a binding post of output and draws from the contact n of above-mentioned two series capacitances, and another ac output end a point from figure is drawn.
The course of work of every phase topology unit is as follows:
When semiconductor switch pipe T1, T2 conducting, when semiconductor switch pipe T3, T4, D2, D3, D4 cut-off, the level of output node a equals positive bus-bar level.When outlet side electric current flows out to inductance L 1 from a point, diode D1 cut-off, current circuit is T1-L1-V
g-L2-C1-T1; When outlet side electric current flows to a point from inductance L 1, diode D1 conducting, current circuit is D1-C1-L2-V
g-L1-D1.
When semiconductor switch pipe T2, T3 conducting, when semiconductor switch pipe T1, T4, D1, D4 cut-off, the level of output node a equals two capacitances in series contact level.When outlet side electric current flows out to inductance L 1 from a point, diode D3 conducting, diode D2 cut-off, current circuit is T2-D3-L1-V
g-L2-T2; When outlet side electric current flows to a point from inductance L 1, diode D2 conducting, diode D3 cut-off, current circuit is T3-D2-L2-V
g-L1-T3.
When semiconductor switch pipe T3, T4 conducting, when semiconductor switch pipe T1, T2, D1, D2, D3 cut-off, the level of output node a equals negative busbar level.When outlet side electric current flows out to inductance L 1 from a point, diode D4 conducting, current circuit is D4-L1-V
g-L2-C2-D4; When outlet side electric current flows to a point from inductance L 1, diode D4 cut-off, current circuit is T4-C2-L2-V
g-L1-T4.
From the above-mentioned course of work, the maximum voltage that in four groups of semiconductor switch pipes of T font three-level inverter, T1, T4 bear is the total input voltage of direct current, and the maximum voltage that T2, T3 bear is the total input voltage of half direct current.Therefore, increase the switching loss of semiconductor switch pipe T1, T4, but without two clamping diodes, avoided this part loss.
Summary of the invention
The problem that the embodiment of the present invention exists for above-mentioned prior art, provides a kind of three-phase four-wire system three-level inverter, to reduce loss, improves energy conversion efficiency.
For this reason, the embodiment of the present invention provides following technical scheme:
A kind of three-phase four-wire system three-level inverter, for the converting direct-current power into alternating-current power that DC power supply is exported, comprise: four topology unit, each topology unit in described four topology unit is connected between described DC power supply, and in described four topology unit, at least comprise following two topology unit: the first topology unit and the second topology unit the two one of and 1 font topology unit and T font topology unit the two one of, wherein:
Described the first topology unit comprises: four switching devices, the first switching device wherein, second switch device and the 4th switching device are connected in series between described DC power supply, wherein, the first end of the first switching device connects the anode of described DC power supply, and the second end of the 4th switching device connects the negative terminal of described DC power supply; The second end of the 3rd switching device connects the dividing potential drop mid point of described DC power supply, and the first end of the 3rd switching device connects the second end of the first switching device and the first end of second switch device; The second end of second switch device is connected with the first end of the 4th switching device and as an output of described inverter;
Described the second topology unit comprises: four switching devices, the first switching device wherein, the 3rd switching device and the 4th switching device are connected in series between described DC power supply, wherein, the first end of the first switching device connects the anode of described DC power supply, and the second end of the 4th switching device connects the negative terminal of described DC power supply; The first end of second switch device connects the dividing potential drop mid point of described DC power supply, and the second end of second switch device connects the second end of the 3rd switching device and the first end of the 4th switching device; The second end of the first switching device is connected with the first end of the 3rd switching device and as an output of described inverter.
Preferably, each switching device includes: switching tube and with the antiparallel diode of described switching tube.
Alternatively, described diode is the anti-paralleled diode that separate diode or described switching tube inside carry.
Preferably, the driving signal of four switching devices in described the first topology unit or the second topology unit is handed over and is cut generation with triangular carrier by sinusoidal wave, and:
At the positive half period of described sinusoidal modulation wave, second switch break-over of device, the 4th switching device turn-offs, and if the level of described triangular carrier is less than the level of described sinusoidal modulation wave, the first switching device conducting, the 3rd switching device turn-offs; If the level of described triangular carrier is greater than the level of described sinusoidal modulation wave, the first switching device turn-offs, the 3rd switching device conducting;
Negative half-cycle at described sinusoidal modulation wave, the first switching device keeps off state, and the 3rd switching device keeps conducting state, and if the level of described triangular carrier is greater than the level of described sinusoidal modulation wave after oppositely, second switch break-over of device, the 4th switching device turn-offs; If the level of described triangular carrier is less than the level of described sinusoidal modulation wave after oppositely, second switch device turn-offs, the 4th switching device conducting.
Preferably, the output of any one topology unit in described four topology unit is as zero line, and the output of other three topology unit is as live wire.
Preferably, described three-phase four-wire system three-level inverter also comprises:
Two dividing potential drop electric capacity, are connected in series between described DC power supply, for described DC power supply is carried out to dividing potential drop, and the dividing potential drop mid point that the tie point of described two dividing potential drop electric capacity is described DC power supply.
Preferably, the capacitive reactance of described two electric capacity is identical.
The three-phase four-wire system three-level inverter that the embodiment of the present invention provides, can, when the device count that keeps three-level inverter is minimum, reduces the voltage stress of part switching tube, thereby can select small-power semiconductor switch pipe, reduce loss, improve conversion efficiency.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present application or technical scheme of the prior art, to the accompanying drawing of required use in embodiment be briefly described below, apparently, the accompanying drawing the following describes is only some embodiment that record in the present invention, for those of ordinary skills, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is each phase 1 font topological structure schematic diagram of three-phase tri-level inverter topology in prior art;
Fig. 2 is each phase T font topological structure schematic diagram of three-phase tri-level inverter topology in prior art;
Fig. 3 is the structural representation of the first topology unit in the embodiment of the present invention;
Fig. 4 is the structural representation of the second topology unit in the embodiment of the present invention;
Fig. 5 is the structural representation of 1 font topology unit in the embodiment of the present invention;
Fig. 6 is the structural representation of T font topology unit in the embodiment of the present invention;
Fig. 7, Fig. 8, Fig. 9, Figure 10 are respectively a kind of structural representations of embodiment of the present invention three-phase four-wire system three-level inverter;
Figure 11 is the driving signal schematic representation of each switching device in the first topology unit and the second topology unit in the embodiment of the present invention;
Figure 12 is the current circuit schematic diagram of the first topology unit under the first operation mode in the embodiment of the present invention;
Figure 13 is the current circuit schematic diagram of the first topology unit under the second operation mode in the embodiment of the present invention;
Figure 14 is the current circuit schematic diagram of the first topology unit under the 3rd operation mode in the embodiment of the present invention.
Figure 15 is the current circuit schematic diagram of the second topology unit under the first operation mode in the embodiment of the present invention;
Figure 16 is the current circuit schematic diagram of the second topology unit under the second operation mode in the embodiment of the present invention;
Figure 17 is the current circuit schematic diagram of the second topology unit under the 3rd operation mode in the embodiment of the present invention.
Embodiment
In order to make those skilled in the art person understand better the scheme of the embodiment of the present invention, below in conjunction with drawings and embodiments, the embodiment of the present invention is described in further detail.
The embodiment of the present invention provides a kind of three-phase four-wire system three-level inverter, and for the converting direct-current power into alternating-current power that DC power supply is exported, described DC power supply can be photo-voltaic power supply, can be also energy-storage battery.The outlet side of described three-phase four-wire system three-level inverter can get access to grid or AC load.
At this three-phase four-wire system three-level inverter, comprise: four topology unit, each topology unit in described four topology unit is connected between described DC power supply, and at least comprises following two topology unit in described four topology unit: the first topology unit and the second topology unit the two one of and 1 font topology unit and T font topology unit the two one of.
First these four topology unit are elaborated below.
For convenience, by above-mentioned the first topology unit, referred to as M1, the second topology unit is referred to as M2.
As shown in Figure 3, be a kind of structural representation and the corresponding simplified block diagram thereof of the first topology unit in the embodiment of the present invention.
This first topology unit comprises: four switching devices, the first switching device wherein, second switch device and the 4th switching device are connected in series between described DC power supply, wherein, the first end of the first switching device connects the anode of described DC power supply, and the second end of the 4th switching device connects the negative terminal of described DC power supply; The second end of the 3rd switching device connects the dividing potential drop mid point of described DC power supply, and the first end of the 3rd switching device connects the second end of the first switching device and the first end of second switch device; The second end of second switch device is connected with the first end of the 4th switching device and as an output of described inverter.
As shown in Figure 4, be a kind of structural representation and the corresponding simplified block diagram thereof of the second topology unit in the embodiment of the present invention.
This second topology unit comprises: four switching devices, the first switching device wherein, the 3rd switching device and the 4th switching device are connected in series between described DC power supply, wherein, the first end of the first switching device connects the anode of described DC power supply, and the second end of the 4th switching device connects the negative terminal of described DC power supply; The first end of second switch device connects the dividing potential drop mid point of described DC power supply, and the second end of second switch device connects the second end of the 3rd switching device and the first end of the 4th switching device; The second end of the first switching device is connected with the first end of the 3rd switching device and as an output of described inverter.
As shown in Figure 5, be structural representation and the corresponding simplified block diagram thereof of 1 font topology unit in the embodiment of the present invention.
This 1 font topology unit is same as the prior art, comprising: four switching devices, these four switching devices are connected in series between described DC power supply successively, in addition, also comprise two clamping diode D5, D6.
As shown in Figure 6, be structural representation and the corresponding simplified block diagram thereof of T font topology unit in the embodiment of the present invention.
This T font topology unit is same as the prior art, comprise: four switching devices, the first switching device wherein and the 4th switching device are connected in series between described DC power supply, wherein, the first end of the first switching device connects the anode of described DC power supply, and the second end of the 4th switching device connects the negative terminal of described DC power supply; The second end of second switch device is connected with the second end of the 3rd switching device, and, the first end of second switch device connects the dividing potential drop mid point of described DC power supply, and the first end of the 3rd switching device is connected with the second end of the first switching device and the first end of the 4th switching device respectively.
It should be noted that, in actual applications, the dividing potential drop mid point of above-mentioned DC power supply can be formed by two dividing potential drop electric capacity that are connected in series between described DC power supply, the dividing potential drop mid point that tie point of described two dividing potential drop electric capacity is described DC power supply.
Each switching device in above-mentioned Fig. 3 to Fig. 6 comprises: switching tube and with the antiparallel diode of described switching tube, described switching tube can be semiconductor switch pipe, such as MOSFET (high voltage metal oxide silicon field effect transistor), IGBT (igbt), IGCT (integrated gate commutated thyristor), IEGT (strengthening injection grid transistor) etc.Described diode can be the anti-paralleled diode that separate diode or described switching tube inside carry.Correspondingly, the drain electrode of described switching tube or collector electrode are connected and form the first end of described switching device with the negative electrode of described diode, and the source electrode of described switching tube or emitter are connected with the anode of described diode and form the second end of described switching device.Certainly, the embodiment of the present invention does not limit the type of above-mentioned switching tube, can also be the switching tube of other type.
As shown in Figures 3 to 6, the first switching device is comprised of the first switch transistor T 1 and the first diode D1, second switch device is comprised of second switch pipe T2 and the second diode D2, the 3rd switching device is comprised of the 3rd switch transistor T 3 and the 3rd diode D3, and the 4th switching device is comprised of the 4th switch transistor T 4 and the 4th diode D4.
Based on above-mentioned various topology unit, the three-phase four-wire system three-level inverter that the embodiment of the present invention provides can have various deformation structure.
Fig. 7, Fig. 8, Fig. 9, Figure 10 are respectively a kind of structural representations of embodiment of the present invention three-phase four-wire system three-level inverter.
As shown in Figure 7, two dividing potential drop capacitor C 11, C12 are connected in series between DC power supply, and the capacitive reactance of two dividing potential drop capacitor C 11, C12 is identical, for DC power supply is carried out to dividing potential drop; Four topology unit are respectively the first topology unit M1, the first topology unit M1, the first topology unit M1 and 1 font topology unit, are connected between described DC power supply.
Shown in Fig. 8, Fig. 9, Figure 10, three-phase four-wire system three-level inverter and Fig. 7 are similar, and just four topology unit in Fig. 8 are respectively the first topology unit M1, the first topology unit M1, the first topology unit M1 and T font topology unit; Four topology unit in Fig. 9 are respectively the second topology unit M2, the second topology unit M2, the second topology unit M2 and 1 font topology unit; Four topology unit in Figure 10 are respectively the second topology unit M2, the second topology unit M2, the second topology unit M2 and T font topology unit.
It should be noted that, in each three-phase four-wire system three-level inverter shown in Fig. 7 to Figure 10, in the output of four topology unit, can select that wherein any one is as zero line, the output of other other three topology unit is as live wire.Article three, driving signal phase mutual deviation 120 degree of each corresponding switching device in three topology unit that live wire is corresponding.
In addition, shown in Fig. 7 to Figure 10, be only several examples of embodiment of the present invention three-phase four-wire system three-level inverter, be not limited in above-mentioned these several topological forms, can also have other topological form, only need make at least to comprise in four topology unit following two topology unit: the first topology unit and the second topology unit the two one of and 1 font topology unit and T font topology unit the two one of.
In the embodiment of the present invention, in the first topology unit M1 and the second topology unit M2 and 1 font topology unit and T font topology unit, the driving signal of four switching devices is handed over and is cut generation by sinusoidal modulation wave (being modulation signal) and triangular carrier (being carrier signal), as shown in figure 11.
Wherein, Ug is sinusoidal wave, and such as 50Hz, Uc is triangular carrier, as 20KHz.S1, S2, S3 and S4 represent respectively the driving signal of the first switching device, second switch device, the 3rd switching device and the 4th switching device, V
anthe output signal that represents corresponding topology unit.
At the positive half period of described sinusoidal modulation wave Ug, second switch device and the 4th switching device drive with power frequency component, and the first switching device and the 3rd switching device drive with high-frequency pulse signal.Particularly, as shown in figure 21, second switch break-over of device, the 4th switching device turn-offs, and if the level of described triangular carrier is less than the level of described sinusoidal modulation wave, i.e. and Uc < Ug, the first switching device conducting, the 3rd switching device turn-offs; If the level of described triangular carrier is greater than the level of described sinusoidal modulation wave, i.e. Uc > Ug, the first switching device turn-offs, the 3rd switching device conducting;
At the negative half-cycle of described sinusoidal modulation wave Ug, the first switching device and the 3rd switching device drive with power frequency component, and second switch device and the 4th switching device drive with high-frequency pulse signal.Particularly, as shown in figure 21, the first switching device keeps off state, the 3rd switching device keeps conducting state, and if the level of described triangular carrier is greater than the level of described sinusoidal modulation wave after oppositely, be Uc >-Ug, second switch break-over of device, the 4th switching device turn-offs; If the level of described triangular carrier is less than the level of described sinusoidal modulation wave after oppositely, i.e. Uc <-Ug, second switch device turn-offs, the 4th switching device conducting.
It should be noted that, above-mentioned high-frequency pulse signal is pwm pulse signal, such as being pulse signal within the scope of KHz.
Above-mentioned four topology unit in the embodiment of the present invention are all operated in the operation mode of three level, and the course of work of 1 font topology unit and T font topology unit is same as the prior art, at this, is not described in detail.Only in conjunction with Fig. 3 and Fig. 4, describe the course of work of the first topology unit M1 and the second topology unit M2 in the embodiment of the present invention below in detail.
Figure 12, Figure 13 and Figure 14 show respectively three operation modes of the first topology unit M1, wherein:
As shown in figure 12, when the first switch transistor T 1, second switch pipe T2 conducting, when the 3rd switch transistor T 3, the 4th switch transistor T 4, the 3rd diode D3, the 4th diode D4 cut-off, the level of output node a equals positive bus-bar level.When outlet side electric current flows out to inductance L from node a, the first diode D1, the second diode D2 cut-off, current circuit is T1-T2-L-V
g-C1-T1; Outlet side electric current is during from inductance L flows into node a, the first diode D1 and the second diode D2 conducting, and current circuit is D2-D1-C1-V
g-L-D2.
As shown in figure 13, when second switch pipe T2, the 3rd switch transistor T 3 conductings, when the first switch transistor T 1, the 4th switch transistor T 4, the first diode D1, the 4th diode D4 cut-off, the level of output node a equals the level of two dividing potential drop capacitances in series contact n, i.e. V
dc/ 2, wherein, V
dclevel for DC power supply.When outlet side electric current flows out to inductance L from node a, the 3rd diode D3 conducting, the second diode D2 cut-off, current circuit is D3-T2-L-V
g-D3; Outlet side electric current is during from the first inductance L 1 flows into node a, the second diode D2 conducting, and the 3rd diode D3 cut-off, current circuit is D2-T3-V
g-L-D2.
As shown in figure 14, when the 3rd switch transistor T 3, the 4th switch transistor T 4 conductings, when the first switch transistor T 1, second switch pipe T2, the first diode D1, the second diode D2, the 3rd diode D3 cut-off, the level of output node a equals negative busbar level.When outlet side electric current flows out to inductance L from node a, the 4th diode D4 conducting, current circuit is D4-L-V
g-C2-D4; Outlet side electric current is during from inductance L flows into node a, the 4th diode D4 cut-off, and current circuit is T4-C2-V
g-L-T4.
By the above-mentioned course of work, can be found out that the first topology unit in the embodiment of the present invention, without two clamping diodes, has reduced the on-state loss of a switching tube; And wherein the voltage stress of two groups of switching tubes reduces half, therefore can select small-power semiconductor switch pipe, reduce loss, improve conversion efficiency.
Figure 15, Figure 16 and Figure 17 show respectively three operation modes of the second topology unit M2, wherein:
As shown in figure 15, when the first switch transistor T 1, second switch pipe T2 conducting, when the 3rd switch transistor T 3, the 4th switch transistor T 4, the second diode D2, the 3rd diode D3, the 4th diode D4 cut-off, the level of output node a equals positive bus-bar level.When outlet side electric current flows out to inductance L from node a, the first diode D1 cut-off, current circuit is T1-L-V
g-C1-T1; When outlet side electric current flows to a point from inductance L, the first diode D1 conducting, current circuit is D1-C1-V
g-L-D1.
As shown in figure 16, when second switch pipe T2, the 3rd switch transistor T 3 conductings, when the first switch transistor T 1, the 4th switch transistor T 4, the first diode D1, the 4th diode D4 cut-off, the level of output node a equals the level of two dividing potential drop capacitances in series contact n, i.e. V
dc/ 2, wherein, V
dclevel for DC power supply.When outlet side electric current flows out to L from node a, the 3rd diode D3 conducting, the second diode D2 cut-off, current circuit is T2-D3-L-V
g-T2; Outlet side electric current is during from inductance L flows into node a, the second diode D2 conducting, and the 3rd diode D3 cut-off, current circuit is T3-D2-V
g-L-T3.
As shown in figure 17, when second switch pipe T2, the 3rd switch transistor T 3 conductings, when the first switch transistor T 1, the 4th switch transistor T 4, the first diode D1, the 4th diode D4 cut-off, the level of output node a equals the level of two dividing potential drop capacitances in series contact n, i.e. V
dc/ 2, wherein, V
dclevel for DC power supply.When outlet side electric current flows out to inductance L from node a, the 3rd diode D3 conducting, the second diode D2 cut-off, current circuit is T2-D3-L-V
g-T2; Outlet side electric current is during from inductance L flows into node a, the second diode D2 conducting, and the 3rd diode D3 cut-off, current circuit is T3-D2-V
g-L-T3.
By the above-mentioned course of work, can be found out that the second topology unit in the embodiment of the present invention, without two clamping diodes, has reduced the on-state loss of a switching tube; And wherein the voltage stress of two groups of switching tubes reduces half, therefore can select small-power semiconductor switch pipe, reduce loss, improve conversion efficiency.
Above the embodiment of the present invention is described in detail, has applied embodiment herein the present invention is set forth, the explanation of above embodiment is just for helping to understand equipment of the present invention; , for one of ordinary skill in the art, according to thought of the present invention, all will change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention meanwhile.
Claims (7)
1. a three-phase four-wire system three-level inverter, for the converting direct-current power into alternating-current power that DC power supply is exported, it is characterized in that, comprise: four topology unit, each topology unit in described four topology unit is connected between described DC power supply, and in described four topology unit, at least comprise following two topology unit: the first topology unit and the second topology unit the two one of and 1 font topology unit and T font topology unit the two one of, wherein:
Described the first topology unit comprises: four switching devices, the first switching device wherein, second switch device and the 4th switching device are connected in series between described DC power supply, wherein, the first end of the first switching device connects the anode of described DC power supply, and the second end of the 4th switching device connects the negative terminal of described DC power supply; The second end of the 3rd switching device connects the dividing potential drop mid point of described DC power supply, and the first end of the 3rd switching device connects the second end of the first switching device and the first end of second switch device; The second end of second switch device is connected with the first end of the 4th switching device and as an output of described inverter;
Described the second topology unit comprises: four switching devices, the first switching device wherein, the 3rd switching device and the 4th switching device are connected in series between described DC power supply, wherein, the first end of the first switching device connects the anode of described DC power supply, and the second end of the 4th switching device connects the negative terminal of described DC power supply; The first end of second switch device connects the dividing potential drop mid point of described DC power supply, and the second end of second switch device connects the second end of the 3rd switching device and the first end of the 4th switching device; The second end of the first switching device is connected with the first end of the 3rd switching device and as an output of described inverter.
2. three-phase four-wire system three-level inverter according to claim 1, is characterized in that, each switching device includes: switching tube and with the antiparallel diode of described switching tube.
3. three-phase four-wire system three-level inverter according to claim 2, is characterized in that, described diode is the anti-paralleled diode that separate diode or described switching tube inside carry.
4. three-phase four-wire system three-level inverter according to claim 1, is characterized in that, the driving signal of four switching devices in described the first topology unit or the second topology unit is handed over to cut by sinusoidal modulation wave and triangular carrier and produced, and:
At the positive half period of described sinusoidal modulation wave, second switch break-over of device, the 4th switching device turn-offs, and if the level of described triangular carrier is less than the level of described sinusoidal modulation wave, the first switching device conducting, the 3rd switching device turn-offs; If the level of described triangular carrier is greater than the level of described sinusoidal modulation wave, the first switching device turn-offs, the 3rd switching device conducting;
Negative half-cycle at described sinusoidal modulation wave, the first switching device keeps off state, and the 3rd switching device keeps conducting state, and if the level of described triangular carrier is greater than the level of described sinusoidal modulation wave after oppositely, second switch break-over of device, the 4th switching device turn-offs; If the level of described triangular carrier is less than the level of described sinusoidal modulation wave after oppositely, second switch device turn-offs, the 4th switching device conducting.
5. three-phase four-wire system three-level inverter according to claim 1, is characterized in that, the output of any one topology unit in described four topology unit is as zero line, and the output of other three topology unit is as live wire.
6. according to the three-phase four-wire system three-level inverter described in claim 1 to 5 any one, it is characterized in that, also comprise:
Two dividing potential drop electric capacity, are connected in series between described DC power supply, for described DC power supply is carried out to dividing potential drop, and the dividing potential drop mid point that the tie point of described two dividing potential drop electric capacity is described DC power supply.
7. three-phase four-wire system three-level inverter according to claim 6, is characterized in that, the capacitive reactance of described two electric capacity is identical.
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| CN105305804B (en) * | 2014-07-22 | 2019-06-07 | 伊顿智能动力有限公司 | The driving guard method of T-type tri-level circuit and Drive Protecting Circuit |
| CN108649823A (en) * | 2018-06-26 | 2018-10-12 | 四川宏晶新能源汽车有限公司 | A kind of three-phase inverter using three-phase and four-line formula inversion topological |
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| CN101599713A (en) * | 2009-07-07 | 2009-12-09 | 华中科技大学 | A kind of three-level inverter of single-phase mixed bridge |
| CN102035423A (en) * | 2010-11-10 | 2011-04-27 | 上海兆能电力电子技术有限公司 | Three-phase four-wire three-level photovoltaic grid-connected connection inverter and control method thereof |
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| JP5205094B2 (en) * | 2008-03-24 | 2013-06-05 | 東芝三菱電機産業システム株式会社 | Inverter control device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101599713A (en) * | 2009-07-07 | 2009-12-09 | 华中科技大学 | A kind of three-level inverter of single-phase mixed bridge |
| CN102035423A (en) * | 2010-11-10 | 2011-04-27 | 上海兆能电力电子技术有限公司 | Three-phase four-wire three-level photovoltaic grid-connected connection inverter and control method thereof |
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