CN101866922A - GGNMOS device used in ESD protective circuit - Google Patents
GGNMOS device used in ESD protective circuit Download PDFInfo
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- CN101866922A CN101866922A CN201010172659A CN201010172659A CN101866922A CN 101866922 A CN101866922 A CN 101866922A CN 201010172659 A CN201010172659 A CN 201010172659A CN 201010172659 A CN201010172659 A CN 201010172659A CN 101866922 A CN101866922 A CN 101866922A
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Abstract
The invention provides a GGNMOS device used in an ESD protective circuit. The device comprises a substrate and a P trap region positioned on the substrate, wherein a plurality of drain electrode regions are arranged in the P trap region; the surface of the P trap region and two sides of the drain electrode regions are provided with grid electrode regions; the P trap region and the other sides of the grid electrode regions are provided with source electrode regions; P type doped regions are arranged among the source electrode regions; and a position below the source electrode regions and close to the source electrode regions is provided with an N trap region. The GGNMOS device used in the ESD protective circuit not only can solve non-uniform triggering problems, but also can solve the problems of resistance reduction, trigger voltage raising and difficult leakage of electrostatic current in a leakage path.
Description
Technical field
The present invention relates to esd protection circuit, relate in particular to a kind of GGNMOS device that is used for esd protection circuit.
Background technology
In integrated circuit (IC) chip manufacturing and final application system, along with improving constantly of very lagre scale integrated circuit (VLSIC) technology, the CMOS integrated circuit has entered the sub-micro stage at present, the MOS size of devices is constantly dwindled, gate oxide thickness is more and more thinner, its grid voltage endurance capability significantly descends, and (Electrostatic Discharge, ESD) harm to integrated circuit becomes more and more significant to static discharge.According to statistics, have 35% to be in the product of ic failure because the ESD problem is caused.Therefore, integrated circuit is carried out the esd protection design and also become particularly important.
Esd protection circuit is the discharge path that electrostatic induced current is provided for chip circuit, to avoid static internal circuit is punctured.Because static generally comes from the outside, for example human body, machine etc., so esd protection circuit is usually around the bond pad (PAD) of chip.The output bond pad generally links to each other with drive circuit, promptly link to each other with the drain region of NMOS pipe with large-sized PMOS, so this class device itself can be used for esd protection and discharge, and in order to insure, output also adds esd protection circuit generally speaking; And the input bond pad generally is connected on the gate regions of metal-oxide-semiconductor, therefore at the input of chip, must add esd protection circuit.In addition, on the power supply (Udd) of chip and ground (Uss) port, also to add esd protection circuit, can be discharged into Uss safely from Udd to guarantee the ESD electric current.
When using device that integrated circuit is carried out esd protection, device commonly used is gate regions grounding NMOS pipe (GGNMOS), GDPMOS (gate regions connects the P type metal-oxide-semiconductor of VDD power supply) and SCR (controllable silicon) or the like.Because GGNMOS and integrated circuit CMOS technology are well compatible, GGNMOS has obtained using widely.
Fig. 1 is a kind of GGNMOS device that is used for esd protection circuit in the prior art; as shown in Figure 1; comprise: substrate 1a; be positioned at the P well region 2a on the described substrate; the some drain region 7a that in described P well region 2a, are provided with; in the both sides of described drain region 7a and the gate regions 6a that is provided with of the surface of described P well region 2a; the source area 4a that in the opposite side of described gate regions 6a and described P well region 2a, is provided with, the P type doped region 5a that is positioned at the STI that the described source area 4a outside at edge is provided with (shallow trench isolation from) 3a and is positioned at the STI outside.Described drain region 7a and ESD input 8a are electrical connected, described source area 4a and described gate regions 6a ground connection, described P type doped region 5a ground connection.Described drain region 7a and ESD input 8a are electrical connected, described source area 4a, described gate regions 6a and described P type doped region 5a ground connection.
When ESD comes interim, electric current flows into described drain region 7a by ESD input 8a, described electric current flows through described P type doped region 5a by described P well region 2a, then produce voltage difference at described P well region 2a this moment, when voltage difference surpasses threshold voltage, (described source area 4a is equivalent to emitter region just to form the state of NPN triode conducting, described gate regions 6a is in the base, described drain region 7a is in collector area), this moment, electric current just flowed into described gate regions 6a from described drain region 7a, flow through described source area 4a at last and flow out, release ESD, avoided the electrostatic damage circuit like this.
As can see from Figure 1, this GGNMOS structure adopts many fingers transistor, and the NMOS that its structure is equivalent to a plurality of single fingers is connected in parallel, and has increased the area of esd protection.Yet, this GGNMOS structure can cause non-consistent triggering problem: the described P type doped region of drain region distance of the single finger NMOS in the middle of being positioned at is bigger than the distance to described P type doped region of single finger NMOS on every side, dead resistance in the leakage path of middle single finger NMOS is bigger than the dead resistance in the leakage path of single finger NMOS on every side, perhaps because technology out-of-flatness or resistance substrate are not of uniform size, cause conducting when the several finger NMOS of ESD stress certain or certain elder generation, cause electrostatic induced current to release from this finger, other fingers perform practically no function; Even ESD to flow through the current unevenness of each finger even, thereby reduced the transistorized esd protection circuit performance of many fingers.Even cause the damage of esd protection.
Fig. 2 is the another kind of GGNMOS device that is used for esd protection in the prior art; as shown in Figure 2; comprise: substrate 1b; be positioned at the P well region 2b on the described substrate; the some drain region 7b that in described P well region 2b, are provided with; in the both sides of described drain region 7b and the gate regions 6b that is provided with of the surface of described P well region 2b; the source area 4b that in the opposite side of described gate regions 6b and described P well region 2b, is provided with; P type doped region 5b between described source area, and be positioned at the STI that the described source area 4b outside at edge is provided with (shallow trench isolation from) 3b.Described drain region and ESD input are electrical connected, described source area and described gate regions ground connection, described P type doped region 5b ground connection.As we can see from the figure, same many fingers transistor arrangement that adopts, but this GGNMOS structure P doped region inserts between all source area ends, make the bleeder resistance of leakage path of each single finger NMOS identical, this structure can be separated consistent by no means triggering problem, but greatly reduce length at the leakage path of P well region, reduced the dead resistance in the leakage path, and then reduced voltage difference in the P well region, have only then that bigger electrostatic current is fashionable just to reach threshold voltage, could so that conducting, leak away static, therefore, this causes the raising greatly of trigger voltage again, the antileakaging problem of electrostatic induced current.
In sum, need provide a kind of GGNMOS device that is used for esd protection can separate consistent by no means triggering problem, can solve the problem that resistance reduces in the leakage path, trigger voltage raises again.
Summary of the invention
The present invention will solve the non-consistent triggering problem of the GGNMOS device that is used for esd protection in the prior art and solve resistance reduction in the leakage path, trigger voltage rising, the antileakaging problem of electrostatic induced current.
For addressing the above problem; the invention provides a kind of GGNMOS device that is used for esd protection; comprise: substrate; be positioned at the P well region on the described substrate, the some drain regions that are provided with in described P well region are in the both sides of described drain region and the gate regions that is provided with of the surface of described P well region; the source area that in the opposite side of described gate regions and described P well region, is provided with; the P type doped region that between described source area, is provided with, below described source area, the N well region that adjacent described source area place is provided with.
Further, described drain region and ESD input are electrical connected, described source area, described gate regions ground connection and described P type doped region ground connection.
Further, in described GGNMOS device edge, described N trap, also be provided with sti structure.
Further, the doping content of described P well region is 10
12/ cm
2～10
13/ cm
2
Further, the doping content of described N well region is 10
12/ cm
2～10
13/ cm
2
Further, the concentration of described P type doped region is 10
12/ cm
2～10
13/ cm
2
Preferably, the degree of depth of described N well region equals the degree of depth of described source area.
Preferably, the width of described N well region equals the width of described source area.
Further, the degree of depth of described P well region equals described N well region and source area degree of depth sum.
Preferably, the width of described P type doped region is the minimum widith that satisfies technological requirement.
Description of drawings
Fig. 1 is a kind of GGNMOS device that is used for esd protection circuit in the prior art.
Fig. 2 is the another kind of GGNMOS device that is used for esd protection in the prior art.
Fig. 3 is a kind of GGNMOS device that is used for esd protection among the present invention.
Embodiment
For making content of the present invention clear more understandable, below in conjunction with Figure of description, the content novel to the present invention is described further.Certainly the present invention is not limited to this specific embodiment, and the known general replacement of the common and personnel that say in this area also is encompassed in protection scope of the present invention.
Secondly, the present invention utilizes schematic diagram to carry out detailed statement, and when example of the present invention was described in detail in detail, for convenience of explanation, schematic diagram did not amplify according to general ratio is local, should be with this as limitation of the invention.
Central idea of the present invention is, P type doped region is set between described source area can solves consistency problem, under described source area, the position of adjacent source area is provided with the N well region simultaneously, improve the resistance in the leakage path, thereby solve the problem that trigger voltage raises.
The present invention proposes a kind of GGNMOS device that is used for esd protection; comprise: substrate 1; be positioned at the P well region 2 on the described substrate 1; the some drain regions 7 that in described P well region 2, are provided with; in the both sides of described drain region 7 and the gate regions 6 that is provided with of the surface of described P well region 2, the source area 4 that in the opposite side of described gate regions 6 and described P well region 2, is provided with, the P type doped region 5 that between described source area 4, is provided with; below described source area 4, the N well region 9 that adjacent described source area 4 places are provided with.
Further, described drain region 7 is electrical connected described source area 4, described gate regions 6 ground connection and described P type doped region 5 ground connection with ESD input 8.
In the present embodiment, described P well region 1 mixes for boron, and doping content is 10
12/ cm
2～10
13/ cm
2Described N well region 9 is a phosphorus doping, and doping content is 10
12/ cm
2～10
13/ cm
2, described P type doped region 5 mixes for boron, and doping content is 10
12/ cm
2～10
13/ cm
2Adopt above-mentioned doping content, meet technological requirement, can effectively improve the dead resistance of leakage path.
Preferably, the degree of depth of described N well region 9 equals the degree of depth of described source area 4.
Preferably, the width of described N well region 9 equals the width of described source area 4.
Further, the degree of depth of described P well region 1 equals described N well region 9 and described source area 4 degree of depth sums.
Preferably, the width of described P type doped region 5 is the minimum widith that satisfies technological requirement.The width of above-mentioned doped region and the degree of depth are under the situation that satisfies the GGNMOS performance, are convenient to the technology manufacturing.
Further.The doping content that source area is arranged of described GGNMOS device, doping area and doping thickness change with technology, requirement on devices, and other doped regions all change with requirement on devices, do not limit in an embodiment.
In sum, when ESD comes interim, electric current flows into described drain region 7 by ESD input 8, described electric current flows through described P type doped region 5 by described P well region 2, owing in the described P well region 2 dead resistance is arranged, the electric current of then flowing through produces voltage difference in described P well region 2, when voltage difference surpasses threshold voltage, just form the state (described source area 4 is equivalent to emitter region, and described gate regions 6 is in the base, and described drain region 7 is in collector area) of NPN triode conducting, this moment, electric current just flowed into described gate regions from described drain region, flow through described source area 4 at last and flow out, release static, avoided the electrostatic damage circuit like this.In the utility model, the described GGNMOS device that is used for esd protection has many fingers NMOS structure, its structure is connected in parallel with regard to the NMOS that is equivalent to a plurality of single fingers, P type doped region 5 is set between described source area 4, make the leakage path length of each single finger NMOS identical, and then can solve consistency problem; Simultaneously under described source area 4, the position of adjacent source area 4 is provided with N well region 9, make the leakage of electric current walk around described N well region 9 from needs drain region 7 and flow into P type doped region 5, increased the length of leakage path like this, improve the parasitic resistance values of leakage path, and then improve voltage difference, thereby less relatively static can make described GGNMOS conducting, discharging static, trigger voltage raises, the antileakaging problem of static thereby solve.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; have in the technical field under any and know the knowledgeable usually; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (10)
1. GGNMOS device that is used for esd protection; it is characterized in that; comprise: substrate; be positioned at the P well region on the described substrate; the some drain regions that in described P well region, are provided with, the gate regions that is provided with in the both sides of described P well region surface, described drain region is in described P well region, the source area that is provided with of the opposite side of described gate regions; the P type doped region that is provided with between described source area is below described source area, the N well region that is provided with of adjacent described source area.
2. the GGNMOS device that is used for esd protection as claimed in claim 1 is characterized in that described drain region and ESD input are electrical connected, described source area, described gate regions and described P type doped region ground connection.
3. the GGNMOS device that is used for esd protection as claimed in claim 1 is characterized in that, also is provided with sti structure in described GGNMOS device edge, described N trap.
4. the GGNMOS device that is used for esd protection as claimed in claim 1 is characterized in that the doping content of described P well region is 10
12/ cm
2～10
13/ cm
2
5. the GGNMOS device that is used for esd protection as claimed in claim 1 is characterized in that the doping content of described N well region is 10
12/ cm
2～10
13/ cm
2
6. the GGNMOS device that is used for esd protection as claimed in claim 1 is characterized in that the concentration of described P type doped region is 10
12/ cm
2～10
13/ cm
2
7. the GGNMOS device that is used for esd protection as claimed in claim 1 is characterized in that the degree of depth of described N well region equals the degree of depth of described source area.
8. the GGNMOS device that is used for esd protection as claimed in claim 1 is characterized in that the width of described N well region equals the width of described source area.
9. the GGNMOS device that is used for esd protection as claimed in claim 1 is characterized in that, the degree of depth of described P well region equals described N well region and described source area degree of depth sum.
10. the GGNMOS device that is used for esd protection as claimed in claim 1 is characterized in that the width of described P type doped region is the minimum widith that satisfies technological requirement.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010172659.7A CN101866922B (en) | 2010-05-12 | 2010-05-12 | GGNMOS device used in ESD protective circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010172659.7A CN101866922B (en) | 2010-05-12 | 2010-05-12 | GGNMOS device used in ESD protective circuit |
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| Publication Number | Publication Date |
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| CN101866922A true CN101866922A (en) | 2010-10-20 |
| CN101866922B CN101866922B (en) | 2015-01-07 |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102646601A (en) * | 2012-04-19 | 2012-08-22 | 中国科学院微电子研究所 | Semiconductor structure and manufacturing method thereof |
| CN103094271A (en) * | 2011-11-01 | 2013-05-08 | 中芯国际集成电路制造(上海)有限公司 | Static discharge protection circuit |
| CN103872039A (en) * | 2012-12-11 | 2014-06-18 | 中芯国际集成电路制造(上海)有限公司 | Electrostatic discharge protection circuit and manufacturing method thereof |
| CN104916631A (en) * | 2014-03-11 | 2015-09-16 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacturing method thereof, and electronic apparatus |
| CN105489503A (en) * | 2016-01-27 | 2016-04-13 | 上海华虹宏力半导体制造有限公司 | Semiconductor structure, forming method thereof, and electrostatic protection circuit |
| US20240030215A1 (en) * | 2022-07-25 | 2024-01-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strap technology to improve esd hbm performance |
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| CN1983588A (en) * | 2005-12-13 | 2007-06-20 | 上海华虹Nec电子有限公司 | Anti-electrostatic protecting structure by NMOS |
| US20070159754A1 (en) * | 2006-01-12 | 2007-07-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Circuit system for protecting thin dielectric devices from ESD induced damages |
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Patent Citations (3)
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| CN101283452A (en) * | 2005-10-06 | 2008-10-08 | Nxp股份有限公司 | Electrostatic discharge protection device |
| CN1983588A (en) * | 2005-12-13 | 2007-06-20 | 上海华虹Nec电子有限公司 | Anti-electrostatic protecting structure by NMOS |
| US20070159754A1 (en) * | 2006-01-12 | 2007-07-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Circuit system for protecting thin dielectric devices from ESD induced damages |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103094271A (en) * | 2011-11-01 | 2013-05-08 | 中芯国际集成电路制造(上海)有限公司 | Static discharge protection circuit |
| CN103094271B (en) * | 2011-11-01 | 2016-04-06 | 中芯国际集成电路制造(上海)有限公司 | A kind of ESD protection circuit |
| CN102646601A (en) * | 2012-04-19 | 2012-08-22 | 中国科学院微电子研究所 | Semiconductor structure and manufacturing method thereof |
| CN102646601B (en) * | 2012-04-19 | 2016-09-28 | 北京燕东微电子有限公司 | A kind of semiconductor structure and manufacture method thereof |
| CN103872039A (en) * | 2012-12-11 | 2014-06-18 | 中芯国际集成电路制造(上海)有限公司 | Electrostatic discharge protection circuit and manufacturing method thereof |
| CN103872039B (en) * | 2012-12-11 | 2016-04-06 | 中芯国际集成电路制造(上海)有限公司 | The manufacture method of ESD protection circuit |
| CN104916631A (en) * | 2014-03-11 | 2015-09-16 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacturing method thereof, and electronic apparatus |
| CN104916631B (en) * | 2014-03-11 | 2020-01-03 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, manufacturing method thereof and electronic device |
| CN105489503A (en) * | 2016-01-27 | 2016-04-13 | 上海华虹宏力半导体制造有限公司 | Semiconductor structure, forming method thereof, and electrostatic protection circuit |
| CN105489503B (en) * | 2016-01-27 | 2018-08-10 | 上海华虹宏力半导体制造有限公司 | Semiconductor structure and forming method thereof, electrostatic discharge protective circuit |
| US20240030215A1 (en) * | 2022-07-25 | 2024-01-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strap technology to improve esd hbm performance |
| US12132042B2 (en) * | 2022-07-25 | 2024-10-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strap technology to improve ESD HBM performance |
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| Publication number | Publication date |
|---|---|
| CN101866922B (en) | 2015-01-07 |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI Effective date: 20140514 |
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