CN101494090B

CN101494090B - Memory access control method

Info

Publication number: CN101494090B
Application number: CN200810004694.0A
Authority: CN
Inventors: 宁树梁; 刘维理
Original assignee: Nanya Technology Corp
Current assignee: Nanya Technology Corp
Priority date: 2008-01-21
Filing date: 2008-01-21
Publication date: 2014-03-19
Anticipated expiration: 2028-01-21
Also published as: CN101494090A

Abstract

The invention provides a memory control method. A read write command is decoded to generate a mode memory setup signal; when the mode memory setup signal is enabled, a flip-latch outputs a memory vault selection signal; afterwards, the memory vault selection signal is decoded to generate a register selection signal. The register selection signal can select a register so as to write an address signal into the selected register. And the value of a certain register can be used for determining whether an error checking function is enabled. Therefore, the next-generation memory framework which supports the CRC function can be compatible with the original memory framework.

Description

Memory access control method

Technical field

The invention relates to a kind of memory access control method, and particularly relevant for a kind of determine whether carry out Cyclical Redundancy Check memory access control method of (cyclic redundancy check, CRC).

Background technology

In communication system or computer system, can utilize Cyclical Redundancy Check (cyclic redundancy check, CRC) to improve bug check ability.After data transmission or data storing, CRC can be used for checking whether make a mistake in data transmission procedure.In data transmission procedure, receiving/send out both sides all needs to carry out CRC computing, and the CRC operation result of then being calculated by one party comparison both sides, can learn that whether received data are wrong.

Along with the transfer speed of data of computer system is more and more faster, existing memory architecture cannot ensure the data transmission accuracy of storer.Therefore, in follow-on memory architecture, can use crc error audit function in memory access, to guarantee the correct of data transmission.But legacy memory framework also cannot be supported crc error audit function, makes to support that the memory architecture of future generation of crc error audit function cannot upwards be compatible to existing memory architecture.

Namely, if use the memory architecture of future generation of supporting crc error audit function and the existing memory architecture that cannot support crc error audit function in same computer system simultaneously, must close the CRC function of memory architecture of future generation, otherwise System Operation has problem.

On the other hand, if all use the memory architecture of future generation that can support crc error audit function in same computer system, preferably can start CRC function, to increase system effectiveness.

Summary of the invention

The present invention is a kind of memory access control method, cannot upwards be compatible to the problem of old memory transfer framework in order to solve the storer that contains CRC function.

One of example of the present invention provides a kind of memory control methods, comprising: decoding one read write command is deposited setting signal to produce a pattern; When this pattern is deposited setting signal and is activation, decoding one data base is selected signal, to produce a register selection signal; According to this register selection signal, from a plurality of registers, select at least one register, and an address signal is written to selecteed this register; And according to the value of selecteed this register, whether to determine activation one error checking function.

Comprehensively the above, when the present invention cannot support CRC function at old memory transfer framework, can close CRC unit, makes storer can upwards be compatible to old memory transfer framework.Or when memory transfer framework is supported CRC function, can open CRC unit, keep due system effectiveness.

Accompanying drawing explanation

For above-mentioned purpose of the present invention, feature and advantage can be become apparent, below in conjunction with accompanying drawing, the specific embodiment of the present invention is elaborated, wherein:

Fig. 1 is the rough schematic view of storer 100.

Fig. 2 is the control calcspar according to storer 100 inside of the embodiment of the present invention.

Fig. 3 is instruction decoder 220 sequential schematic diagram.

Main element symbol description:

100: storer

210: receiving element

220: instruction decoder

230: latch

240,250: demoder

260-0,260-1: group of registers

260-1a: register

270:CRC unit

ADD_BUS: address bus

ADD<0:12>: address signal

BS<0:1>: data base is selected signal

rwo address strobe signals

CMD_BUS: instruction bus

CLK: clock signal

CRC_EN:CRC function enable signal

CRC_V: error checking function operation result

DQ: data bus

MRS: pattern is deposited setting signal

: column address gating signal

SEL, SELp0, SELp1: register selection signal

VSS, VDD: power supply

write enable signal

CS: chip enable signal

Embodiment

In embodiments of the present invention, disclose a kind of memory control methods and memory architecture, can optionally determine whether to start/close the CRC function of memory architecture of future generation.Preferably, when all memory module all can be supported CRC function in system, just start CRC function, to increase system effectiveness.That is to say, as long as while having a memory module can not support CRC function, had better not start CRC function in system, make mistakes avoiding.

Please refer to Fig. 1, the rough schematic view of its display-memory 100, certainly, storer 100 also has other I/O pins, but is simplified illustration, and other I/O pins do not demonstrate.

As shown in Figure 1, the I/O pin of storer 100 at least comprises: address pin, its address signal on can receiver address bus ADD_BUS; Instruction pin, it can receive instruction bus CMD_BUS and (comprise

and CS) command signal on; Two power pins, receive respectively power vd D and VSS; Clock pulse pin, receives clock signal CLK; And data pin, receive data bus DQ.

Storer 100 will, according to received address signal and instruction signal, determine whether activation error checking function CRC.At error checking function CRC, be not enabled under Qing Indistinct, data bus DQ can output error audit function operation result CRC_V; In the situation that error checking function CRC is enabled, data bus DQ can output error audit function operation result CRC_V.

Fig. 2 is the storer 100 internal control calcspars according to the embodiment of the present invention, and it can determine whether start CRC function.At this, take address signal ADD<0:12> as 13, and data base to select signal BS<0:1> to be 2 be example explanation.Certainly, the present embodiment is not limited to this.

Receiving element 210 is accepted address signal on clock signal CLK, address bus ADD_BUS and the command signal on instruction bus CMD_BUS.Particularly, receiving element 210 will decode address signal ADD<0:12> and data base selection signal BS<0:1> by address bus ADD_BUS.In addition, receiving element 210 can be by the address gating signal in column of the signal decoding on instruction bus CMD_BUS

(row address strobe), rwo address strobe signals ,-

(column address strobe), write enable signal

(write enable) and chip enable signal CS (chip selected).

220 pairs of column address gating signals of instruction decoder

rwo address strobe signals

write enable signal WE and chip enable signal CS decodes, to produce a plurality of signals, one of them signal is called pattern and deposits setting signal MRS.This pattern is deposited setting signal MRS and is used to activation latch 230.Please refer to Fig. 3, its display column address gating signal

rwo address strobe signals

write enable signal

deposit the sequential chart of setting signal MRS with pattern.As shown in Figure 3, work as column address gating signal

rwo address strobe signals

with write enable signal

be all logic low and chip enable signal CS and be logic when high, it is activation that pattern is deposited setting signal MRS.Certainly, the present embodiment is not limited to this.

Latch 230 more can receiver address signal ADD<0:12>, data base selection signal BS<0:1>.Such as, when pattern is deposited setting signal MRS and is activation, address signal ADD<0:12> and data base that latch 230 outputs are latched are selected signal BS<0:1>.

Demoder 240 selects signal BS<0:1> to be decoded into register selection signal SEL<0:3> data base.

Demoder 250 is decoded into register selection signal SELp0, SELp1 by register selection signal SEL<0:3> ...Those register selection signal SELp0, SELp1 ... can be used for activation group of registers 260-0,260-1 ...

At this, the group of registers of take comprises that 13 registers explain as example.Address signal ADD<0:12> can be written into the group of registers being enabled.Such as, when group of registers 260-1 is enabled, address signal ADD<0:12> can write 13 registers in group of registers 260-1 so far.

In the present embodiment, whether the output valve of a certain register can be treated as CRC function enable signal CRC_EN, to control CRC function, be enabled.This register is such as depositing setting (MRS, mode register setting) register 260-1a for the pattern in group of registers 260-1.

CRC unit 270 can receive data DQ, and it is carried out to CRC computing, to produce error checking function operation result CRC_V.When this CRC function enable signal CRC_EN is activation, can activation CRC unit 270, to make CRC unit 270 produce error checking function operation result CRC_V.Relative, when this CRC function enable signal CRC_EN is anergy, can anergy CRC unit 270, to make CRC unit 270 not produce error checking function operation result CRC_V.Certainly, CRC function enable signal CRC_EN is other I/O circuit in writable control storage 100 also, to make the data output of storer 100 can be not wrong.

The embodiment of the present invention can be applicable to high speed/big data quantity storer (such as, DDR4) in, to make it be compatible to old memory architecture.

Although the present invention discloses as above with preferred embodiment; so it is not in order to limit the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; when doing a little modification and perfect, so protection scope of the present invention is worked as with being as the criterion that claims were defined.

Claims

1. a memory control methods, is suitable for being applied in an accumulator system, and this accumulator system comprises a plurality of memory modules, and this memory control methods comprises:

The read write command of decoding is deposited setting signal to produce a pattern;

When this pattern is deposited setting signal and is activation, decoding one data base is selected signal, to produce a register selection signal;

According to this register selection signal activation one group of registers, and an address signal is written to a plurality of registers in this group of registers being enabled, the output valve of the one of wherein said register is as an enable signal; And

According to the Determines of this enable signal activation one error checking function whether,

When wherein all memory modules all can be supported this error checking function in this accumulator system, start this error checking function; And

While having at least a memory module can not support this error checking function, do not start this error checking function in this accumulator system.

2. memory control methods as claimed in claim 1, characterized by further comprising:

The signal of decoding on an address bus, selects signal to produce this address signal and this data base.

3. memory control methods as claimed in claim 1 or 2, characterized by further comprising:

The signal of decoding on an instruction bus, to produce this read write command.

4. memory control methods as claimed in claim 3, is characterized in that, this read write command at least comprises: a column address gating signal, a rwo address strobe signals, a chip enable signal and write enable signal.

5. memory control methods as claimed in claim 4, is characterized in that, when this column address gating signal, this rwo address strobe signals, this chip enable signal and this write enable signal, is all logic when high, and it is activation that this pattern is deposited setting signal.

6. memory control methods as claimed in claim 1, characterized by further comprising:

Latch this address signal and this data base and select signal; And

When this pattern is deposited setting signal and is activation, this address signal that output is latched and this data base selection signal.

7. memory control methods as claimed in claim 5, characterized by further comprising:

Latch this address signal and this data base and select signal; And