CN101350709B - Method and device for synchronizing block and frame - Google Patents
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Abstract
The present invention relates to the field of communication, and discloses a block and frame synchronization method, and a device thereof. When the input error rate is relatively high, the synchronization can be completed more accurately. In the method, N bit groups are detected; the times of the appearance of bit segments with the same position as the block synchronization head in each bit group is summarized; if only the statistic value of one position is more than the first threshold, the position can be used for arranging the block synchronization head. The receiving sequences which consist of M block synchronization heads are displaced for times of M minus 1 in a circular way, so as to acquire various possible results of the circular displacement of the receiving sequence; the relevant calculation of the results of the circular displacement and the reference sequence is completed; the relevant values can be used for quantitative indication of the degree of proximity between the results of the circular displacement and the reference sequence; the relevant values of K bit groups corresponding to the times of the circular displacement are summarized, so as to reliably acquire the result of the circular displacement which is closest to the reference sequence, and further to accurately acquire the position of the frame.
Description
Technical Field
The invention relates to the field of communication, in particular to a block and frame synchronization technology.
Background
An Ethernet Passive Optical Network (EPON) access technology is a better access technology, and has the main advantages of simple maintenance, low cost, high transmission bandwidth and high cost performance.
However, since EPON is a technology that employs passive optical transmission, components having amplification and relay functions are not used in this network. The transmission distance and the number of branches of an EPON network depend on the power budget and various transmission losses. As the transmission distance or the number of branches increases, the Signal to Noise Ratio (SNR) of the transmission data gradually decreases, and the error rate of the transmission data gradually increases. In order to solve the problem, a Forward Error Correction (FEC) technology is introduced into the EPON system to improve the interference rejection of the system, thereby increasing the power budget of the system.
However, 64b/66b and 64b/65b are two line coding mechanisms with higher coding efficiency, and a scrambling mode with non-scrambling code synchronous characters and control characters is used. In the Physical Coding Sublayer (PCS for short) of the EPON system, a line Coding technique is used to improve the accuracy of data transmission.
The FEC frame structure scheme is shown in fig. 1, and data entering the PCS layer is first subjected to 64b/66b line coding to form a line coding block with 66 bits as a unit. The 64b/66b coding scheme is based on 64-bit data information, and adds a 2-bit synchronization header. The 2-bit sync header has only two possibilities of "01" or "10". Wherein, the synchronization header is "01" to indicate that 64 bits are all data information; the synchronous head is 10, which means that 64 bits of information contains data information and control information; and the synchronization header is "00" or "11" to indicate that an error occurs in the transmission process. At the receiving end, a two-bit "01" or "10" synchronization header in 64b/66b line coding is needed to implement 64b/66b line coding block synchronization (block synchronization) in order to judge the type of data in the line coding block according to the synchronization header, and then to implement frame synchronization (frame synchronization) in order to facilitate subsequent decoding of FEC.
The implementation principles of block synchronization and FEC codeword information frame synchronization in the prior art are as follows:
the block synchronization principle is as follows: at the receiving end, a buffer register with the length of 66 bits is set, and all the positions in the buffer register are initialized to be set to be True before synchronization begins. Then, the input bit data is compared with the bit data before the input bit data, and if the 2-bit data is the same, the corresponding position in the buffer register is set to "false". Since the 2-bit data of the sync header of the 64b/66b code block will only be different, when a certain number of data are inputted, the value of a certain position of the buffer register is always "True", and then the position is determined as the position where the sync header of the 64b/66b code block starts, thereby realizing block synchronization.
The FEC frame synchronization process is similar to the block synchronization process, except that the length of the buffer register is increased to the length of one FEC frame. Before synchronization, all positions of the buffer register are set as 'True', input bit data are compared with bit data before the buffer register, and the position of the buffer register, the value of which is always 'True', can be determined to be the position of a synchronization head by utilizing the characteristic that 64b/66b coding block synchronization heads are different and the characteristic that a check block synchronization head is the same, so that the FEC information frame synchronization is realized.
In addition, a relatively simple FEC information frame synchronization method is provided, the method only scans the synchronization head of the check information block in the FEC frame, and since the 2-bit synchronization head of the check information block is always the same, the value at the corresponding position of the buffer register will always be true, so that the start position of the check information block is determined, and the FEC frame synchronization is realized by determining the start position of the FEC frame.
If the synchronization of one of the 64b/66b line coding blocks or the FEC check information block is incorrect, the buffer register may not have a "True" status, and the block synchronization or FEC frame synchronization cannot be completed. The solution is generally taken by reinitializing the cache register and then resuming the synchronization operation. However, the inventor of the present invention finds that when the interference in the channel is strong, the error rate of the received data is high, so that the probability of the error of the synchronization header is also high, and the synchronization cannot be accurately completed, even cannot be realized. In addition, when the synchronization header is wrong, the synchronization operation can be performed only after reinitialization, so that the time delay is increased, and the performance of the system is influenced.
Disclosure of Invention
The main technical problem to be solved by the embodiments of the present invention is to provide a block and frame synchronization method and apparatus, so that when the input error rate is relatively high, synchronization can be completed more accurately.
In order to solve the above technical problem, an embodiment of the present invention provides a block synchronization method, including the following steps:
initializing L counters, wherein each counter corresponds to a position in a bit group with the length of L, a block synchronization head appears at one of the L positions corresponding to the L counters, and L is more than 1;
detecting N bit groups, wherein the length of each bit group is L, if a bit segment which is the same as one of the preset block synchronization heads is detected, selecting a counter corresponding to the position of the bit segment from the L counters, and increasing the count value of the selected counter; n is more than 1;
if the count value of only one counter in the L counters is greater than a first threshold, the position corresponding to the counter is judged as the position of the block synchronization head; where the block is L bits long.
An embodiment of the present invention further provides a block synchronization apparatus, including:
l counters, each counter corresponding to a position in a bit group with length L, the block synchronization head appearing at one of the L positions corresponding to the L counters, L > 1;
the detection module is used for detecting N bit groups, the length of each bit group is L, if a bit segment which is the same as one of the preset block synchronization heads is detected, a counter corresponding to the position of the bit segment is selected from the L counters, and the selected counter is indicated to increase the count value;
the initialization module is used for initializing the L counters before the detection module detects the counters;
the block synchronization decision device is used for judging whether the count value of only one counter in the L counters is greater than a first threshold after the detection module finishes the detection, and if so, determining the position corresponding to the counter as the position of the block synchronization head;
wherein the block length is L bits, and N > 1.
The embodiment of the invention also provides a frame synchronization method, each frame is composed of M blocks, M is more than 1, and the method comprises the following steps:
detecting K bit groups, wherein each bit group comprises M blocks, when each bit group is detected, reading a block synchronization head of the M blocks in the bit group to form a receiving sequence, performing all possible cyclic shifts on the receiving sequence by taking the length of the block synchronization head as a unit, performing correlation operation on all possible arrangements of the receiving sequence subjected to the cyclic shift and a reference sequence, and recording a correlation value obtained by each correlation operation, wherein K is more than 1;
adding correlation values corresponding to the same cyclic shift times in the K bit groups to obtain M correlation sums;
and if only one correlation sum is larger than the second threshold, obtaining the position of the frame header according to the corresponding circular shift times of the correlation sum.
An embodiment of the present invention further provides a frame synchronization apparatus, including:
the detection unit is used for detecting K bit groups, each bit group comprises M blocks, when each bit group is detected, a block synchronization head reading the M blocks in the bit group forms a receiving sequence, all possible cyclic shifts are carried out on the receiving sequence by taking the length of the block synchronization head as a unit, all possible arrangements of the receiving sequence subjected to the cyclic shifts and a reference sequence are subjected to correlation operation, correlation values obtained by each correlation operation are recorded, K is greater than 1, and M is greater than 1;
the accumulator is used for adding correlation values corresponding to the same cyclic shift times in the K bit groups obtained by the detection unit to obtain M correlation sums;
m registers, which are used to store M correlation sums obtained by the accumulator;
and the frame synchronization judger is used for judging whether only one correlation sum in the M registers is larger than a second threshold, and if so, obtaining the position of the frame header according to the corresponding cycle shift times of the correlation sum.
Compared with the prior art, the implementation mode of the invention has the main differences and the effects that:
detecting N bit groups, counting the times of occurrence of bit segments which are the same as the block synchronization head at each position in each bit group, and if the statistical value of only one position is greater than a first threshold, the position is the position of the block synchronization head. When the input error rate is high, the statistical values of all positions are only relatively close, but the probability that the statistical value of the position of the block synchronization head is obviously larger than that of other positions is still very high, so that the synchronization can still be accurately finished.
Drawings
Fig. 1 is a diagram illustrating a FEC information frame structure in the prior art;
FIG. 2 is a flow chart of a block synchronization method according to a first embodiment of the present invention;
FIG. 3 is a schematic diagram of a block synchronization apparatus according to a second embodiment of the present invention;
FIG. 4 is a flow chart of a block synchronization method according to a third embodiment of the present invention;
fig. 5 is a schematic diagram of an FEC information frame structure for performing block synchronization according to a third embodiment of the present invention;
FIG. 6 is a flow chart of a block synchronization method according to a third embodiment of the present invention;
FIG. 7 is a schematic diagram of a block synchronization apparatus according to a fourth embodiment of the present invention;
fig. 8 is a schematic diagram of a frame synchronization method according to a fifth embodiment of the present invention;
fig. 9 is a flowchart of a frame synchronization method according to a fifth embodiment of the present invention;
fig. 10 is a schematic diagram illustrating a principle of a synchronization correlation operation for frame synchronization according to a fifth embodiment of the present invention;
fig. 11 is a schematic structural diagram of a frame synchronization apparatus according to a sixth embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
The first embodiment of the present invention relates to a block synchronization method, in which a block synchronization header of each block in a received data stream is 2 bits, and a preset block synchronization header is "10" or "01". Where the block is L bits long, for example, 66 bits long (i.e., L ═ 66), L counters are set in the system accordingly, that is, 66 counters are set. When block synchronization is carried out, the data stream of N bit groups is detected by taking L bits as a bit group, wherein L counters respectively correspond to a possible block synchronization head position in one bit group. The specific flow of the block synchronization method is shown in fig. 2.
In step 201, at the start of synchronization, L (L ═ 66) counters are initialized, that is, all of the 66 counters Bff _ cnt [ a% L ] are cleared, where a is L, Bff _ cnt [0] points to the lth counter, the Block counter Block _ cnt is set to zero, and the value of the variable Block _ lock indicating the synchronization state is set to "false", that is, "Block _ lock < ═ false". Wherein a% L represents a modulo L of a, and when a is less than or equal to L, a% L is a; when a is greater than L, then a% L is equal to the remainder of L divided by a.
In step 202, each bit in the N bit groups is scan-detected, in this embodiment, the preset Block sync header is "10" or "01", so it is only necessary to determine whether the value of the a-th bit in the scanned bit group is different from that of the a + 1-th bit, that is, an if (input [ a ] | ═ input [ a +1]) statement is executed for each bit group, where the function input [ a ] indicates to read the data of the a-th bit in the bit group indicated by Block _ cnt in the input data stream, and thus the statement indicates to determine whether the data of the a-th bit in the bit group indicated by Block _ cnt at present is different from that of the a + 1-th bit, and by simply determining whether the data of two bits are different from each other, it is possible to quickly determine whether two adjacent bits are one of the preset Block sync headers. If the two bit data values are different, the value of if (input [ a ] | ═ input [ a +1]) statement is "true", step 203 is entered, the count value of the counter Bff _ cnt [ a% L ] corresponding to the position of the bit segment is added by 1, and then step 204 is entered; otherwise, the value of the if (input [ a ] | ═ input [ a +1]) statement is "false", the counter Bff _ cnt [ a% L ] does not operate, that is, the count value is not changed, and the process proceeds to step 204 directly.
In step 204, determining whether a% L is 0, only when a is L, the value of a% L is 0, and if the value of a% L is 0, it indicates that each bit in the current bit group is compared with its adjacent bit, proceeding to step 205, adding 1 to the Block counter Block _ cnt so that data of the next bit group can be scanned, and then proceeding to step 206; if the value of a% L is not 0, it indicates that the comparison between each bit in the group of bits and its adjacent bits has not been completed, the Block counter Block _ cnt value is not changed, the scanning of the group of bits will continue, and step 206 is directly entered.
In step 206, it is determined whether the Block _ cnt value of the Block counter is greater than or equal to N, if the Block _ cnt value is less than N, step 207 is entered, a is set to "a + 1", and then step 202 is entered; if the Block _ cnt value is greater than or equal to N, it indicates that the scanning of the N bit groups is completed, and the process proceeds to step 208.
In step 208, it is determined whether the count value of only one of the L counters is greater than a block threshold value (B _ threshold), where B _ threshold is equal to N — block offset value (B _ offset), and B _ offset can be determined according to a preset error rate of the block, where the higher the preset error rate is, the larger the B _ offset value is. Different input error rates can be accommodated by flexibly setting the B _ offset.
If the count values of all the L counters are less than or equal to B _ threshold, or the count values of at least two of the L counters are greater than B _ threshold, returning to step 201 according to the Block _ lock value being "false", and performing the Block synchronization operation again to perform the synchronization detection on the subsequent data stream; if the count value of only one of the L counters is greater than B _ threshold, step 209 is entered, a statement "Block _ lock ≦ true" is executed, the variable Block _ lock is set to true, "the synchronization of the decision Block is completed, and the position corresponding to the counter is determined as the position of the Block synchronization header. In the process, the counter is used for realizing statistics, when the input error rate is higher, the statistics of each position are only relatively close, but the probability that the statistics of the position of the block synchronization head is obviously greater than the statistics of other positions is still very high, so that the synchronization can still be accurately finished through the implementation mode.
The specific process of detection and judgment in the present embodiment is as follows:
the input data of 66 bits of the 1 st group is detected and analyzed, and the specific detection and analysis process is as follows: comparing the value of the 2 nd bit of the group with the value of the 1 st bit, if the values of the values are different and are 10 or 01, indicating that the bit segment formed by the 1 st bit of the 1 st group and the 2 nd bit of the 1 st group is the same as the preset block synchronization head, and adding 1 to the 1 st counter; if the values of the counter and the counter are the same and are "00" or "11", it indicates that the bit segment composed of the 1 st bit of the 1 st group and the 2 nd bit of the 1 st group is different from the preset block synchronization header, and then the value of the 1 st counter is kept unchanged. Then, the value of the 3 rd bit of the group is compared with the value of the 2 nd bit in sequence, if the values of the 3 rd bit and the 2 nd bit are different, the 2 nd counter is added with 1; if they take the same value, the value of the 2 nd counter is unchanged. And by analogy, the data of 66 bits in the 1 st group are sequentially subjected to detection analysis.
When a is 66, a +1 is 67, the 66 th bit and the 67 th bit of the received data are compared, and if the values of the bits are different, the 66 th counter is increased by 1 (when a is L, Bff _ cnt [ a% L ], that is, Bff _ cnt [0] points to the lth counter); if they take the same value, the value of the 66 th counter is unchanged. Then, when a is 67 and a +1 is 68, the data of the 67 th bit and the 68 th bit are compared, and if the values of the bits are different, the value of the 1 st counter pointed by Bff _ cnt [ a% L ] is increased by 1; if they take the same value, the value of the 1 st counter remains unchanged. It is easy to understand that the scan analysis of the 66 × N bit data of the N bit groups may be performed sequentially by the above-described method.
Experiments prove that: when the value of N is 30, the value of B _ offset is 4, and the Bit Error Rate (BER for short) of channel coding is 10-3In time, the probability of correct synchronization can reach 99.8% by adopting the embodiment, and the probability of correct synchronization by adopting the prior art scheme is 94.2%; when the value of N is 60, the value of B _ offset is 5, and the channel coding BER is 10-3In time, the probability of correct synchronization is close to 100% by adopting the embodiment, and the probability of correct synchronization by adopting the prior art is 88.7%; when the value of N is 30, the value of B _ offset is 4, and the BER of the channel coding is 10-2In time, the probability of correct synchronization is 99.8% by adopting the embodiment, and the probability of correct synchronization by adopting the prior art scheme is 54.8%; when the value of N is 60, the value of B _ offset is 5, and the BER of the channel coding is 10-2In time, the probability of correct synchronization is 99.98% with this embodiment, and 30.1% with the prior art scheme. Obviously, when the interference in the channel is large, the probability of correct synchronization in the prior art is very low, and even the synchronization cannot be performed, but the implementation mode of the invention can maintain a high correct synchronization rate, so that the performance of the system can be greatly improved, and the superiority of the scheme of the invention is shown.
A second embodiment of the present invention relates to a block synchronization apparatus, as shown in fig. 3, including L (e.g., L ═ 66) counters, a detection module, an initialization module, and a block synchronization decider. Where L is the length of the block in bits. The block sync header is 2 bits, and the preset block sync header is "10" or "01".
Specifically, 66 counters, each counter corresponding to a possible block sync header position in a bit group having a length of 66 bits; the detection module is used for detecting N (N is more than 1) bit groups, the length of each bit group is 66, and if a bit segment which is the same as one of the preset block synchronization heads is detected, the counter corresponding to the position of the bit segment is indicated to increase the count value; the initialization module is used for initializing the 66 counters before the detection module detects the counters; and the block synchronization decider is used for judging whether the count value of only one counter in the 66 counters is greater than the B _ threshold after the detection module finishes detection, and if so, determining the position corresponding to the counter as the position of the block synchronization head.
The method for calculating the position of the synchronization head is as follows: when the value of one counter x (x is 1-N) is larger than B _ threshold, the x + nx66 (N is 0-N-1) th bit of the input data is the start of the synchronous head of the 64B/66B line coding block, at this moment, the block synchronous decision device declares that the synchronous operation is finished, and simultaneously, the block synchronous decision device starts the zero setting operation, and the 66 counters are set to zero, so that the next synchronous operation is facilitated.
And if the block synchronization decider judges that the count values of the 66 counters are all less than or equal to the B _ threshold, or the count values of at least two counters in the 66 counters are greater than the B _ threshold, the initialization module is instructed to initialize the 66 counters again, and then the detection module is instructed to detect new N bit groups.
In addition, the detection module further comprises: a shift register and a comparator.
The shift register is used for storing two bits currently detected; and the comparator is used for comparing the two bits in the shift register, and if the two bits are different, the comparator indicates that the counter corresponding to the bit segment formed by the two bits increases the count value.
Before the block synchronizer works, all 66 cycle counters are set to be 0, then the 1 st bit and the 2 nd bit of received data are respectively sent to an address 1 and an address 2 of a 2-bit shift register, then the register sends the stored data to a comparator, if the values of the 2 bits are different, the comparator triggers the 1 st counter to add 1, and if the values of the 2 bits are different, triggering operation is not carried out.
Then, the shift register shifts the 2 nd bit data in the address 2 to the address 1, and then sends the received 3 rd bit data to the address 2 of the shift register. And similarly, the comparator compares the data of 2 bits in the shift register, if the values are different, the 2 nd counter is triggered to be added by 1, and otherwise, the triggering counting operation is not carried out.
And analogically, when the address 1 of the shift register stores the 66 th bit of received data and the address 2 stores the 67 th bit of received data, the comparator compares the two bits and determines whether to perform trigger counting operation on the 66 th counter. Next, when the shift register address 1 stores the 67 th bit of received data and the address 2 stores the 68 th bit of received data, the comparator compares the two bits and then loops to the 1 st counter, if the values of the two bits of received data are different, the comparator triggers the 1 st counter to add 1, otherwise, the trigger counting operation is not performed.
A third embodiment of the present invention relates to a block synchronization method, which is similar to the first embodiment of the present invention and sequentially detects and analyzes L bits of data in N bit groups, except that in the detection process of the present embodiment, after each time the values of the a-th bit and the a + 1-th bit are compared and the corresponding operation of adding 1 to or keeping the value of the counter Bff _ cnt [ a% L ] (where, when a is made to be L, Bff _ cnt [0] points to the L-th counter), it is determined that if the count values of at least two counters are greater than B _ threshold, the current detection is immediately stopped, and block synchronization is performed again, so that the detection that is unlikely to succeed can be ended as early as possible before the N bit groups are detected, and the detection time is saved; in addition, the block synchronization header of each block in the data stream received in the first embodiment is one of the preset block synchronization headers, but in the present embodiment, the received data stream includes a block having a block synchronization header different from the preset block synchronization header, so that the present invention can be applied to successfully find the position of the block synchronization header in a frame in which a plurality of kinds of blocks coexist. Accordingly, the calculation method of B _ threshold is also different.
Specifically, in the present embodiment, B _ threshold is N-B _ offset-P. B _ offset can be determined according to a preset error rate of the block, and the higher the preset error rate is, the larger the value of B _ offset is, and the flexibly set B _ offset can adapt to different input error rates; n is also the number of bit groups tested; and N-P is the number of blocks of which the block synchronization head is a preset block synchronization head; p is the number of blocks whose block sync header does not belong to the preset block sync header. And judging whether the count values of at least two counters in the L counters are greater than the B _ threshold according to the B _ threshold, and if so, re-performing block synchronization.
FEC information frames as shown in fig. 5, each frame comprises 30 blocks, namely 27 line coding blocks and 3 check information blocks, each 27 consecutive line coding blocks are followed by 3 consecutive check blocks, and each frame is continued to each other. In addition, the length of the line coding block and the length of the check information block are both L ═ 66 bits, and each line coding block includes a 2-bit synchronization header, specifically: the synchronization head of the line coding block has opposite values, namely '01' or '10'; and the synchronous heads of the check blocks have the same value, namely '00' or '11'.
According to the formula of B _ threshold — N-B _ offset-P calculation, P is the number of blocks whose block sync header does not belong to the preset block sync header, and the sync headers "00" and "11" of 3 parity information blocks in the information frame shown in fig. 5 do not belong to the preset block sync header, that is, P is 3. Therefore, from the set B _ offset value, and the known N ═ 30, the value of B _ threshold is easily obtained.
The specific flow of the embodiment is as follows:
In step 404, determining whether the count value of at least 2 counters in the L counters is greater than B _ threshold, if yes, immediately stopping current detection, and returning to step 401 to perform block synchronization detection on subsequent data again; otherwise, it indicates that the count value of 1 or 0 of the L counters is greater than B _ threshold, and step 405 is entered.
The flowchart of the block synchronization method according to this embodiment can also be represented by the flowchart shown in fig. 6 without departing from the spirit of the present invention. Before Block synchronization is performed, a variable Block _ lock indicating a synchronization state is set to "false" to indicate that Block synchronization is started. The counters are reset simultaneously, all of the 66 counters Bff _ cnt [66] are set to zero, while the Block counter Block _ cnt is set to zero. Then, a block synchronization test is performed to execute an if (input [ a ] | ═ input [ a +1]) statement, i.e., to compare the last bit of the input data with the current bit. If the statement value is true, for legal transformation, the counter Bff _ cnt [ a% 66] value is incremented by 1, the value of a is incremented by 1 (i.e., a + +), and a determination is made as to whether a% 66 is 0, and if so, the Block counter Block _ cnt is incremented by 1. If this statement is false, for illegal transitions, the value of a is incremented by 1, the counter Bff _ cnt [66] does not act, only the block counter counts according to the corresponding condition. Assume that the number of information blocks required for testing block synchronization is N, and the threshold required for reaching block synchronization is threshold. Then after testing a sequence of a certain length, depending on the test situation, several different states may occur for block synchronization:
(1) if the block counter value is less than N and only one of the 66 counters is greater than the set threshold, then the test continues.
(2) If the value of the block counter is N, all the counters in the 66 counters are less than or equal to the threshold, or a plurality of counters are greater than the threshold, then the block synchronization operation is declared to fail, and the synchronization is resumed.
(3) If the block counter value is less than N and all of the 66 counters are less than or equal to the threshold, then testing will continue.
(4) If the value of the block counter is less than N and a number of the 66 counters are greater than a threshold, a block synchronization operation failure is declared and a sliding test is performed. Namely, the block synchronization test is immediately finished, and the next block synchronization test is started from the next test block.
(5) If the value of the Block counter is N and the value of only one of the 66 counters is greater than or equal to the threshold value threshold, the synchronization test is declared successful, and the synchronization state variable Block _ lock is set to "true".
BER 10 at channel coding was tested by block synchronization experiments on a data stream similar to the information frame shown in fig. 5-3When N is 60 and B _ offset is 4, the probability of correct synchronization of the information frame can be close to 100% by using the present embodiment, and the probability of correct synchronization by using the prior art scheme is 89.8%; BER 10 in channel coding-2When N is 60 and B _ offset is 4, the probability of correct synchronization of the information frame is 99.6% in the present embodiment, and 38.3% in the prior art. The embodiment of the invention is explained again that the high probability block synchronization can be still maintained under the condition that the BER of the channel coding is relatively high, thereby explaining the superiority of the invention.
A fourth embodiment of the present invention relates to a block synchronization apparatus, which is similar to the apparatus described in the second embodiment and includes L counters, a detection module, an initialization module, and a block synchronization decision device. The detection module further comprises a shift register and a comparator. The difference is that in this embodiment, the apparatus further comprises a detection suspension module, as shown in fig. 7.
The module is used for judging whether the count values of at least two counters in the L counters are larger than B _ threshold in the process of detecting the N bit groups by the detection module, if so, the initialization module is indicated to initialize the L counters again, and then the detection module is indicated to detect new N bit groups.
A fifth embodiment of the present invention relates to a frame synchronization method, which performs information frame synchronization after completing block synchronization and determining start and end positions of a line coding block and a check information block in a received data stream. For example, after the block synchronization of the information frame shown in fig. 5 according to the third embodiment is successfully performed, the frame synchronization of the frame of the data stream is performed as shown in fig. 8.
Each frame comprises 30(M > 1) blocks, 27 line coding blocks and 3 check information blocks, each 27 consecutive line coding blocks are followed by 3 consecutive check blocks, and each frame is followed by another frame. The length of the line coding block and the length of the check information block are both L ═ 66 bits, and each line coding block comprises a 2-bit synchronization header, specifically: the synchronization head of the line coding block has opposite values, namely '01' or '10'; and the synchronous heads of the check blocks have the same value, namely '00' or '11'. The frame synchronization method is shown in fig. 9, and its specific flow is as follows.
In step 901, K bit groups, each bit group including M ═ 30 blocks and K > 1, are detected, wherein when each bit group is detected, block synchronization headers of M blocks in the bit group are read to form a receiving sequence.
For example, as shown in fig. 10, the 1 st sync header of the received 1 st data block is denoted by h11, the 2 nd sync header of the received 1 st data block is denoted by h12, and the corresponding h301 and h302 denote the 1 st and 2 nd sync headers of the received 30 th data block, respectively. Starting from a certain block, a synchronization test is continuously performed on 30 blocks of the FEC information frame, and the 30 data blocks certainly contain 27 line coding blocks and 3 check blocks. Feeding h11 and h12 into the first two positions of a circular shift register, then, spacing 64 bits apart, finding h21 and h22, and feeding h21 and h22 into the next two positions of the circular shift register. And the like until h 11-h 302 are stored in the circular shift register in sequence.
In step 902, a correlation operation is performed on the received sequence and a reference sequence to obtain a correlation value of circularly shifted 0 bit, and the correlation value is recorded.
The reference sequence is composed of a line coding block synchronization header and a check information block synchronization header, wherein the line coding block synchronization header can be set to be any one of '01' or '10', and the check information block synchronization header can be set to be any one of '00' or '11'. Therefore, the synchronization header part of the line coding block of the reference sequence can be set to be "01", and the 3 check information block synchronization headers are: 00, 11, 11.
The basic idea of the synchronization correlation operation is to use an operation method to measure the correlation degree of the synchronization header received from the reference sequence. For example, if the received sync header is "00", it indicates that the two are completely correlated, if the received sync header is "11", it indicates that the two are not correlated, or the correlation is poor, and if the received sync header is "01" or "10", it indicates that the two have a certain correlation.
One method of synchronous correlation is shown in table 1, in which 16 possible correlation cases and their corresponding results are listed, and correlation values can be obtained by looking up the table. Specifically, the received block synchronization header is "00", and correlation values corresponding to the reference sequence values of "00", "11", "01", and "10" are 2, 0, 1, and 1, respectively; the received block synchronization header is "11", and the correlation values corresponding to the reference sequence values of "00", "11", "01", and "10" are 0, 2, 1, and 1, respectively; the received block synchronization header is "01", and the correlation values corresponding to the reference sequence are "00", "11", "01" and "10" and are 1, 2 and 2, respectively; the received block sync header is "10", and correlation values corresponding to the reference sequence values "00", "11", "01", and "10" are 1, 2, and 2, respectively.
TABLE 1
| Received block synchronization header | Reference | Correlation value | |
| 0 0 | 0 0 | 2 | |
| 0 0 | 1 1 | 0 | |
| 0 0 | 0 1/1 0 | 1 | |
| 1 1 | 0 0 | 0 | |
| 1 1 | 1 1 | 2 | |
| 1 1 | 0 1/1 0 | 1 | |
| 0 1/1 0 | 0 0 | 1 | |
| 0 1/1 0 | 1 1 | 1 | |
| 0 1/1 0 | 0 1/1 0 | 2 |
Take the sync header sequence "011000111101100110" in the circular shift register and the sync header sequence "010101010101001111" in the reference sequence as an example.
According to the synchronization correlation algorithm shown in table 1, the correlation value between the 1 st pair of synchronization headers "01" in the register and the 1 st pair of synchronization headers "01" in the reference sequence is 2, the correlation value between the 1 st pair of synchronization headers "10" in the register and the 1 st pair of synchronization headers "01" in the reference sequence is 2, and the correlation values are sequentially calculated and then added to obtain the correlation value between the synchronization sequence and the reference sequence in the register as 12.
Another synchronous correlation operation method is to calculate by using formula one: <math><mrow><mi>γ</mi><mo>=</mo><munderover><mi>Σ</mi><mrow><mi>i</mi><mo>=</mo><mn>1</mn></mrow><mi>M</mi></munderover><mrow><mo>(</mo><mn>2</mn><mo>-</mo><mo>|</mo><mrow><mo>(</mo><msub><mi>c</mi><mrow><mi>i</mi><mn>1</mn></mrow></msub><mo>-</mo><msub><mi>r</mi><mrow><mi>i</mi><mn>1</mn></mrow></msub><mo>)</mo></mrow><mo>+</mo><mrow><mo>(</mo><msub><mi>c</mi><mrow><mi>i</mi><mn>2</mn></mrow></msub><mo>-</mo><msub><mi>r</mi><mrow><mi>i</mi><mn>2</mn></mrow></msub><mo>)</mo></mrow><mo>|</mo><mo>)</mo></mrow></mrow></math> formula (1)
Where γ is the correlation value between the received sequence and the reference sequence, ci1、ci2Respectively 1 st and 2 nd sync header of data block of i-th receiving sequencei1、ri2Respectively, the data of the position corresponding to the data block of the ith received sequence in the reference sequence. Also in cyclic shiftThe sync header sequence "011000111101100110" in the register and the sync header sequence "010101010101001111" in the reference sequence are calculated as an example, and it can be found that the result is the same as that obtained by using the operation method in table 1.
In step 903, all possible cyclic shifts of the received sequence are performed in units of 2 bits of the length of the block synchronization header, where the cyclic shift may be a cyclic shift of 2 bits to the left or right, for example, after a cyclic shift of 2 bits to the right as shown in fig. 10, the synchronization headers h301 and h302 of the 30 th data block are shifted to the first 2 positions of the register.
In step 904, it is determined whether the cyclic shift is finished, and if the sequence shifted in step 903 is the same as the sequence shifted by 0 bit, that is, after the mth shift, it is determined that the cyclic shift is finished, and step 905 is entered; if the number of times of cyclic shift is less than M and the cyclic shift is not finished, step 902 is executed, correlation operation is performed on the shifted sequence and the reference sequence, a corresponding correlation value is obtained, and the value is stored.
Of course, the shift count may be counted, and after the M-1 th shifted sequence is correlated with the reference sequence and the obtained correlation value is stored, the shift operation for the bit group may be ended, and the procedure goes to step 905 in the same manner.
In step 905, it is determined whether the K bit groups have been respectively read out of the block synchronization header, and the operations of shifting and correlation operation are performed on the sequence to obtain correlation values of the sequence of the K bit groups corresponding to each cycle position, if yes, the step 907 is performed; otherwise, step 906 is entered, the sequence formed by the M sync headers of the next bit group in the K bit groups is continuously read, step 902 is entered, the sequence and the reference sequence are subjected to correlation operation, and the process is repeated in a cyclic manner until the K sequences corresponding to the K bit groups and the M correlation values of the reference sequence are obtained at each cyclic position.
In step 907, K sequences corresponding to K bit groups are obtained, and after the correlation value of each cyclic position with the reference sequence is obtained, the K correlation values with the same cyclic position are added to obtain M correlation sums.
For example, 3 bit groups (i.e., K equals 3) are detected, the number of blocks M contained in each bit group equals 6, the correlation values between the cyclic shift 6 bits corresponding to the 1 st, 2 nd and 3 th frames and the reference sequence are 54, 48 and 32, respectively, and the correlation sum corresponding to the cyclic shift 6 bits in the information frame is 54+48+32 equals 134.
In step 908, it is determined whether only one of the M correlation sums is greater than a frame threshold (F-threshold), which is 2M × K-frame offset (F _ offset). The value of F _ offset is determined according to a preset error rate in the frame, the higher the preset error rate is, the larger the F _ offset is, and different input error rates can be adapted by flexibly setting the F _ offset.
If only one correlation sum is greater than the F-threshold, step 909 is entered, and the position of the frame header is obtained according to the corresponding cyclic shift times of the correlation sum, so as to complete frame synchronization. For example, if only the correlation sum corresponding to the right cyclic shift y bits is greater than F-threshold, the M-y/2 th data block in the K bit groups can be determined as the start position of the information frame; if only the correlation sum corresponding to the left cyclic shift y bits is greater than the F-threshold, the y/2 th data block in the K bit groups can be determined as the start position of the information frame.
If all the correlation sums are less than or equal to the F-threshold, or if at least two correlation sums are greater than the F-threshold, the process returns to step 901, and the frame synchronization is performed again.
The method comprises the steps of performing cyclic displacement for M-1 times on a receiving sequence consisting of M block synchronization heads to obtain various possible cyclic displacement results of the receiving sequence, performing correlation operation on the cyclic displacement results and a reference sequence, quantitatively indicating the proximity degree of various cyclic displacement results and the reference sequence by using correlation values, and adding the correlation values corresponding to the same cyclic displacement times in K bit groups to reliably know which cyclic displacement result is closest to the reference sequence when the input error rate is higher, thereby accurately knowing the position of a frame head.
A sixth embodiment of the present invention relates to a frame synchronization device, as shown in fig. 11, including a detection unit, an accumulator, M registers, and a frame synchronization determiner.
The detection unit is used for detecting K bit groups, each bit group comprises M blocks, when each bit group is detected, a block synchronization head of the M blocks in the bit group is read to form a receiving sequence, all possible cyclic shifts are carried out on the receiving sequence by taking the length of the block synchronization head as a unit, all possible arrangements of the receiving sequence subjected to the cyclic shifts and a reference sequence are subjected to correlation operation, correlation values obtained by each correlation operation are recorded, K is greater than 1, and M is greater than 1;
the accumulator is used for adding correlation values corresponding to the same cyclic shift times in the K bit groups obtained by the detection unit to obtain M correlation sums;
m registers, which are used to store M correlation sums obtained by the accumulator;
and the frame synchronization judger is used for judging whether only one correlation sum in the M registers is larger than F-threshold, wherein the F-threshold is 2 MxK-F _ offset, and if so, the position of the frame header is obtained according to the corresponding cyclic shift times of the correlation sum.
If the frame synchronization decider decides that all the correlation sums in the M registers are less than or equal to F-threshold, or that at least two correlation sums are greater than F-threshold, the detection unit is instructed to detect a new K bit group.
In addition, the detection unit further comprises a cyclic shift register, a reference sequence memory and a correlation operator.
Specifically, the cyclic shift register is composed of 2M bits and is used for storing a receiving sequence composed of block synchronization heads of M blocks in a bit group, and the cyclic shift register cyclically shifts two bits at a time; a reference sequence memory for holding a reference sequence composed of 2M bits; and the correlation operator is used for carrying out bit-wise correlation operation on the cyclic shift register and the reference sequence memory to obtain a correlation value.
The degree of the closeness of various cyclic shift results and the reference sequence is quantitatively indicated by using correlation values, and the cyclic shift results which are closest to the reference sequence can still be reliably known when the input error rate is higher by adding the correlation values corresponding to the same cyclic shift times in K bit groups, so that the position of a frame header is accurately known.
Through experimental tests, for the information frame with the structure shown in fig. 5, when K is 3, F _ offset is 5, and BER is 10-3In the meantime, the probability of correct frame synchronization for performing frame synchronization on data of 3 information frames by using the embodiment is close to 100%, and the probability of correct frame synchronization by using the prior art is 78.7%; when K is 3, F _ offset is 5, BER is 10-2In this case, the probability of correct frame synchronization is 96.7% in the present embodiment, and the probability of correct frame synchronization is only 9.1% in the related art. The test result shows that the design scheme of the invention can maintain higher correct synchronization rate when the BER is higher than the prior art.
In summary, in the embodiment of the present invention, N bit groups are detected, the number of times that the same bit segment as the block synchronization header appears at each position in each bit group is counted, and if the counted value of only one position is greater than the first threshold, the position is the position of the block synchronization header. When the input error rate is high, the statistical values of all positions are only relatively close, but the probability that the statistical value of the position of the block synchronization head is obviously larger than that of other positions is still very high, so that the synchronization can still be accurately finished.
In the detection process, if the count values of at least two counters are larger than the first threshold, the block synchronization is carried out again, so that the detection which is not possible to succeed can be ended as early as possible before the detection of the N bit groups is finished, and the detection time is saved.
The first threshold can be set to an N-block offset value, and different input error rates can be adapted by flexibly setting the block offset value.
The first threshold may also be set to N-block offset value-P, and a block synchronization header of P blocks among the N blocks does not belong to one of the preset block synchronization headers, so that the position of the block synchronization header can be successfully found in a frame where a plurality of blocks coexist.
By comparing whether two adjacent bits are different from each other, it can be quickly determined whether two adjacent bits are one of the preset block synchronization heads when the block synchronization head has only two bits and the preset block synchronization head is "10" or "01".
The method comprises the steps of performing cyclic displacement for M-1 times on a receiving sequence consisting of M block synchronization heads to obtain various possible cyclic displacement results of the receiving sequence, performing correlation operation on the cyclic displacement results and a reference sequence, quantitatively indicating the proximity degree of various cyclic displacement results and the reference sequence by using correlation values, and adding the correlation values corresponding to the same cyclic displacement times in K bit groups to reliably know which cyclic displacement result is closest to the reference sequence when the input error rate is higher, thereby accurately knowing the position of a frame head.
While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention.
Claims (12)
1. A block synchronization method, comprising the steps of:
initializing L counters, wherein each counter corresponds to a position in a bit group with the length of L, a block synchronization head appears at one of the L positions corresponding to the L counters, and L is more than 1;
detecting N bit groups, wherein the length of each bit group is L, if a bit segment which is the same as one of preset block synchronization heads is detected, selecting a counter corresponding to the position of the bit segment from the L counters, and increasing the count value of the selected counter; n is more than 1;
if the count value of only one counter in the L counters is greater than a first threshold, the position corresponding to the counter is determined as the position of the block synchronization head; wherein the block is L bits long.
2. The block synchronization method according to claim 1, wherein the block synchronization header is 2 bits, and the preset block synchronization header is "10" or "01".
3. The block synchronization method according to claim 2, wherein the step of detecting N groups of bits comprises the sub-steps of:
scanning each bit in each bit group, and if the value of the Xth bit in the scanned bit group is different from that of the (X + 1) th bit, judging that a bit segment which is the same as one of preset block synchronization heads is detected, wherein the detected bit segment consists of the Xth bit and the (X + 1) th bit;
the step of increasing the count value by the counter corresponding to the position of the bit segment comprises the following substeps:
and adding 1 to the count value of the Xth counter.
4. The block synchronization method of claim 1, further comprising, after the step of detecting the N bit groups, the steps of:
and if the count values of the L counters are all smaller than or equal to the first threshold, or the count values of at least two counters in the L counters are larger than the first threshold, the block synchronization is carried out again.
5. The block synchronization method according to claim 1, wherein in the step of detecting the N bit groups, the sub-step of:
and detecting the bit groups one by one, and immediately stopping current detection and re-performing block synchronization if the count values of at least two counters in the L counters are greater than the first threshold before the detection of the N bit groups is finished.
6. The block synchronization method according to any one of claims 1 to 5, wherein N is the number of blocks in each frame;
the block synchronization header of each block in the frame is one of the preset block synchronization headers, and the first threshold is an N-block offset value;
or,
the block synchronization header of N-P blocks in the frame is one of the preset block synchronization headers, the block synchronization header of P blocks does not belong to one of the preset block synchronization headers, and the first threshold is N-block offset-P.
7. The block synchronization method according to claim 6, wherein the block offset value is determined according to a preset error rate in the block.
8. A block synchronization apparatus, comprising:
l counters, each counter corresponding to a position in a bit group with length L, a block synchronization head appearing at one of the L positions corresponding to the L counters, L > 1;
the detection module is used for detecting N bit groups, the length of each bit group is L, if a bit segment which is the same as one of the preset block synchronization heads is detected, a counter corresponding to the position of the bit segment is selected from the L counters, and the selected counter is indicated to increase the count value;
the initialization module is used for initializing the L counters before the detection module detects the counters;
the block synchronization decision device is used for judging whether the count value of only one counter in the L counters is greater than a first threshold after the detection module finishes the detection, and if so, determining the position corresponding to the counter as the position of a block synchronization head;
wherein the block is L bits long and N > 1.
9. The block synchronization apparatus according to claim 8, wherein the block synchronization header is 2 bits, and the preset block synchronization header is "10" or "01".
10. The block synchronization apparatus according to claim 9, wherein the detection module comprises:
the shift register is used for storing two currently detected bits;
and the comparator is used for comparing two bits in the shift register and indicating a counter corresponding to a bit segment formed by the two bits to increase a count value if the two bits are different.
11. The block synchronization apparatus according to any one of claims 8 to 10, wherein the block synchronization decider determines that the count values of the L counters are all less than or equal to the first threshold, or the count values of at least two of the L counters are greater than the first threshold, then the initialization module is instructed to re-initialize the L counters, and then the detection module is instructed to detect a new N bit groups.
12. The block synchronization device according to any one of claims 8 to 10, further comprising:
and a detection suspension module, configured to, during a detection process of the detection module on the N bit groups, determine whether count values of at least two counters in the L counters are greater than the first threshold, if so, instruct the initialization module to reinitialize the L counters, and then instruct the detection module to detect new N bit groups.
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| EP1515457A2 (en) * | 2003-09-10 | 2005-03-16 | Nec Corporation | Synchronization judging circuit capable of operating moderately |
| CN1859047A (en) * | 2006-01-24 | 2006-11-08 | 华为技术有限公司 | Frame synchronous processing device and method |
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| EP1515457A2 (en) * | 2003-09-10 | 2005-03-16 | Nec Corporation | Synchronization judging circuit capable of operating moderately |
| CN1859047A (en) * | 2006-01-24 | 2006-11-08 | 华为技术有限公司 | Frame synchronous processing device and method |
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