CN101197308A - Production method of metal wiring structure in semiconductor element - Google Patents
Production method of metal wiring structure in semiconductor element Download PDFInfo
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- CN101197308A CN101197308A CNA200610119048XA CN200610119048A CN101197308A CN 101197308 A CN101197308 A CN 101197308A CN A200610119048X A CNA200610119048X A CN A200610119048XA CN 200610119048 A CN200610119048 A CN 200610119048A CN 101197308 A CN101197308 A CN 101197308A
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Abstract
The invention relates to a metal wiring structure fabrication method in a semiconductor device; after a wiring pattern is formed and through adjusting the component proportion of etching agent, the selection ratio of the etching rate of an ultraviolet light absorption layer and an inner medium layer is controlled; firstly a first etching phase is performed till a deep ultraviolet light absorption layer in the position of an photoresist opening of a connecting area of the metal is fully removed; secondly a second etching phase is performed in order that the channel depth of the connecting area of the metal is the same with that of a dual-damascene structure area basically. The invention reduces the nonuniformity of resistance distribution of metal conducting wires in the metal wiring of the prior art and improves the reliability of circuit connection.
Description
Technical field
The present invention relates to the semiconductor fabrication techniques field, the manufacture method of metal wiring structure in particularly a kind of semiconductor device.
Background technology
Usually, manufacture of semiconductor is the device that forms integrated circuit with depositing technics, photoetching process, etching technics etc. on silicon wafer.Constitute integrated circuit in order to connect each parts, use usually have relative high conductivity metal material for example copper connect up metal line just.A kind of technology the most conventional in the metal line is metal double-insert technology and metal interconnecting technology.
Metal double-insert technology is that wherein through hole and groove are film formed by the selective etch layer insulation with the technology of metal material filling vias and groove.The dual-damascene technics that provides for 02106882.8 Chinese patent application file of application number for example.Metal interconnecting technology is the technology with metal material filling vias or groove, for example the manufacture method of the metal interconnecting structure that provided for the Chinese patent application file of CN02105018 of application number.
In the same wiring layer of semiconductor device, according to the circuit design requirement of device, can form dual-damascene structure and metal interconnecting structure simultaneously, shown in Figure 1A to Fig. 1 E, be the manufacture method of metal wiring structure in the semiconductor device in the prior art.At first, shown in Figure 1A, on semiconductor substrate 10, form etching stop layer 11, on etching stop layer 11, form inner layer dielectric layer (inter-layerdielectrics; ILD) 12, described inner layer dielectric layer material such as fluorine silex glass and advanced low-k materials etc., afterwards, the zone 1 to needs formation dual-damascene structure etches through hole 17 on inner layer dielectric layer 12.
Afterwards, with reference to the accompanying drawings shown in the 1B, form filling vias 17 and cover dark purple porphin light absorbing zone 13 (the DUV Light Absorbing Oxide of inner layer dielectric layer 12; DUO), because the existence of through hole 17 in the zone 1 of formation dual-damascene structure, therefore, there is a difference 18 in the thickness that forms in the zone 1 of dual-damascene structure deep UV (ultraviolet light) absorbed layer 13 in the zone 2 that needs to form metal interconnecting on the inner layer dielectric layer 12 on the thickness of deep UV (ultraviolet light) absorbed layer 13 and semiconductor device, shown in Figure 1B.
Subsequently, on inner layer dielectric layer 12, form photoresist 14, and the required pattern of formation that exposes, develops, shown in accompanying drawing 1C, in the zone 1 that forms dual-damascene structure, form photoresist opening 16, wherein photoresist opening 16 is positioned at the top of through hole 17.And form photoresist openings 15 in the zone 2 of needs formation metal interconnecting.
Subsequently, with reference to the accompanying drawings shown in the 1D, with the photoresist is mask, etching deep UV (ultraviolet light) absorbed layer 13 and inner layer dielectric layer 12 form raceway groove 16b in the zone 1 that forms dual-damascene structure, and form groove 15b in the zone 2 that forms metal interconnecting, because the etching agent of available technology adopting is basic identical to the etch rate of deep UV (ultraviolet light) absorbed layer 13 and inner layer dielectric layer 12, therefore, still there is thickness difference 18a in etching between the raceway groove 16b of formation and the groove 15b after finishing.
Afterwards, with reference to the accompanying drawings shown in the 1E, remove photoresist 14 and deep UV (ultraviolet light) absorbed layer 13, form through hole 17 and raceway groove 16b in the inner layer dielectric layer 12 in the zone 1 that forms dual-damascene structure, in the inner layer dielectric layer 12 in the zone 2 that forms metal interconnecting, form groove 15b, wherein still have thickness difference 18a between raceway groove 16b and the groove 15b.
At last, in through hole 17, raceway groove 16b and groove 15b, fill for example copper of metal material, and to promptly forming the metal line (not shown) after the surface formation planarization.Owing to have thickness difference 18a between raceway groove 16b and the groove 15b, therefore also there is the difference of thickness in the metal line material that forms in raceway groove 16b and the groove 15b, this species diversity causes the resistance of semiconductor device inside conductor to produce difference, make the resistance value of different parts plain conductor inhomogeneous, had a strong impact on the performance of device.
Summary of the invention
The problem that the present invention solves is that the wire structures that the manufacture method of metal wiring structure in the prior art semiconductor device forms exists difference in thickness, thereby causes the plain conductor that the forms uneven defective of resistance everywhere.
The invention provides the manufacture method of metal wiring structure in a kind of semiconductor device, comprise the steps:
Form etching stop layer and inner layer dielectric layer successively on semiconductor substrate, described etching stop layer and inner layer dielectric layer comprise dual-damascene structure zone and metal interconnecting zone;
On the inner layer dielectric layer in dual-damascene structure zone, form through hole;
Form filling vias and cover the deep UV (ultraviolet light) absorbed layer of inner layer dielectric layer;
On the deep UV (ultraviolet light) absorbed layer, form photoresist layer, and the formation photoresist opening that exposes, develops, the photoresist aperture position in dual-damascene structure zone is corresponding with lead to the hole site, and the photoresist A/F is greater than the through hole width, and the photoresist aperture position in metal interconnecting zone is for forming the position of metal line;
The phase I etching: selecting for use the etch rate of deep UV (ultraviolet light) absorbed layer and inner layer dielectric layer is selected than greater than 1 etching agent, is mask with the photoresist layer, until the deep UV (ultraviolet light) absorbed layer of removing metal interconnecting zone photoresist aperture position fully;
Second stage etching: the inner layer dielectric layer of etching metal interconnecting zone photoresist aperture position, form raceway groove, deep UV (ultraviolet light) absorbed layer in the inner layer dielectric layer in etching dual-damascene structure zone and the through hole forms groove, and described raceway groove and the groove degree of depth in inner layer dielectric layer is basic identical;
Remove the deep UV (ultraviolet light) absorbed layer in photoresist layer and the through hole.
The present invention also provides the manufacture method of metal wiring structure in a kind of semiconductor device, comprises the steps:
Form etching stop layer and inner layer dielectric layer successively on semiconductor substrate, described etching stop layer and inner layer dielectric layer comprise dual-damascene structure zone and metal interconnecting zone;
On the inner layer dielectric layer in dual-damascene structure zone, form through hole;
Form filling vias and cover the deep UV (ultraviolet light) absorbed layer of inner layer dielectric layer;
On the deep UV (ultraviolet light) absorbed layer, form photoresist layer, and the formation photoresist opening that exposes, develops, the photoresist aperture position in dual-damascene structure zone is corresponding with lead to the hole site, and the photoresist A/F is greater than the through hole width, and the photoresist aperture position in metal interconnecting zone is for forming the position of metal line;
Pre-etching: with the photoresist layer is mask, etching deep UV (ultraviolet light) absorbed layer, deep UV (ultraviolet light) absorbed layer until removing dual-damascene structure zone photoresist aperture position fully still has the deep UV (ultraviolet light) absorbed layer on the inner layer dielectric layer of the photoresist aperture position in metal interconnecting zone at this moment;
The phase I etching: selecting for use the etch rate of deep UV (ultraviolet light) absorbed layer and inner layer dielectric layer is selected than greater than 1 etching agent, is mask with the photoresist layer, until the deep UV (ultraviolet light) absorbed layer of removing metal interconnecting zone photoresist aperture position fully;
Second stage etching: the inner layer dielectric layer of etching metal interconnecting zone photoresist aperture position, form raceway groove, deep UV (ultraviolet light) absorbed layer in the inner layer dielectric layer in etching dual-damascene structure zone and the through hole forms groove, and described raceway groove and the groove degree of depth in inner layer dielectric layer is basic identical;
Remove the deep UV (ultraviolet light) absorbed layer in photoresist layer and the through hole.
Compared with prior art, the present invention has the following advantages:
(1) the present invention selects for use during etching the etch rate of deep UV (ultraviolet light) absorbed layer and inner layer dielectric layer is selected than greater than 1 carrying out the phase I, be preferably 2: 1～3.5: 1 etching agent, with the photoresist layer is mask, until the deep UV (ultraviolet light) absorbed layer of removing metal interconnecting zone photoresist aperture position fully, at this moment, though remove the deep UV (ultraviolet light) absorbed layer in dual-damascene structure zone fully, and be etched to inner layer dielectric layer, since etching agent to the etch rate of inner layer dielectric layer much smaller than the etch rate that deep ultraviolet is absorbed photosphere, therefore, reduced since on dual-damascene structure zone and the metal interconnecting zone existence of deep ultraviolet absorbed layer difference in height cause the wire laying slot that forms after the etching and the influence of channel depth, make the wire channels and the degree of depth of groove in inner layer dielectric layer of final formation basic identical, increase the uniformity of wiring, avoided the uneven defective of wiring back conductor resistance.
(2) in another technical scheme of the present invention, at first carry out pre-etching, etching deep UV (ultraviolet light) absorbed layer, until the deep UV (ultraviolet light) absorbed layer of removing dual-damascene structure zone photoresist aperture position fully, and then carry out the etching first time, select for use the etch rate of deep UV (ultraviolet light) absorbed layer and inner layer dielectric layer is selected than the etching agent that is 2: 1～3.5: 1, with the photoresist layer is mask, be etched to the deep UV (ultraviolet light) absorbed layer of removing metal interconnecting zone photoresist aperture position fully, adopt the technical program, can prevent the deep UV (ultraviolet light) absorbed layer in the too much etching removal dual-damascene structure zone through hole, cause the damage semiconductor substrate, and can avoid over etching, avoid in the through hole in dual-damascene structure zone, producing multi-plane structure the inner layer dielectric layer around the through hole.
Description of drawings
Figure 1A to Fig. 1 E is the cross section structure schematic diagram of the manufacture method technological process of metal wiring structure in the prior art semiconductor device;
Fig. 2 A to Fig. 2 F is the cross section structure schematic diagram of the manufacture method technological process of metal wiring structure in the first embodiment of the invention semiconductor device;
Fig. 3 A to Fig. 3 G is the cross section structure schematic diagram of the manufacture method technological process of metal wiring structure in the second embodiment of the invention semiconductor device;
Fig. 4 forms the regional cross section scanning electron microscope diagram of metal interconnecting for the present invention;
Fig. 5 forms the regional cross section scanning electron microscope diagram of dual-damascene structure for the present invention.
Embodiment
Below in conjunction with accompanying drawing the specific embodiment of the present invention is done detailed description.
At first, the invention provides the manufacture method of metal wiring structure in a kind of semiconductor device, comprise the steps:
Form etching stop layer and inner layer dielectric layer successively on semiconductor substrate, described etching stop layer and inner layer dielectric layer comprise dual-damascene structure zone and metal interconnecting zone; On the inner layer dielectric layer in dual-damascene structure zone, form through hole; Form filling vias and cover the deep UV (ultraviolet light) absorbed layer of inner layer dielectric layer; On the deep UV (ultraviolet light) absorbed layer, form photoresist layer, and the formation photoresist opening that exposes, develops, the photoresist aperture position in dual-damascene structure zone is corresponding with lead to the hole site, and the photoresist A/F is greater than the through hole width, and the photoresist aperture position in metal interconnecting zone is for forming the position of metal line; Selecting for use the etch rate of deep UV (ultraviolet light) absorbed layer and inner layer dielectric layer is selected than the etching agent that is 2: 1～3.5: 1, is mask with the photoresist layer, until the deep UV (ultraviolet light) absorbed layer of removing metal interconnecting zone photoresist aperture position fully; The inner layer dielectric layer of etching metal interconnecting zone photoresist aperture position, form raceway groove, deep UV (ultraviolet light) absorbed layer in the inner layer dielectric layer in etching dual-damascene structure zone and the through hole forms groove, and described raceway groove and the groove degree of depth in inner layer dielectric layer is basic identical; Remove the deep UV (ultraviolet light) absorbed layer in photoresist layer and the through hole.
Shown in Fig. 2 A to Fig. 2 F, be the cross section structure schematic diagram of the different process step of the manufacture method of metal wiring structure in the first embodiment of the invention semiconductor device.
At first, shown in figure 2A, provide semiconductor matrix 100, described semiconductor substrate 100 can be a metal wiring layer, also can be device layer.On semiconductor substrate 100, form etching stop layer 110; described etching stopping layer 110 for example is silicon nitride or carborundum; form for example plasma reinforced chemical vapour deposition method of technology; for protection semiconductor substrate 100 in etching process, the thickness of etching stop layer 110 is preferably 20～50 nanometers.On etching stop layer 110, form inner layer dielectric layer (inter-layerdielectrics; ILD) 120, described inner layer dielectric layer material such as fluorine silex glass and advanced low-k materials such as carbonado etc., as the insulating barrier between the internal layer, the thickness of inner layer dielectric layer 120 is 100～800 nanometers.In the manufacturing process of semiconductor device, circuit design requirement according to device, in same wiring layer, may need to form dual-damascene structure and metal interconnecting structure simultaneously, in the present embodiment, for the convenience of describing, shown in the 2A, inner layer dielectric layer 120 and etching stop layer are divided into dual-damascene structure zone 101 and metal interconnecting zone 102 with reference to the accompanying drawings.Afterwards, the zone 101 to needs formation dual-damascene structure etches through hole 111 on inner layer dielectric layer 120, and the aperture of through hole 111 is 120～180 nanometers.
Afterwards, with reference to the accompanying drawings shown in the 2B, form filling vias 111 and cover deep UV (ultraviolet light) absorbed layer 130 (the DUV Light Absorbing Oxide of inner layer dielectric layer 120; DUO), the thickness of deep UV (ultraviolet light) absorbed layer 130 is 150～300 nanometers, is used as the sacrifice layer and the anti-reflecting layer of channel etching in the metal wiring structure manufacturing process.Described deep UV (ultraviolet light) absorbed layer is a kind of oxide material that has the molecular radical that absorbs deep UV (ultraviolet light), for example has the silica material of organic molecule group on silicon atom, shown in the following molecular formula I.
Because the existence of through hole 111 in the zone 101 of formation dual-damascene structure, therefore, there is a difference 180 in the thickness that forms in the zone 101 of dual-damascene structure deep UV (ultraviolet light) absorbed layer 130 in the zone 102 that needs to form metal interconnecting on the inner layer dielectric layer 120 on the thickness of deep UV (ultraviolet light) absorbed layer 130 and semiconductor device, and its thickness difference is greatly about 60～100 nanometers.Shown in Figure 1B.The existence of thickness difference can cause the resistance value of the final plain conductor that forms inhomogeneous, influences the performance of device.
Subsequently, on inner layer dielectric layer 120, form photoresist 140, and the required pattern of formation that exposes, develops, shown in accompanying drawing 2C, form photoresist opening 160 in the zone 101 that forms dual-damascene structure, wherein photoresist opening 160 is positioned at the top of through hole 111, and A/F is greater than the width of through hole 111, the zone 102 that forms metal interconnecting at needs forms photoresist opening 150, and the position of photoresist opening 150 is the position that will form metal line.
Subsequently, with reference to the accompanying drawings shown in the 2D, carry out the phase I etching, select for use the etch rate of deep UV (ultraviolet light) absorbed layer and inner layer dielectric layer is selected than greater than 1 etching agent, the present invention preferably selects than the etching agent that is 2: 1～3.5: 1 etch rate of deep UV (ultraviolet light) absorbed layer and inner layer dielectric layer, with the photoresist is mask, etching deep UV (ultraviolet light) absorbed layer 130 and inner layer dielectric layer 120, until the deep UV (ultraviolet light) absorbed layer 130 of removing metal interconnecting zone 102 photoresist aperture positions fully, in the zone 101 that forms dual-damascene structure, form raceway groove 160a, and form groove 150a in the zone 102 that forms metal interconnecting.
Owing to have a difference 180 between the thickness of deep UV (ultraviolet light) absorbed layer 130 in the zone 102 of dual-damascene structure zone 101 and metal interconnecting, therefore, when removing the deep UV (ultraviolet light) absorbed layer 130 of metal interconnecting zone 102 photoresist aperture positions fully, deep UV (ultraviolet light) absorbed layer 130 on the dual-damascene structure zone 101 is etched away fully, and has begun the deep UV (ultraviolet light) absorbed layer 130 in etching inner layer dielectric layer 120 and the through hole 111.But, the etching agent that present embodiment is selected for use is to the higher selectivity that has of deep UV (ultraviolet light) absorbed layer 130 and inner layer dielectric layer 120, therefore, after the deep UV (ultraviolet light) absorbed layer 130 on the intact dual-damascene structure zone 101 of etching, etch rate to inner layer dielectric layer 130 is very slow, behind the deep UV (ultraviolet light) absorbed layer 130 of removing metal interconnecting zone 102 fully, the etch thicknesses of inner layer dielectric layer 130 is still very little on the dual-damascene structure zone 101, therefore, carry out after the phase I etching, reduced the difference in height in zone 101 of dual-damascene structure on the inner layer dielectric layer 130 and metal interconnecting zone 102.
The described etch rate to deep UV (ultraviolet light) absorbed layer 130 and inner layer dielectric layer 120 of present embodiment is selected to contain following component: C than the etching agent that is 2: 1～3.5: 1
4F
8, C
2F
6And C
3F
8In any one, volume percent content is 2%～10%; CHF
3, CF
4, NF
3And SF
6In any one, volume percent content is 4%～10%; Inert gas, volume percent content are 10%～20%; Oxygen, volume percent content are 1%～5%; All the other are nitrogen.Described inert gas is argon gas etc. for example.This etching agent is 500～600nm/min to the etch rate of deep UV (ultraviolet light) absorbed layer 130, and to the etch rate 150～220nm/min of inner layer dielectric layer 120, in the specific embodiment of the present invention, used etch period is 30s～60s.
In a specific embodiment of the present invention, adopt following etching agent: volume percent content is 5% C
4F
8, volume percent content is 8% CHF
3, volume percent content is 15% argon gas, and volume percent content is 3% oxygen, and all the other are nitrogen, carry out after the etching of phase I, and the height in dual-damascene structure zone 101 and metal interconnecting zone 102 is basic identical on the inner layer dielectric layer 130.
With reference to the accompanying drawings shown in the 2E, carry out the etching second time, the inner layer dielectric layer 120 of etching metal interconnecting zone 102 photoresist aperture positions, form raceway groove 150b, deep UV (ultraviolet light) absorbed layer 130 in the inner layer dielectric layer 120 in etching dual-damascene structure zone 101 and the through hole 111, form groove 160b, the described raceway groove 150b and the degree of depth of groove 160b in inner layer dielectric layer 120 are basic identical.
Because the second stage etch material is mainly inner layer dielectric layer 120, also have the part deep UV (ultraviolet light) absorbed layer 130 in the through hole 111, therefore, the etching agent of selecting for use is that the etching agent of conventional etching inner layer dielectric layer 120 materials gets final product.In the present invention, the selection ratio of preferred deep UV (ultraviolet light) absorbed layer 130 and inner layer dielectric layer 120 etch rates is 0.8: 1～1.5: 1 a etching agent, to avoid the UV Absorption layer 130 in the too fast etching through hole 111.The etching agent composition is two kinds of fluoro-gas and inert gas, and wherein a kind of fluoro-gas is CF
4, C
4F
8And C
3F
8In a kind of, its volume content is 15%～30%, another kind of fluoro-gas is CHF
3, SF
6And C
3F
8In a kind of, its volume content is 10%～20%, all the other are inert gas, its volume content is 50%～75%, described inert gas is for for argon gas, a kind of in neon or the helium.Etch rate to deep UV (ultraviolet light) absorbed layers 130 in the through hole 111 is 500～540nm/min, is 470～520nm/min to the etch rate of inner layer dielectric layer 120.When etching depth reach institute's etching medium thickness 1/3 and 2/3 between the time, stop etching, the raceway groove 150b that form in the inner layer dielectric layer 120 and the degree of depth of groove 160b are basic identical.
In a specific embodiment of the present invention, adopt following etching agent: volume percent content is 20% CF
4, volume percent content is 15% CHF
3, volume percent content is 65% argon gas, stops after the etching, the raceway groove 150b that forms in the inner layer dielectric layer 120 and the degree of depth of groove 160b are basic identical.
Afterwards, with reference to the accompanying drawings shown in the 2F, remove the deep UV (ultraviolet light) absorbed layer 130 in photoresist 140 and the through hole 111, form through hole 111 and raceway groove 160b in the inner layer dielectric layer 120 in the zone 101 that forms dual-damascene structure, form groove 150b in the inner layer dielectric layer 120 in the zone 102 that forms metal interconnecting, wherein the degree of depth of raceway groove 160b and groove 150b is basic identical.
At last, in through hole 111, raceway groove 160b and groove 150b, fill for example copper of metal material, and to promptly forming the metal line (not shown) after the surface formation planarization.Because the degree of depth of raceway groove 160b and groove 150b is basic identical, therefore, the thickness of the metal line material that forms in raceway groove 160b and the groove 150b is also basic identical, relative and prior art, the resistance value size basically identical of different parts plain conductor.
The manufacture method of metal wiring structure in a kind of semiconductor device comprises: form etching stop layer and inner layer dielectric layer successively on semiconductor substrate, described etching stop layer and inner layer dielectric layer comprise dual-damascene structure zone and metal interconnecting zone; On the inner layer dielectric layer in dual-damascene structure zone, form through hole; Form filling vias and cover the deep UV (ultraviolet light) absorbed layer of inner layer dielectric layer; On the deep UV (ultraviolet light) absorbed layer, form photoresist layer, and the formation photoresist opening that exposes, develops, the photoresist aperture position in dual-damascene structure zone is corresponding with lead to the hole site, and the photoresist A/F is greater than the through hole width, and the photoresist aperture position in metal interconnecting zone is for forming the position of metal line; Pre-etching: with the photoresist layer is mask, etching deep UV (ultraviolet light) absorbed layer, deep UV (ultraviolet light) absorbed layer until removing dual-damascene structure zone photoresist aperture position fully still has the deep UV (ultraviolet light) absorbed layer on the inner layer dielectric layer of the photoresist aperture position in metal interconnecting zone at this moment; Phase I etching: select for use the etch rate of deep UV (ultraviolet light) absorbed layer and inner layer dielectric layer is selected than the etching agent that is 2: 1～3.5: 1, with the photoresist layer is mask, until the deep UV (ultraviolet light) absorbed layer of removing metal interconnecting zone photoresist aperture position fully; Second stage etching: the inner layer dielectric layer of etching metal interconnecting zone photoresist aperture position, form raceway groove, deep UV (ultraviolet light) absorbed layer in the inner layer dielectric layer in etching dual-damascene structure zone and the through hole forms groove, and described raceway groove and the groove degree of depth in inner layer dielectric layer is basic identical; Remove the deep UV (ultraviolet light) absorbed layer in photoresist layer and the through hole.
Shown in Fig. 3 A to Fig. 3 G, be the cross section structure schematic diagram of the different process step of the manufacture method of metal wiring structure in the first embodiment of the invention semiconductor device.
At first, shown in figure 3A, provide semiconductor matrix 200, described semiconductor substrate 200 can be a metal wiring layer, also can be device layer.On semiconductor substrate 200, form etching stop layer 210; described etching stopping layer 210 for example is silicon nitride or carborundum; form for example plasma reinforced chemical vapour deposition method of technology; for protection semiconductor substrate 200 in etching process, the thickness of etching stop layer 210 is preferably 20～50 nanometers.On etching stop layer 210, form inner layer dielectric layer (inter-layerdielectrics; ILD) 220, described inner layer dielectric layer material such as fluorine silex glass and advanced low-k materials such as carbonado etc., as the insulating barrier between the internal layer, the thickness of inner layer dielectric layer 220 is 100～800 nanometers.In the manufacturing process of semiconductor device, circuit design requirement according to device, in same wiring layer, may need to form dual-damascene structure and metal interconnecting structure simultaneously, in the present embodiment, for the convenience of describing, shown in the 2A, inner layer dielectric layer 220 and etching stop layer are divided into dual-damascene structure zone 201 and metal interconnecting zone 202 with reference to the accompanying drawings.Afterwards, the zone 201 to needs formation dual-damascene structure etches through hole 222 on inner layer dielectric layer 220, and the aperture of through hole 222 is 120～180 nanometers.
Afterwards, with reference to the accompanying drawings shown in the 3B, form filling vias 222 and cover deep UV (ultraviolet light) absorbed layer 230 (the DUV Light Absorbing Oxide of inner layer dielectric layer 220; DUO), the thickness of deep UV (ultraviolet light) absorbed layer 230 is 150～300 nanometers, is used as the sacrifice layer and the anti-reflecting layer of channel etching in the metal wiring structure manufacturing process.Described deep UV (ultraviolet light) absorbed layer is a kind of oxide material that has the molecular radical that absorbs deep UV (ultraviolet light), for example has the silica material of organic molecule group on silicon atom, shown in the following molecular formula I.
Because the existence of through hole 222 in the zone 201 of formation dual-damascene structure, therefore, there is a difference 280 in the thickness that forms in the zone 201 of dual-damascene structure deep UV (ultraviolet light) absorbed layer 230 in the zone 202 that needs to form metal interconnecting on the inner layer dielectric layer 220 on the thickness of deep UV (ultraviolet light) absorbed layer 230 and semiconductor device, and its thickness difference is greatly about 60～100 nanometers.Shown in Fig. 3 B.The existence of thickness difference can cause the resistance value of the final plain conductor that forms inhomogeneous, influences the performance of device.
Subsequently, on inner layer dielectric layer 220, form photoresist 240, and the required pattern of formation that exposes, develops, shown in accompanying drawing 3C, form photoresist opening 260 in the zone 201 that forms dual-damascene structure, wherein photoresist opening 260 is positioned at the top of through hole 222, and A/F is greater than the width of through hole 222, the zone 202 that forms metal interconnecting at needs forms photoresist opening 250, and the position of photoresist opening 250 is the position that will form metal line.
Subsequently, shown in the 3D, carry out pre-etching with reference to the accompanying drawings: with photoresist 240 is mask, etching deep UV (ultraviolet light) absorbed layer 230, deep UV (ultraviolet light) absorbed layer 230 until removing dual-damascene structure zone 201 photoresist aperture positions fully forms groove 260c, forms raceway groove 250c in the metal interconnecting zone.Because there is thickness difference 280 in deep UV (ultraviolet light) absorbed layer 230 on dual-damascene structure zone 201 and inner layer dielectric layer 220, therefore, when removing the deep UV (ultraviolet light) absorbed layer 230 of dual-damascene structure zone 201 photoresist aperture positions fully, still there be the deep UV (ultraviolet light) absorbed layer 230 identical on the inner layer dielectric layer 220 of the photoresist aperture position in metal interconnecting zone 201 with thickness difference 280 numerical value.Because pre-etch step is etching deep UV (ultraviolet light) absorbed layer 230 only, therefore, the etching agent of selecting for use is that the etching agent of conventional etching deep UV (ultraviolet light) absorbed layer 230 materials gets final product.The preferred etching agent of present embodiment is selected than being 1: 0.8～1.2 the etch rate of deep UV (ultraviolet light) absorbed layer 230 and inner layer dielectric layer 220.
In a specific embodiment of the present invention, etching agent is a kind of fluoro-gas and inert gas, and wherein fluoride is CF
4, C
4F
8, C
3F
8, C
2F
6, CHF
3, NF
3, SF
6In a kind of, inert gas is an argon gas, a kind of in neon or the helium.The volume content of fluoro-gas is 10%～25%, and the volume content of inert gas is 75%～90%.Used etch period is 15s～40s.
Afterwards, with reference to the accompanying drawings shown in the 3E, carry out the phase I etching, select for use the etch rate of deep UV (ultraviolet light) absorbed layer and inner layer dielectric layer is selected than greater than 1 etching agent, the present invention preferably selects than the etching agent that is 2: 1～3.5: 1 etch rate of deep UV (ultraviolet light) absorbed layer and inner layer dielectric layer, with the photoresist is mask, etching deep UV (ultraviolet light) absorbed layer 230 and inner layer dielectric layer 220, until the deep UV (ultraviolet light) absorbed layer 230 of removing metal interconnecting zone 202 photoresist aperture positions fully, in the zone 201 that forms dual-damascene structure, form raceway groove 260a, and form groove 250a in the zone 202 that forms metal interconnecting.
Owing to have a difference 280 between the thickness of deep UV (ultraviolet light) absorbed layer 230 in the zone 202 of dual-damascene structure zone 201 and metal interconnecting, therefore, when removing the deep UV (ultraviolet light) absorbed layer 230 of metal interconnecting zone 202 photoresist aperture positions fully, deep UV (ultraviolet light) absorbed layer 230 on the dual-damascene structure zone 201 is etched away fully, and has begun the deep UV (ultraviolet light) absorbed layer 230 in etching inner layer dielectric layer 220 and the through hole 222.But, the etching agent that present embodiment is selected for use is to the higher selectivity that has of deep UV (ultraviolet light) absorbed layer 230 and inner layer dielectric layer 220, therefore, after the deep UV (ultraviolet light) absorbed layer 230 on the intact dual-damascene structure zone 201 of etching, etch rate to inner layer dielectric layer 230 is very slow, behind the deep UV (ultraviolet light) absorbed layer 230 of removing metal interconnecting zone 202 fully, the etch thicknesses of inner layer dielectric layer 230 is still very little on the dual-damascene structure zone 201, therefore, carry out after the phase I etching, reduced the difference in height in zone 201 of dual-damascene structure on the inner layer dielectric layer 230 and metal interconnecting zone 202.
The described etch rate to deep UV (ultraviolet light) absorbed layer 230 and inner layer dielectric layer 220 of present embodiment is selected to contain following component: C than the etching agent that is 2: 1～3.5: 1
4F
8, C
2F
6And C
3F
8In any one, volume percent content is 2%～10%; CHF
3, CF
4, NF
3And SF
6In any one, volume percent content is 4%～10%; Inert gas, volume percent content are 10%～20%; Oxygen, volume percent content are 1%～5%; All the other are nitrogen.Described inert gas is argon gas etc. for example.This etching agent is 500～600nm/min to the etch rate of deep UV (ultraviolet light) absorbed layer 230, and to the etch rate 150～220nm/min of inner layer dielectric layer 220, in the specific embodiment of the present invention, used etch period is 30s～60s.
In a specific embodiment of the present invention, adopt following etching agent: volume percent content is 10% C
2F
6, volume percent content is 10% CF
4, volume percent content is 10% argon gas, and volume percent content is 5% oxygen, and all the other are nitrogen, carry out after the etching of phase I, and the height in dual-damascene structure zone 201 and metal interconnecting zone 202 is basic identical on the inner layer dielectric layer 230.
With reference to the accompanying drawings shown in the 3F, carry out the second stage etching, the inner layer dielectric layer 220 of etching metal interconnecting zone 202 photoresist aperture positions, form raceway groove 250b, deep UV (ultraviolet light) absorbed layer 230 in the inner layer dielectric layer 220 in etching dual-damascene structure zone 201 and the through hole 222, form groove 260b, the described raceway groove 250b and the degree of depth of groove 260b in inner layer dielectric layer 220 are basic identical.
Because the second stage etch material is mainly inner layer dielectric layer 220, also have the part deep UV (ultraviolet light) absorbed layer 230 in the through hole 222, therefore, the etching agent of selecting for use is that the etching agent of conventional etching inner layer dielectric layer 220 materials gets final product.In the present invention, the selection ratio of preferred deep UV (ultraviolet light) absorbed layer 230 and inner layer dielectric layer 220 etch rates is 0.8: 1～1.5: 1 a etching agent, to avoid the UV Absorption layer 230 in the too fast etching through hole 222.The etching agent composition is two kinds of fluoro-gas and inert gas, and wherein a kind of fluoro-gas is CF
4, C
4F
8And C
3F
8In a kind of, its volume content is 15%～30%, another kind of fluoro-gas is CHF
3, SF
6And C
3F
8In a kind of, its volume content is 10%～20%, all the other are inert gas, its volume content is 50%～75%, described inert gas is for for argon gas, a kind of in neon or the helium.Etch rate to deep UV (ultraviolet light) absorbed layers 230 in the through hole 222 is 500～540nm/min, is 470～520nm/min to the etch rate of inner layer dielectric layer 220.When etching depth reach institute's etching medium thickness 1/3 and 2/3 between the time, stop etching, the raceway groove 250b that form in the inner layer dielectric layer 220 and the degree of depth of groove 260b are basic identical.
In a specific embodiment of the present invention, adopt following etching agent: volume percent content is 15% C
3F
8, volume percent content is 10% SF
6, volume percent content is 75% argon gas, stops after the etching, the raceway groove 250b that forms in the inner layer dielectric layer 220 and the degree of depth of groove 260b are basic identical.
Afterwards, with reference to the accompanying drawings shown in the 3G, remove the deep UV (ultraviolet light) absorbed layer 230 in photoresist 240 and the through hole 222, form through hole 222 and raceway groove 260b in the inner layer dielectric layer 220 in the zone 201 that forms dual-damascene structure, form groove 250b in the inner layer dielectric layer 220 in the zone 202 that forms metal interconnecting, wherein the degree of depth of raceway groove 260b and groove 250b is basic identical.
At last, in through hole 222, raceway groove 260b and groove 250b, fill for example copper of metal material, and to promptly forming the metal line (not shown) after the surface formation planarization.Because the degree of depth of raceway groove 260b and groove 250b is basic identical, therefore, the thickness of the metal line material that forms in raceway groove 260b and the groove 250b is also basic identical, relative and prior art, the resistance value size basically identical of different parts plain conductor.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (17)
1. the manufacture method of metal wiring structure in the semiconductor device comprises:
Form etching stop layer and inner layer dielectric layer successively on semiconductor substrate, described etching stop layer and inner layer dielectric layer comprise dual-damascene structure zone and metal interconnecting zone;
On the inner layer dielectric layer in dual-damascene structure zone, form through hole;
Form filling vias and cover the deep UV (ultraviolet light) absorbed layer of inner layer dielectric layer;
On the deep UV (ultraviolet light) absorbed layer, form photoresist layer, and the formation photoresist opening that exposes, develops, the photoresist aperture position in dual-damascene structure zone is corresponding with lead to the hole site, and the photoresist A/F is greater than the through hole width, and the photoresist aperture position in metal interconnecting zone is for forming the position of metal line;
It is characterized in that, also comprise:
The phase I etching: selecting for use the etch rate of deep UV (ultraviolet light) absorbed layer and inner layer dielectric layer is selected than greater than 1 etching agent, is mask with the photoresist layer, until the deep UV (ultraviolet light) absorbed layer of removing metal interconnecting zone photoresist aperture position fully;
The second stage etching: the inner layer dielectric layer of etching metal interconnecting zone photoresist aperture position, form raceway groove, the deep UV (ultraviolet light) absorbed layer in the inner layer dielectric layer in etching dual-damascene structure zone and the through hole forms groove;
Remove the deep UV (ultraviolet light) absorbed layer in photoresist layer and the through hole.
2. the manufacture method of metal wiring structure is characterized in that in the semiconductor device according to claim 1, and the etching agent that the phase I etching is selected for use is selected than being 2: 1～3.5: 1 the etch rate of deep UV (ultraviolet light) absorbed layer and inner layer dielectric layer.
3. the manufacture method of metal wiring structure is characterized in that in the semiconductor device according to claim 2, and described etch rate to deep UV (ultraviolet light) absorbed layer and inner layer dielectric layer is selected to contain following component than the etching agent that is 2: 1～3.5: 1:
C
4F
8, C
2F
6And C
3F
8In any one, volume percent content is 2%～10%;
CHF
3, CF
4, NF
3And SF
6In any one, volume percent content is 4%～10%;
Inert gas, volume percent content are 10%～20%;
Oxygen, volume percent content are 1%～5%; All the other are nitrogen.
4. the manufacture method of metal wiring structure is characterized in that in the semiconductor device according to claim 1, and the etching agent of second stage etching is selected than being 0.8: 1～1.5: 1 the etch rate of deep UV (ultraviolet light) absorbed layer and inner layer dielectric layer.
5. the manufacture method of metal wiring structure is characterized in that in the semiconductor device according to claim 4, and described etching agent contains following component: CF
4, C
4F
8And C
3F
8In a kind of, its volume content is 15%～30%, another kind of fluoro-gas is CHF
3, SF
6And C
3F
8In a kind of, its volume content is 10%～20%, the volume content of inert gas is 50%～75%.
6. the manufacture method of metal wiring structure is characterized in that in the semiconductor device according to claim 1, and described etching stop layer is silicon nitride or carborundum.
7. the manufacture method of metal wiring structure is characterized in that in the semiconductor device according to claim 1, and described inner layer dielectric layer is fluoride glass or carbonado.
8. the manufacture method of metal wiring structure is characterized in that in the semiconductor device according to claim 1, and described deep UV (ultraviolet light) absorbed layer is for absorbing the deep UV (ultraviolet light) oxide, and structural formula is:
9. the manufacture method of metal wiring structure in the semiconductor device comprises:
Form etching stop layer and inner layer dielectric layer successively on semiconductor substrate, described etching stop layer and inner layer dielectric layer comprise dual-damascene structure zone and metal interconnecting zone;
On the inner layer dielectric layer in dual-damascene structure zone, form through hole;
Form filling vias and cover the deep UV (ultraviolet light) absorbed layer of inner layer dielectric layer;
On the deep UV (ultraviolet light) absorbed layer, form photoresist layer, and the formation photoresist opening that exposes, develops, the photoresist aperture position in dual-damascene structure zone is corresponding with lead to the hole site, and the photoresist A/F is greater than the through hole width, and the photoresist aperture position in metal interconnecting zone is for forming the position of metal line;
It is characterized in that, also comprise:
Pre-etching: with the photoresist layer is mask, etching deep UV (ultraviolet light) absorbed layer, deep UV (ultraviolet light) absorbed layer until removing dual-damascene structure zone photoresist aperture position fully still has the deep UV (ultraviolet light) absorbed layer on the inner layer dielectric layer of the photoresist aperture position in metal interconnecting zone at this moment;
The phase I etching: selecting for use the etch rate of deep UV (ultraviolet light) absorbed layer and inner layer dielectric layer is selected than greater than 1 etching agent, is mask with the photoresist layer, until the deep UV (ultraviolet light) absorbed layer of removing metal interconnecting zone photoresist aperture position fully;
The second stage etching: the inner layer dielectric layer of etching metal interconnecting zone photoresist aperture position, form raceway groove, the deep UV (ultraviolet light) absorbed layer in the inner layer dielectric layer in etching dual-damascene structure zone and the through hole forms groove;
Remove the deep UV (ultraviolet light) absorbed layer in photoresist layer and the through hole.
10. the manufacture method of metal wiring structure is characterized in that in the semiconductor device according to claim 9, and the etching agent that the phase I etching is selected for use is selected than being 2: 1～3.5: 1 the etch rate of deep UV (ultraviolet light) absorbed layer and inner layer dielectric layer.
11. the manufacture method of metal wiring structure is characterized in that in the semiconductor device according to claim 10, described etch rate to deep UV (ultraviolet light) absorbed layer and inner layer dielectric layer is selected to contain following component than the etching agent that is 2: 1～3.5: 1:
C
4F
8, C
2F
6And C
3F
8In any one, volume percent content is 2%～10%;
CHF
3, CF
4, NF
3And SF
6In any one, volume percent content is 4%～10%;
Inert gas, volume percent content are 10%～20%;
Oxygen, volume percent content are 1%～5%; All the other are nitrogen.
12. the manufacture method of metal wiring structure is characterized in that in the semiconductor device according to claim 9, the etching agent of second stage etching is selected than being 0.8: 1～1.5: 1 the etch rate of deep UV (ultraviolet light) absorbed layer and inner layer dielectric layer.
13. the manufacture method of metal wiring structure is characterized in that in the semiconductor device according to claim 12, described etching agent contains following component: CF
4, C
4F
8And C
3F
8In a kind of, its volume content is 15%～30%, another kind of fluoro-gas is CHF
3, SF
6And C
3F
8In a kind of, its volume content is 10%～20%, the volume content of inert gas is 50%～75%.
14. the manufacture method of metal wiring structure is characterized in that in the semiconductor device according to claim 9, the etching agent of pre-etch step contains following component:
CF
4, C
4F
8, C
3F
8, C
2F
6, CHF
3, NF
3And SF
6In any one, volume percent content is 10%～25%;
Inert gas, volume percent content are 75%～90%.
15. the manufacture method of metal wiring structure is characterized in that in the semiconductor device according to claim 9, described etching stop layer is silicon nitride or carborundum.
16. the manufacture method of metal wiring structure is characterized in that in the semiconductor device according to claim 9, described inner layer dielectric layer is fluoride glass or carbonado.
17. the manufacture method of metal wiring structure is characterized in that in the semiconductor device according to claim 9, described deep UV (ultraviolet light) absorbed layer is for absorbing the deep UV (ultraviolet light) oxide, and structural formula is:
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|---|---|---|---|
| CNB200610119048XA CN100517639C (en) | 2006-12-04 | 2006-12-04 | Production method of metal wiring structure in semiconductor element |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB200610119048XA CN100517639C (en) | 2006-12-04 | 2006-12-04 | Production method of metal wiring structure in semiconductor element |
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| CN101197308A true CN101197308A (en) | 2008-06-11 |
| CN100517639C CN100517639C (en) | 2009-07-22 |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101826458B (en) * | 2009-03-02 | 2012-01-25 | 中芯国际集成电路制造(上海)有限公司 | Etching method and double-depth groove formation method |
| CN101764059B (en) * | 2008-12-25 | 2012-05-23 | 中芯国际集成电路制造(上海)有限公司 | Method for forming dual damascene structure and method for forming trench |
| CN108901149A (en) * | 2018-08-28 | 2018-11-27 | 上海美维科技有限公司 | It is a kind of can the imaging-type dielectric material method that makes two-sided printed circuit board of sunkening cord |
| CN109727910A (en) * | 2018-12-29 | 2019-05-07 | 上海华力集成电路制造有限公司 | A kind of semiconductor structure and its manufacturing method |
| WO2022142227A1 (en) * | 2021-01-04 | 2022-07-07 | 长鑫存储技术有限公司 | Semiconductor structure and preparation method therefor |
-
2006
- 2006-12-04 CN CNB200610119048XA patent/CN100517639C/en active Active
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101764059B (en) * | 2008-12-25 | 2012-05-23 | 中芯国际集成电路制造(上海)有限公司 | Method for forming dual damascene structure and method for forming trench |
| CN101826458B (en) * | 2009-03-02 | 2012-01-25 | 中芯国际集成电路制造(上海)有限公司 | Etching method and double-depth groove formation method |
| CN108901149A (en) * | 2018-08-28 | 2018-11-27 | 上海美维科技有限公司 | It is a kind of can the imaging-type dielectric material method that makes two-sided printed circuit board of sunkening cord |
| CN109727910A (en) * | 2018-12-29 | 2019-05-07 | 上海华力集成电路制造有限公司 | A kind of semiconductor structure and its manufacturing method |
| CN109727910B (en) * | 2018-12-29 | 2020-12-15 | 上海华力集成电路制造有限公司 | Semiconductor structure and manufacturing method thereof |
| WO2022142227A1 (en) * | 2021-01-04 | 2022-07-07 | 长鑫存储技术有限公司 | Semiconductor structure and preparation method therefor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100517639C (en) | 2009-07-22 |
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