CN100382439C - Self interference signal clearing method for direct frequency conversion receiver - Google Patents
Self interference signal clearing method for direct frequency conversion receiver Download PDFInfo
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- CN100382439C CN100382439C CNB2004100955771A CN200410095577A CN100382439C CN 100382439 C CN100382439 C CN 100382439C CN B2004100955771 A CNB2004100955771 A CN B2004100955771A CN 200410095577 A CN200410095577 A CN 200410095577A CN 100382439 C CN100382439 C CN 100382439C
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Abstract
The present invention relates to a self interference signal clearing method for direct frequency conversion receivers, which can cause a direct frequency conversion receiver to be applied in a time division duplexing mode (TDD). The receiver is turned on after the automatic gain control value of a receiver is adjusted to a first gain truncation point, and the gain of a variable gain amplifier of the receiver is cut off by the first gain truncation point; the automatic gain control value of the receiver is adjusted to a normal value after the receiver is turned on for certain delay time; the receiver is turned off after the automatic gain control value of the receiver is adjusted to a second gain truncation point, and the gain of the variable gain amplifier of the receiver is cut off by the second gain truncation point. The present invention adopts the gain truncation control method to eliminate or reduce the interference to receiving time slot for a self-interference of signal capacitance charging and discharging pulse, which generates because the direct frequency conversion receiver frequently receives and sends switching under the TDD mode. The gain truncation points are selected within the certain range of the automatic gain control.
Description
Technical field
The present invention relates to time division duplex mobile communication system receiver technology, the sweep-out method of the self-interference signal that produces when relating to Direct Conversion receiver in the time division duplex mobile communication system or rather and under TDD mode, working.
Background technology
The topological structure of the receiver of Direct Conversion shown in Fig. 1.Mainly comprise reception antenna 101, band pass filter (BPF) 102, low noise amplifier (LNA) 103, frequency mixer 104, frequency synthesizer (SYNTH) 105, low pass filter 111 (LPF1), 121 (LPF2), capacitor 112,122, be subjected to the variable gain amplifier 113,123 of automatic gain control AGC value control, analog to digital converter 114,124, supplementary number mode converter (Aux DAC) 12 and baseband signal processor (control circuit that contains receiver) 13.Reception antenna 101 is converted to high-frequency current signal with the space electromagnetic wave, amplify through low noise, the local frequency mixing of in frequency mixer, exporting with frequency synthesizer, divide two-way output: the one tunnel is to carry out mixing with the in-phase component of carrier wave to obtain homophase output output in-phase component I signal; Another road is that the mixed with quadrature components with carrier wave obtains quadrature output, output orthogonal component Q signal, and two paths of signals is uncorrelated mutually.Change the local frequency of frequency synthesizer 105, can make receiver receive different CF signal.Homophase output is sent baseband signal processor 13 after passing through low pass filter (111,121), capacitor (112,122), variable gain amplifier (113,123) and analog to digital converter (114,124) respectively with quadrature output.Receiver control circuit output automatic gaining controling signal in the baseband signal processor 13 is converted to automatic gain control AGC analog quantity, the amplification quantity of going to regulate variable gain amplifier (113,123) through supplementary number mode converter 12.Receiver control circuit in the baseband signal processor 13 is also exported unlatching or the shutdown signal and the configuration frequency synthesizer of receiver, goes to control the switching (local frequency) of transceiver switching and receive frequency.
The Direct Conversion receiver is compared with traditional superhet receiver, because the Direct Conversion receiver has been cancelled the intermediate frequency framework, directly radiofrequency signal is demodulated into baseband signal.Thereby has following advantage: because intermediate frequency is the zero image frequency that do not exist, therefore no longer need the image frequency filter, can simplify the design of low noise amplifier simultaneously; Cancel intermediate frequency SAW (Surface Acoustic Wave) filter (IF SAW) and corresponding medium-frequency transformation circuit, and only needed low pass filter and baseband signal amplifier.
Because there is the self-mixing phenomenon that causes because of local-oscillator leakage in the receiver of this type of topological structure, produce direct current offset, this direct current offset can cause late-class circuit saturated, forms self-interference signal.
At present, a kind of relative mature technique scheme that addresses the above problem is to adopt the mode of AC coupled, promptly utilize capacitor 112,122 to form high pass filter and remove direct current offset (DC component of carrying), be called the electric capacity of removing direct current offset, and, form the employed capacitor appearance of high pass filter value and also should choose greatly in order not damage useful signal as far as possible.
When mobile communication system is operated under the mode of frequency division duplexing, owing to do not need frequently to receive and dispatch switching, the receiver of this topological structure has excellent adaptability.But under time division duplex (TDD) pattern,, therefore when using, must cause following defective owing to need frequently to receive and dispatch in a short period of time switching:
When opening or closing receiver, electric capacity charging, discharge process that above-mentioned capacitor brings because of removing direct current offset, can produce and discharge and recharge pulse accordingly, and the main gain stage of Direct Conversion receiver is at baseband circuit, even very faint discharge and recharge pulse, after amplifying, also be easy to make late-class circuit saturated through baseband circuit, overcome the saturated needs of circuit discharge process relatively for a long time, will influence the reception of signal next time around here.
See that self-interference signal shown in Figure 2 produces schematic diagram: produce charging pulse 21 because of the electric capacity charging when receiver is opened; When receiver is closed, because of capacitor discharge produces discharge pulse 22, when receiver switches to next time accepting state again, this discharge pulse 22 will be superimposed upon next time on the received signal, impact to received signal.
In sum, when system works under TDD mode, the Direct Conversion receiver is except causing self-mixing because of local-oscillator leakage, outside the generation direct current offset, also can be owing to transmitting-receiving switching continually, produce the capacitor charge and discharge pulse, if collect mail this moment and post a letter when having the property of analogy between interval and the capacitor charge and discharge constant, this self-interference signal can bring interference to next receiving slot.This is the new problem that the Direct Conversion receiver meets with under TDD mode, causes the Direct Conversion receiver to be unsuitable for directly using in the time division duplex mobile communication system of Time Division-Synchronous Code Division Multiple Access (TD-SCDMA) class.
Summary of the invention
The objective of the invention is to design a kind of self interference signal clearing method of Direct Conversion receiver, be the removing method of the self-interference signal that produces when under TDD mode, working of Direct Conversion receiver, the Direct Conversion receiver of having eliminated self-interference signal can be directly applied under the TDD mode.
The technical scheme that realizes the object of the invention is: a kind of self interference signal clearing method of Direct Conversion receiver is characterized in that comprising:
A. again communication terminal is switched to the collection of letters after adjusting to the automatic gain control AGC value of described receiver on the first gain point of cut-off, this first gain point of cut-off blocks the gain of the variable gain amplifier of receiver, is used to make charging pulse can not influence signal and receives;
B. communication terminal is switched to the collection of letters through one section delay time after, the automatic gain of receiver control AGC value is adjusted to normal value;
C. communication terminal is switched to after adjusting to the automatic gain control AGC value of receiver on the second gain point of cut-off again and post a letter, this second gain point of cut-off blocks the gain of the variable gain amplifier of receiver, is used to make discharge pulse can not influence signal and receives.
In the described steps A, the AGC of the described first gain point of cut-off and the second gain point of cut-off is at [Vtc_min, Vtc_max] scope in value, Vtc_min is the circuit gain minimum of receiver automatic gain control AGC, and Vtc_max discharges and recharges pulse and can not influence receiver and receive pairing circuit gain maximum next time and choose according to receiver.
Described steps A, it is receiver control circuit by baseband signal processor in the receiver, commencing signal is blocked in one first gain of output before opening receiver first, this signal is converted to analog quantity through supplementary number mode converter DAC, and this analog quantity is adjusted to the AGC value of receiver on the described first gain point of cut-off.
In the described steps A, when before opening receiver first, also needing to adjust the receive frequency of receiver, also be included in and adjust this receive frequency in the Timing Advance.
Described step B, it is receiver control circuit by baseband signal processor in the receiver, after the unlatching receiver is through one section delay time, export a gain and block end signal, this signal is converted to analog quantity through supplementary number mode converter DAC, and this analog quantity is adjusted to described normal value with the AGC value of receiver.
Described step C, it is receiver control circuit by baseband signal processor in the receiver, commencing signal is blocked in one second gain of output before closing receiver, this signal is converted to analog quantity through supplementary number mode converter DAC, and this analog quantity is adjusted to the AGC value of receiver on the described second gain point of cut-off.
The present invention adopts gain to block control method and eliminates or reduce the self-interference signal of Direct Conversion receiver under time division duplex (TDD) pattern, and the point of cut-off that will gain is controlled at automatic gain and controls in the certain limit of AGC.By revising the control method of Direct Conversion receiver under TDD mode, the Direct Conversion receiver can directly be applied under the TDD mode.
Description of drawings
Fig. 1 is the topological structure schematic diagram of Direct Conversion receiver;
Fig. 2 be the Direct Conversion receiver the capacitor charge and discharge pulse of opening, producing when closing to received signal influence schematic diagram;
Fig. 3 is that the control flow block diagram is blocked in the gain of receiver when opening first;
Fig. 4 is that the control flow block diagram is blocked in the gain of receiver when closing;
Fig. 5 is after adopting gain to block control method, the Direct Conversion receiver the capacitor charge and discharge pulse of opening, producing when closing to received signal influence schematic diagram.
Embodiment
Control (Gain Truncating Control) method is blocked in the gain that the present invention proposes, be the method for blocking self-interference signal, can guarantee when received signal next time, not to be subjected to the influence of capacitor charge and discharge self-interference pulse by control receiver link gain.Below alleged unlatching receiver be that communication terminal switches to the collection of letters (cut out simultaneously and post a letter), the alleged receiver of closing is communication terminal to be switched to post a letter (closing the collection of letters simultaneously).
Referring to Fig. 3, when opening the Direct Conversion receiver first, it is by receiver control circuit in the baseband signal processor and supplementary number mode converter (DAC) that controlled function is blocked in gain, realizes by the AGC value of controlling variable gain amplifier.
Step 33, the time-delay certain hour keeps this lower AGC value in this time, to remove direct current offset (delay time can be determined according to the fresh water (FW) equality of device);
This flow process is by turning down the AGC value of receiver before opening first and again the AGC of receiver is adjusted to normal value through one section time-delay after unlatching, so receiver is opened the charging pulse that produces, method by blocking in gain has realized the self-interference signal elimination.
If when opening receiver first, also need the synthesizer of adjusting frequency, then need under the regular hour lead, carry out the local frequency adjustment, to guarantee that receiver has been stabilized on the desirable working frequency points before first Bit of receiving slot arrives.
Referring to Fig. 4, when closing the Direct Conversion receiver, it is by receiver control circuit in the baseband signal processor and supplementary number mode converter (DAC) that controlled function is blocked in gain, realizes by the AGC value of controlling variable gain amplifier.
Step 41, receiver is after receiving last Bit, block commencing signal by one second gain of the output of the receiver control circuit in the baseband signal processor, convert analog quantity to through the supplementary number mode converter, this analog quantity is adjusted to gain point of cut-off 2 with the AGC of Direct Conversion receiver, be about to the AGC value and adjust to a certain value downwards, this value can be the same or different with the value of gain point of cut-off 1.When the AGC value of this gain point of cut-off 2 can be remembered next receiver and opens as the AGC value of gain point of cut-off 1.Can whether also will readjust the AGC value of gain point of cut-off 1, be benchmark to block disturbing pulse.
The selection principle of AGC point of cut-off is through the discharging and recharging pulse and can not exert an influence to receive next time of base band amplifying circuit output, as shown in Figure 5.So the AGC value of the point of cut-off 1,2 that gains can be chosen within the specific limits.
Referring to Fig. 5, the control procedure of the inventive method shown in the figure.Reduce the AGC value before opening receiver earlier, the charging pulse 51 that produces because of the electric capacity charging when therefore opening receiver can not influence signal and receive; Through again the AGC value being returned to normal value behind one section delay time, enter normal receiving slot then; Reduce the AGC value before closing receiver earlier, the discharge pulse 52 that produces because of capacitor discharge when therefore closing receiver can not influence signal and receive.Before receiving, the electric charge on the electric capacity has discharged and has finished next time.
To the gain lower limit set of point of cut-off of the present invention is the gain minimum of AGC, is designated as Vtc_min.Do not influence to discharge and recharge pulse that to receive pairing circuit gain maximum be the gain point of cut-off upper limit next time, be designated as Vtc_max.The AGC value of point of cut-off of then gaining can be chosen in [Vtc_min, Vtc_max] scope.
The method that the present invention blocks control by gain is eliminated or is reduced the self-interference signal of Direct Conversion receiver under tdd mode, by implementing this method, and Direct Conversion collection of letters function is directly used under TDD mode.
The present invention need not change the hardware designs of existing terminal system, need not change ripe commercial Direct Conversion receiver design, by the AGC state of physical layer control receiver, the control method that adopts gain to block makes Direct Conversion receiver successful Application under TDD mode.
Claims (6)
1. the self interference signal clearing method of a Direct Conversion receiver is characterized in that comprising:
A. again communication terminal is switched to the collection of letters after adjusting to the automatic gain control AGC value of described receiver on the first gain point of cut-off, this first gain point of cut-off blocks the gain of the variable gain amplifier of receiver, is used to make charging pulse can not influence signal and receives;
B. communication terminal is switched to the collection of letters through one section delay time after, the automatic gain of receiver control AGC value is adjusted to normal value;
C. communication terminal is switched to after adjusting to the automatic gain control AGC value of receiver on the second gain point of cut-off again and post a letter, this second gain point of cut-off blocks the gain of the variable gain amplifier of receiver, is used to make discharge pulse can not influence signal and receives.
2. method according to claim 1, it is characterized in that: in the described steps A, the AGC of the described first gain point of cut-off and the second gain point of cut-off is at [Vtc_min, Vtc_max] scope in value, Vtc_min is the circuit gain minimum of receiver automatic gain control AGC, and Vtc_max discharges and recharges pulse and can not influence receiver and receive pairing circuit gain maximum next time and choose according to receiver.
3. method according to claim 1, it is characterized in that: described steps A, it is receiver control circuit by baseband signal processor in the receiver, commencing signal is blocked in one first gain of output before opening receiver first, this signal is converted to analog quantity through supplementary number mode converter DAC, and this analog quantity is adjusted to the AGC value of receiver on the described first gain point of cut-off.
4. method according to claim 1 is characterized in that: in the described steps A, when also needing to adjust the receive frequency of receiver before opening receiver first, also be included in and adjust this receive frequency in the Timing Advance.
5. method according to claim 1, it is characterized in that: described step B, it is receiver control circuit by baseband signal processor in the receiver, after the unlatching receiver is through one section delay time, export a gain and block end signal, this signal is converted to analog quantity through supplementary number mode converter DAC, and this analog quantity is adjusted to described normal value with the AGC value of receiver.
6. method according to claim 1, it is characterized in that: described step C, it is receiver control circuit by baseband signal processor in the receiver, commencing signal is blocked in one second gain of output before closing receiver, this signal is converted to analog quantity through supplementary number mode converter DAC, and this analog quantity is adjusted to the AGC value of receiver on the described second gain point of cut-off.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2004100955771A CN100382439C (en) | 2004-12-02 | 2004-12-02 | Self interference signal clearing method for direct frequency conversion receiver |
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| CNB2004100955771A CN100382439C (en) | 2004-12-02 | 2004-12-02 | Self interference signal clearing method for direct frequency conversion receiver |
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| CN100382439C true CN100382439C (en) | 2008-04-16 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101350629B (en) * | 2008-09-04 | 2012-02-22 | 北京航空航天大学 | Method for predicting latent scrambling frequency band of receiver RF system |
| US8787507B2 (en) * | 2011-07-25 | 2014-07-22 | Spreadtrum Communications USA | Detection and mitigation of interference in a receiver |
| WO2015139266A1 (en) * | 2014-03-20 | 2015-09-24 | 华为技术有限公司 | Apparatus and method for self-interference cancellation |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002027953A1 (en) * | 2000-09-29 | 2002-04-04 | Spirea Ab | Baseband front-end for multi standard receiver |
| CN1344062A (en) * | 2000-09-13 | 2002-04-10 | 日本电气株式会社 | Method and circuit of controlling baseband gain |
| CN1428941A (en) * | 2001-12-26 | 2003-07-09 | 松下电器产业株式会社 | Direct change-over receiver and receiving method of movable radio equipment and radio-frequency signal |
| WO2004047323A1 (en) * | 2002-11-18 | 2004-06-03 | Koninklijke Philips Electronics N.V. | Automatic gain control using signal and interference power to obtain extended blocking performance |
| CN1520637A (en) * | 2001-02-16 | 2004-08-11 | �����ɷ� | Direct conversion receiver architecture |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1344062A (en) * | 2000-09-13 | 2002-04-10 | 日本电气株式会社 | Method and circuit of controlling baseband gain |
| WO2002027953A1 (en) * | 2000-09-29 | 2002-04-04 | Spirea Ab | Baseband front-end for multi standard receiver |
| CN1520637A (en) * | 2001-02-16 | 2004-08-11 | �����ɷ� | Direct conversion receiver architecture |
| CN1428941A (en) * | 2001-12-26 | 2003-07-09 | 松下电器产业株式会社 | Direct change-over receiver and receiving method of movable radio equipment and radio-frequency signal |
| WO2004047323A1 (en) * | 2002-11-18 | 2004-06-03 | Koninklijke Philips Electronics N.V. | Automatic gain control using signal and interference power to obtain extended blocking performance |
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