CN100343967C - Probe for testing flat panel display and manufacturing method thereof - Google Patents

Abstract

The present invention relates to a probe for testing a flat panel display device, in which a plurality of conductors having a parallel arrangement are stacked between a plurality of other conductors, a probe assembly having the probe, and a method of manufacturing the probe and the probe assembly. The present invention provides a probe for testing a flat panel display device comprising: a plate-like dielectric; a plurality of conductors being provided in parallel; and first trenches being provided on at least one plane of upper and lower planes of the dielectric to fix the plurality of conductors in the dielectric in a predetermined arrangement.

Description

The probe of flat panel display and manufacture method thereof

Technical field

The present invention relates to be used for flat panel display probe and make the method for this probe.More specifically, the present invention relates to be used for the probe of flat panel display, wherein a plurality of conductors that are arranged in parallel are stacked between a plurality of other conductors, also relate to the probe groups that comprises probe, and the method for making this probe and probe groups.

Especially the present invention relates to be used for the probe of flat panel display, wherein need not in the manufacture process of MEMS unit, to be undertaken the technology of adhesion probe conductor, thereby obtain the accurately conductor of alignment, and relate to the method for making this probe by jointing machine.

In addition, the present invention relates to be used for the probe of flat panel display,, and relate to the method for making this probe wherein by using MEMS technology the probe conductor to be formed on two planes of single sacrificial substrate on single sacrificial substrate.

Background technology

Generally speaking, as TFT-LCD (Thin Film Transistor-LCD) equipment of flat-panel monitor comprise the lower plate that wherein provides a large amount of thin-film transistors (TFT) and each pixel electrode with preliminary dimension, with preset distance separate with lower plate be used for the look processing color filter, with preset distance separate with lower plate and thereon order provide the upper plate of current electrode and be inserted in liquid crystal between the upper and lower plates.

The gate driving electrode of capacitor area and the auxiliary capacitor zone that TFT-LCD equipment comprises a plurality of TFT as switch module, generated by the liquid crystal between the upper and lower plates, the On/Off (ON/OFF) that is used for drive TFT and be used for applying the image signal electrode of external image signal, thus predetermined image (comprising moving image) shown.

In addition, after making, to stand the test process that contacts with probe groups, with the normality of test flat plate display with eliminate the fault of flat-panel monitor in advance with flat-panel display electric pole pad as the flat-panel monitor of TFT-LCD.

This test utilization comprises that the detecting devices of probe groups carries out.Developed polytype detecting devices.This detecting devices comprises pin type detecting devices, blade type detecting devices, diaphragm type detecting devices and MEMS (MEMS (micro electro mechanical system)) detecting devices.

Recently, because flat-panel monitor is by Highgrade integration, the pattern line-width in the flat-panel monitor is very sharpening.

Therefore, exist exploitation to have a large amount of requirements of the fine pitch of excellent reproducibility and large-duty probe groups and processing flat-panel monitor.

Summary of the invention

The present invention manages to satisfy the requirement in the aforementioned exploitation.Thereby one object of the present invention be can simplified manufacturing technique to reduce process time be used for flat panel display probe and make the method for this probe.

Another object of the present invention is to remove in the production process in the MEMS unit by jointing machine (boding machine) thus come the adhesion probe conductor technology and can be with pinpoint accuracy the align probe that is used for flat panel display of probe conductor and the manufacture method of this probe.

One object of the present invention is can be by using the probe that is used for flat panel display that forms the probe conductor on two planes of MEMS technology in single sacrificial substrate on single sacrificial substrate, and the manufacture method of this probe.

In order to realize aforementioned target, one aspect of the present invention provides and is used for the probe of flat panel display, and it comprises: tabular dielectric; A plurality of conductors that are parallel to each other; First groove with at least one plane that is provided at described dielectric upward lower plane is used for predetermined arrangement a plurality of conductors being fixed in the described dielectric.

Another aspect of the present invention provides and is used for the probe of flat panel display, comprise with predetermined space and dispose and be fixed on a plurality of unit contact assembly on the film bottom respectively, wherein film has preliminary dimension, each unit contact assembly comprises shaft-like bundle element, and wherein provides detection most advanced and sophisticated in the mode that becomes one at an end of bundle element.

Another aspect of the present invention provides and is used for the probe of flat panel display, and it comprises: sacrificial substrate; First groove that utilizes photoetching process and etch process to form; Utilize conducting film to form Process configuration conductor in first groove on sacrificial substrate with predetermined space; Be formed on first dielectric of conductor top; Utilize photoetching process and etch process to form, on the sacrificial substrate lower plane, to expose second groove of conductor; By dielectric substance being imbedded formed second dielectric in the 3rd groove.

Another aspect of the present invention provides the probe that utilizes single sacrificial substrate to form, and it comprises: tabular first dielectric; Second dielectric that piles up, the difference of this step are to be formed on first dielectric top; Provide with predetermined space and to pass first and second dielectric a plurality of conductors; With by the predetermined coating method conductive layer that the stacked conductive material forms on a plane of each conductor.

Another aspect of the present invention provides the probe that utilizes single sacrificial substrate to form, and it comprises: by pile up the dielectric that ceramic wafer forms on lower plane on the epoxy resin; Be formed on a plurality of conductors on the lower plane on the dielectric with predetermined space; Be stacked on the conductive layer on the plane of each conductor by predetermined coating method; Be stacked on the supporting component that is used for fixing size of dielectric sites on the dielectric on the lower plane.

Another aspect of the present invention provides the probe that utilizes single sacrificial substrate to form, and it comprises: tabular dielectric; Be formed on a plurality of conductors on the upper and lower plane of dielectric with predetermined space; Be stacked on the conductive layer on the plane of each conductor by predetermined coating method; Be stacked on the supporting component that is used for fixing size of dielectric sites on the dielectric on the lower plane.

Another aspect of the present invention provides a kind of manufacturing and is used for the method for probe of flat panel display, it may further comprise the steps: form first groove on dielectric at least one plane of lower plane, thereby with predetermined arrangement with a plurality of conductors be fixed on the dielectric first groove form step; With stack supported assembly on plane on dielectric or the lower plane, thereby the supporting component that conductor is fixed in first groove on the dielectric forms step.

Another aspect of the present invention provides a kind of manufacturing and is used for the method for probe of flat panel display, comprising: forms the conductor formation step that the photoresist pattern with predetermined thickness forms conductor thereby utilize photoetching process and conducting film to form technology at least one plane of lower plane on the single sacrificial substrate with predetermined thickness; Utilize photoetching process to form the photoresist pattern of the middle body of opening each conductor and on the middle body that each conductor is opened, form dielectric dielectric and form step; Utilize photoetching process and etch process form groove with expose each conductor lower plane groove form step; Form step by backing material being imbedded the supporting component that forms supporting component in the groove; With the end step of removing sacrificial substrate.

Another aspect of the present invention provides a kind of manufacturing and is used for the method for probe of flat panel display, comprising: utilize photoetching process and first and second etch process to form to have first groove through first groove of the bottom of sphering technology to form step; Utilize photoetching process to open the middle body that comprises first groove, electric conducting material is imbedded in the described unlatching zone then, thereby the conductor that forms conductor forms step; Utilize photoetching process and dielectric film to form technology and form dielectric dielectric formation step on the top of each conductor; With the end step of removing sacrificial substrate.

Another aspect of the present invention provides a kind of manufacturing and is used for the method for probe tile of flat panel display, and it may further comprise the steps: form the first diaphragm pattern on sacrificial substrate, thereby limit the zone at the place, tip that will form a plurality of unit contact assembly; Thereby, the first diaphragm pattern on sacrificial substrate, forms groove by being carried out etch process as etching mask; Remove the first diaphragm pattern; On sacrificial substrate, remove the first diaphragm place and form the second diaphragm pattern, thereby qualification will form the zone that the bundle element (beam element) of unit contact assembly is located; Form the bundle element that metal film forms the unit contact assembly by on sacrificial substrate, forming the second diaphragm pattern place; Open the bundle element of unit contact assembly by removing the second diaphragm pattern; Sentence preliminary dimension cutting sacrificial substrate at the bundle element of opening the unit contact assembly; The film that will have preliminary dimension is positioned on the sacrificial substrate of cutting, and the bundle element of unit contact assembly adhered to and is fixed on the bottom of film; With the tip of opening the unit contact assembly by the sacrificial substrate of removing attachment removal and fixed film.

Another aspect of the present invention is to provide a kind of method of utilizing single sacrificial substrate to make probe, comprise: first groove that utilizes photoetching process and etch process to form first groove on lower plane on single sacrificial substrate forms step, and wherein said single sacrificial substrate has predetermined thickness; Form step by electric conducting material being imbedded the conductor that forms conductor in first groove; Second groove that utilizes photoetching process and etch process to form second groove in the bottom of described conductor forms step; By being imbedded, dielectric substance forms dielectric dielectric formation step in second groove; On at least one plane of lower plane on the sacrificial substrate, form the supporting component formation step that the dielectric place forms supporting component; With the end step of removing sacrificial substrate.

Another aspect of the present invention is to provide a kind of method of utilizing single sacrificial substrate to make probe, comprise: first diaphragm that forms first diaphragm above single sacrificial substrate forms step, wherein said single sacrificial substrate has predetermined thickness, and wherein the first diaphragm pattern is used to form conductor; Form step by electric conducting material being imbedded the upper conductor that forms upper conductor in the first diaphragm pattern; Form second diaphragm formation step that the conductor place forms second diaphragm on sacrificial substrate, wherein second diaphragm is used to form supporting component; The upper support that forms the upper support assembly in the second diaphragm pattern forms step; The groove that utilizes photoetching process and etch process to form the groove that exposes upper conductor on the lower plane of sacrificial substrate forms step; By being imbedded, dielectric substance forms dielectric dielectric formation step in the described groove; With the step of removing sacrificial substrate.

Another aspect of the present invention is to provide a kind of method of utilizing single sacrificial substrate to make probe, comprise: first groove that forms first groove on the predetermined position of single sacrificial substrate forms step, wherein said single sacrificial substrate is made by predetermined material and is experienced glossing to have predetermined thickness, and wherein said groove is used to form dielectric; Form step by dielectric substance being imbedded in first groove to form dielectric dielectric; Form the diaphragm pattern and subsequently electric conducting material is imbedded the conductor formation step that forms conductor in the diaphragm pattern by forming the dielectric place on the lower plane on described sacrificial substrate; With the end step of removing described sacrificial substrate.

Another aspect of the present invention is to provide a kind of method of utilizing single sacrificial substrate to make probe, comprising: the groove that forms the groove with desired depth on the presumptive area on plane on single sacrificial substrate forms step; On sacrificial substrate, form the groove place and form the first diaphragm pattern, thereby the first diaphragm pattern of opening described groove forms step; Groove is imbedded the groove that material imbeds in the groove of being opened by the first diaphragm pattern imbed step, wherein remove described groove and imbed material by etch process; The second diaphragm pattern that utilizes photoetching process to form second diaphragm on lower plane on the sacrificial substrate forms step, and wherein the second diaphragm pattern is used to form conductor; The conductor that forms conductor in the specific location that is limited by the second diaphragm pattern forms step; Form the 3rd diaphragm pattern formation step that the conductor place forms the 3rd diaphragm pattern on lower plane on the sacrificial substrate, wherein the 3rd diaphragm pattern is used to form supporting component; The supporting component that forms supporting component in the specific location that is limited by the 3rd diaphragm pattern forms step; Imbed the partial sacrifice substrate that material separates and remove the end step that groove is imbedded material subsequently with removing by groove.

Description of drawings

Above-mentioned and other target of the present invention, advantage will become clear by the explanation of the preferred embodiment of following connection with figures accompanying drawing, wherein:

Fig. 1 a be explain according to one embodiment of the invention be used for detect the probe of flat-panel monitor and make the perspective view of the method for this probe, Fig. 1 b is the longitdinal cross-section diagram of Fig. 1 a, Fig. 1 c is the view in transverse section of Fig. 1 a;

To be explanation detect the perspective view of technology of another embodiment of the probe of flat-panel monitor according to being used for of making of Fig. 1 a-1c for Fig. 2 a and 2b, and Fig. 2 b is the longitdinal cross-section diagram of Fig. 2 a, and Fig. 2 c is the view in transverse section of Fig. 2 a;

To be explanation detect the perspective view of another embodiment of the probe of flat-panel monitor according to being used for of making of Fig. 2 a-2c to Fig. 3 a-3e;

Fig. 4 a and 4b are the perspective views of double-deck probe that is used for detecting flat-panel monitor of explanation MEMS technology manufacturing according to the present invention;

Fig. 5 a is the perspective view of individual layer probe that is used for detecting flat-panel monitor of explanation MEMS technology manufacturing according to the present invention, and Fig. 5 b is the longitdinal cross-section diagram of Fig. 5 a;

Fig. 6 a-6p explains the sectional view of method that is used for detecting the probe of flat-panel monitor according to another embodiment manufacturing;

Fig. 7 a-7i explains the sectional view of method that is used for detecting the probe of flat-panel monitor according to another embodiment manufacturing;

Fig. 8 a-8t explains the sectional view of method that is used for detecting the probe of flat-panel monitor according to another embodiment manufacturing;

Fig. 9 explains the perspective view of method that is used for detecting the probe of flat-panel monitor according to another embodiment manufacturing;

Figure 10 a explains that decomposition diagram and Figure 10 b according to the probe of another embodiment are its sectional views;

Figure 11 is the perspective view of explaining according to another embodiment of probe that is used for detecting flat-panel monitor;

Figure 12 a-12i explains the sectional view of method that is used for detecting the probe of flat-panel monitor according to another embodiment manufacturing;

Figure 13 a-13d explains the sectional view of each technology of method that is used for detecting the probe of flat-panel monitor according to another embodiment manufacturing;

Figure 14 is the perspective view according to the probe of the manufacturing of method shown in Figure 13 a-13d;

Figure 15 a-15e explains the sectional view of each technology of method that is used for detecting the probe of flat-panel monitor according to another embodiment manufacturing;

Figure 16 is the perspective view according to the probe of the manufacturing of method shown in Figure 15 a-15e;

Figure 17 a-17c explains the sectional view of each technology of method that is used for detecting the probe of flat-panel monitor according to another embodiment manufacturing;

Figure 18 a-18c explains the sectional view of each technology of method that is used for detecting the probe of flat-panel monitor according to another embodiment manufacturing;

Figure 19 a-19d explains the sectional view of each technology of method that is used for detecting the probe of flat-panel monitor according to another embodiment manufacturing;

Figure 20 is the perspective view according to the probe of the manufacturing of method shown in Figure 17 a-17d;

Figure 21 a is that explanation is used for the perspective view and the sectional view of ceramic wafer of the present invention, and its cross section has the shape of parallelogram, and Figure 21 b is perspective view and sectional view that explanation is used for ceramic wafer of the present invention, and its cross section has stairstepping;

Figure 22 a explains the perspective view comprise according to first probe groups of the probe that is used for detecting flat-panel monitor of the present invention, and Figure 22 b is its sectional view;

Figure 23 is explanation at TCP (Tape Carrier Package band carry encapsulation) and is shown in the view of the connection between the unit conductor assembly in Figure 22 and 24;

Figure 24 a explains the perspective view comprise according to second probe groups of the probe that is used for detecting flat-panel monitor of the present invention, and Figure 24 b is its sectional view;

Figure 25 explains the perspective view that comprises according to the probe groups of probe of the present invention;

Figure 26 is that explanation comprises the sectional view according to the probe groups of probe of the present invention.

Embodiment

In specification of the present invention, should notice that " probe " is meant " probe structure " in the present invention.

At first, before the embodiment of describing in detail according to the probe that is used for detecting flat-panel monitor of the present invention, the concept structure of this probe will be described.

Shown in Fig. 1 a-1c and Fig. 2 a-2c, tabular dielectric 10 is made by dielectric substance such as pottery.Dielectric 10 preferably has the thickness of 240 μ m.And the two ends of dielectric 10 preferably have jump shape (step-difference) or the oblique shape of squint.And because dielectric 10 has the function of the probe shape kept and the function of insulation, therefore preferred this dielectric is made by hard material.

The conductor 20a that makes by nickel (Ni) or nickel alloy and 20b is shaft-like and its two terminal part has sharp-pointed shape.

The method that has different manufacturing conductors according to embodiment.In the first embodiment, form the groove wherein will insert conductor by scribing machine technology, the conductor with sharp-pointed terminal part is attached and is fixed in separately the groove, thereby conductor is provided on the dielectric 10.

In second embodiment, determine that based on photoetching process the conductor of its position and size is configured at least one plane on this upper and lower plane of dielectric with predetermined space.

Conductor 20a and 20b are provided to contact respectively the upper and lower plane of dielectric 10.Though form two column conductors respectively on dielectric upper and lower plane, a column conductor may be provided in the dielectric 10.

And, under the situation in a column conductor is provided at dielectric 10, form the individual layer probe, shown in Fig. 2 a-2c.

When observing this probe from probe top, configuration conductor 20a and 20 so that each be provided between the conductor 20b of lower plane that the conductor 20a on the plane on the dielectric 10 can be positioned in adjacent dielectric 10.

And, each length that is provided at the conductor 20a on the last plane of dielectric 10 all be provided at this dielectric lower plane on the length of each conductor 20b identical, conductor 20a that outwards stretch from dielectric 10 and a left side and the right ledge of 20b have identical length.

Shown in Fig. 1 c, the terminal part that is provided at the conductor 20a on the last plane of dielectric 10 is more more outstanding than the terminal part that is provided at the conductor 20b on dielectric 10 lower planes.Especially preferably conductor 20a and 20b are formed and make and is connected that to be provided at that the conductor 20a on the plane and the line 11 that is provided at the conductor 20b on dielectric 10 lower planes on the dielectric 10 can have with respect to each conductive surface be 30 °-60 ° angle.Employed each conductor 20a and 20b all are manufactured with the thickness of 60 ± 5 μ m.

As described later, comprise being used for detecting and mainly in the method for probe of flat-panel monitor having two embodiments of the conductor 20a that is provided on the dielectric 10 and 20b in manufacturing.First embodiment is to utilize scribing machine technology to make the method for probe, and second embodiment is to use MEMS technology to make the method for probe.

Under the situation of using MEMS technology, can on conductor 20a and 20b surface, form thin electric conducting material 40a and 40b, it has than the better conductivity of conductor.This electric conducting material preferably forms with Gold plated Layer.Forming electric conducting material 40a and 40b is in order to improve the conductivity of each conductor.

And supporting component 30a that is provided and 30b are formed by the composition of epoxy resin, ceramic wafer or epoxy resin and ceramic wafer.This supporting component contacts so that strengthen conductor 20a and 20b with the top of conductor 20a and 20b.

And, the invention discloses individual layer probe and double-deck probe.Shown in Fig. 2 a-2c, the individual layer probe comprises tabular dielectric 80 with preliminary dimension, passes dielectric and a plurality of conductors 50 of providing and form the contacted tabular supporting component 60 in a plane with the upper and lower plane of dielectric 80 with certain spaced and parallel.

Under the situation of using MEMS technology, the electric conducting material with superior electrical conductivity can be formed on the plane of each conductor 50 in the individual layer probe.This electric conducting material is gold preferably, thereby forms Gold plated Layer 70.

The assembly of individual layer probe is identical with the assembly of double-deck probe, and also has and its identical functions.Therefore, their detailed description will be omitted.

(first embodiment)

According to first embodiment, make the probe that is used for detecting flat-panel monitor in the groove by forming groove (opening) and conductor inserted and be fixed on the rectangle reinforcement plate that uses slice process to make by hard material, this conductor is used as the pin that detects flat-panel monitor thus.

Below, with reference to Fig. 3-5 first embodiment is described.

Fig. 3 a-3e is used for detecting the perspective view of probe of flat-panel monitor and the process chart that the method for this probe is made in explanation for explanation according to first embodiment of the present invention.

Being used for detecting the probe of flat-panel monitor and making in the method for this probe according to of the present invention shown in Fig. 3 a, preparation has the supporting bracket 90 of rectangular plate shape.This supporting bracket is made by for example hard material of pottery.On supporting bracket 90 plane from a side to offside with vertical formation drop-center 93, thereby can on plane on the supporting bracket 90, form opposed facing first protruding segments 91 and second protruding segments 95.

Drop-center 93 can be with formation such as scribing machines.

Then, shown in Fig. 3 b, many groove 97a that utilize scribing process on the upper surface of first and second protruding segments 91 on the supporting bracket 90 and 95, to form respectively to be needle-like and 97b.These many groove 97a and 97b are connected to drop-center 14.

And the groove 97a and the 97b that are formed on first and second protruding segments 91 and 95 have identical distance respectively, thereby face mutually shown in Fig. 3 c.Otherwise, otherwise described groove can adopt the groove 97a that is formed on first protruding segments 91 to have thin interval and be formed on groove 97b on second protruding segments 95 have thick interval or mode form.

Specifically for the degree of depth of groove 97a and 97b, preferred described groove be formed on drop-center 93 equal heights on, or described groove forms deeplyer than drop-center 93, thereby the flatness that is provided at the conductor among groove 97a and the 97b can be determined by the flatness of drop-center 93.

Then, shown in Fig. 3 d, will have the conductor 98 that predetermined length and predetermined diameter and each all have a sharp shape terminal part and be configured to respectively in first protruding segments 91 and groove 97a and 97b on second protruding segments 95 that is formed on supporting bracket 90.

Each conductor all has from the outwards outstanding predetermined lengths of supporting bracket 90, so that a terminal part of each conductor can be used as the contact assembly and another terminal part that directly contact with the test position of flat-panel monitor and can be used as coupling assembling.Conductor 98 is made by tungsten or tungsten alloy.

Shown in Fig. 3 e, with adhesive applications on supporting bracket 90 the groove 97a that provides pin or conductor (pin) 98 to be inserted into to be formed on first and second protruding segments 91 and 95 and 97b in locate, and with after-applied and cured adhesive epoxy resin for example, with attached on the conductor on the supporting bracket, thereby make probe.

The following embodiment that the manufacture method of the described probe of Fig. 3 is described with reference to Figure 4 and 5.

Fig. 4 a and 4b are that explanation is used for the probe of flat panel display and the perspective view of manufacture method thereof according to another embodiment of the present invention.

According to embodiment of the present invention be used for as shown in Figure 4, in the first embodiment another supporting bracket 100 that is formed with secondary probe on it is provided at supporting bracket 90 tops in the probe and manufacture method thereof of flat panel display.At this, supporting bracket 100 is to be made by the manufacture method identical with supporting bracket 90.

The described superposed probe that is called as probe with first embodiment that is called as probe down in the identical manufacture method manufacturing of probe.That is to say that the groove 107a that is formed on first protruding segments 101 is connected with drop-center 103, and stick with glue agent such as epoxy resin 109 and adhere to and be fixed in conductor 108 among the groove 107a.And other groove is formed on second protruding segments 105, but not shown in Fig. 4 a.

Then, shown in Fig. 4 b, utilize adhesive such as epoxy resin (not shown) will go up probe and adhere to mutually with overlapping with following probe.

Form probe conductor 108 (hereinafter being sometimes referred to as upper conductor) and test needle guide body 98 (hereinafter being sometimes referred to as lower conductor) in the mode of alternately arranging.Probe conductor 108 terminal part is all outwards manyly outstanding than the respective ends portion of each test needle guide body 98 on each.The total length of the outside ledge of last lower conductor is identical, can have identical physical condition thereby go up lower conductor.Each conductor 108 is used as the contact assembly that directly contacts with the panel display test position with a terminal part of 98, and another terminal part then is used as coupling assembling.

Though described in embodiments is double-deck probe, should be appreciated that can be according to the purpose manufacturing three or the more multi-layered probe of manufacturer.

And the attachment position of probe also can be selected decision according to the purpose of manufacturer up and down.Therefore, the supporting bracket 100 that goes up probe directly can be adhered to and is fixed on down on the supporting bracket 90 of probe.

Fig. 5 a be explanation according to another embodiment of the present invention be used for the probe of flat panel display and the perspective view of manufacture method thereof, Fig. 5 b is the sectional view of Fig. 5 a.

According to embodiment of the present invention be used for shown in Fig. 5 a and 5b, on the lower plane of supporting bracket 90, carry out following technology in the probe and manufacture method thereof of flat panel display.Promptly be similar to first embodiment, form the technology of drop-center 112, first protruding segments 110 and second protruding segments 114, form the technology of the first groove 116a and second groove (not shown among Fig. 5 a), the technology of the lower conductor 118 (having predetermined length) that passes through the first groove 116a, the second groove (not shown) and drop-center 112 is provided, thereby make two terminal parts outwards outstanding, and further utilizing adhesive such as epoxy resin to adhere to and the fixing technology of lower conductor 118 on the lower plane of supporting bracket 90 on the lower plane of supporting bracket.

Be formed on the conductor 98 on plane on the supporting bracket 90 and conductor 118 vertical the replacing that are formed on supporting bracket 100 lower planes.A terminal part at each conductor 98 on plane on the supporting bracket is all outstanding than a terminal part of each conductor 118 on the supporting bracket lower plane.Upper conductor 98 is identical with the total length of the outside ledge of lower conductor 118.

(second embodiment)

Second embodiment is to adopt MEMS technology to make the method for probe.At first, general step in the probe manufacture method will be described before the specific embodiments of describing the probe manufacture method.

In the sacrificial substrate preparation process, the sacrificial substrate that substrate constituted that preparation is made by silicon (Si) wafer and ceramic material.In general, sacrificial substrate preferably has the thickness of 400-500 μ m.

Then, form in the step, adopt dry etching process on the presumptive area of lower plane on the sacrificial substrate, to form groove at dielectric.Then, dielectric is inserted or is moulded in the groove, on sacrificial substrate, form dielectric thus.Described dielectric comprises pottery, epoxy resin etc.In other words, epoxy resin is applied in the groove, and before epoxy resin cure, will has the prefabricated ceramic wafer insertion identical and, form dielectric thus attached in the groove with each groove dimensions.Perhaps, insertion has the prefabricated ceramic wafer identical with each groove dimensions, then epoxy resin is applied in the gap between groove and the ceramic wafer, thereby connects groove and ceramic wafer, forms dielectric thus.

Though ceramic wafer is a cuboid, it can have parallelogram or stairstepping, shown in Figure 21 a and 21b.

The technology of the predetermined portions of the last lower plane of etch sacrificial substrate comprises slice process and dry etching process, wherein utilizes the diaphragm pattern that is formed by photoresist to come the etch sacrificial substrate.

Herein, under with the situation of pottery as sacrificial substrate, because sacrificial substrate itself is a dielectric, therefore forming dielectric step on sacrificial substrate top can omit.

Then, form in the step, on lower plane on the sacrificial substrate, form the pattern identical, accurately use this pattern on each position, to form conductor then with conductor shape at conductor.Conductor is preferably made by tungsten or tungsten alloy.

At first, adopt photoresist to form the pattern identical with conductor shape in the accurate location that will form conductor of sacrificial substrate.Then, utilize this pattern, form conductor with electro-plating method.As a result, probe according to the present invention has excellent accuracy and reproducibility on the lower plane on the dielectric aspect configuration space, position and the spacing between the lower conductor, thereby carries out joint technology and compare the failure rate that has reduced finished product with manual.

Owing to be to form conductor by plating technic, therefore need on the sacrificial substrate surface, form Seed Layer before the plating technic, be beneficial to carry out plating technic.At this, can adopt sputtering method to form Seed Layer.In addition, this Seed Layer is preferably made by titanium (Ti) and copper (Cu).Titanium layer has the function that increases the bond properties between sacrificial substrate and the copper layer, and the function of copper layer then is the conduct Seed Layer of plating technic subsequently.

In addition, conductor is made by nickel (Ni) or nickel alloy.

In supporting component forms step, supporting component adhered to and be moulded into form the conductor place on the sacrificial substrate.Supporting component is made by epoxy resin or pottery.Particularly, preferably by applying epoxy resin in advance and obtaining supporting component on it before the epoxy resin cure ceramic wafer being adhered to.

In other words, utilize photoresist to form the supporting component pattern, on the support membrane pattern, apply backing material then, form supporting component thus.

At last, in end step, adopt wet etching process to remove the nubbin of sacrificial substrate, obtain probe thus.

On the other hand, adopting under hard material such as the situation of pottery as sacrificial substrate, the groove that the predetermined position that the manufacture method of probe is included in the last lower plane of single sacrificial substrate of being made by dielectric substance forms the groove with desired depth forms step, wherein adopts glossing to form and has the sacrificial substrate of predetermined thickness; Form supplementary device formation step by forming the diaphragm of opening groove and metal material is imbedded the dielectric that forms dielectric formation supplementary device in the groove on sacrificial substrate, wherein metal material is the material that can utilize the wet etching process selectivity to remove; The conductor that formation has the diaphragm pattern identical with sacrificial substrate upper conductor shape and utilizes this pattern to form conductor in the exact position forms step; The supporting component that conductor formation place on lower plane on the sacrificial substrate forms supporting component forms step; And the step of removing dielectric formation supplementary device from sacrificial substrate.

At this, hard material comprises pottery, glass etc.

Below, describe being used for the structure and the manufacture method thereof of probe of flat panel display with reference to the accompanying drawings.

(embodiment 2-1)

Fig. 6 a-6p is explanation according to the sectional view of manufacture method of probe that is used for flat panel display of another embodiment.

Making in the method for probe, conductor and alignment key are provided on plane on the sacrificial substrate, thereby are beneficial to by utilizing alignment key on its lower plane, to carry out technology according to the embodiment shown in reference Fig. 6 a-6p.Shown in Fig. 6 a, utilize depositing operation such as sputtering technology, on the sacrificial substrate of making by silicon etc. 120, form Seed Layer 126 with predetermined thickness, applying the function with predetermined thickness subsequently on Seed Layer 126 is first photoresist 128 of diaphragm.

Seed Layer 126 is that the titanium layer 122 of 500  and copper layer 124 that thickness is 5000  constitute by thickness.In plating technic subsequently, copper layer 124 function in fact is a Seed Layer 126.It is in order to improve the adhesive property between sacrificial substrate 120 and the copper layer 124 that titanium layer 122 is provided.

Then, shown in Fig. 6 b, form the first photoresist pattern 129 and be used for forming the presumptive area of conductor and the alignment key in the subsequent technique with qualification.Each conductor is the contact assembly of the flat-panel monitor of direct contact measured examination.

Can there be predetermined circuit patterns to form the first photoresist pattern 129 by utilizing on it design, subsequently with its development with the mask that forms conductor and alignment key first photoresist 128 that is formed on the sacrificial substrate that exposes.

Then, shown in Fig. 6 c, (Ni-Co Ni-W-Co) forms conducting film 131 by utilizing plating technic to form the first photoresist pattern, 129 place's deposits conductive material such as nickel (Ni) and nickel alloy on sacrificial substrate.Subsequently, utilize flatening process to make the last plane planarization of sacrificial substrate 120.

Adopt CMP (chemico-mechanical polishing) method and polishing to wait and carry out flatening process.In the plating technic process that forms conducting film 131, copper layer 124 function in the Seed Layer 126 are the seed of coating material.

Specifically, in the desirable plating technic process that forms conducting film 131, only in the opening section of the first photoresist pattern 129, form under the situation of conducting film 131, can omit flatening process.

In addition, form under the situation of conducting film 131 using as PVD (physical vapour deposition (PVD)) method and CVD (chemical vapour deposition (CVD)) method rather than plating technic, the technology of aforementioned formation Seed Layer 126 of carrying out can be omitted.

Then, shown in Fig. 6 d,, form conductor and alignment key 132a and 132b thus by removing some part that the first photoresist pattern 129 comes the exposed copper layer.Can utilize the wet etching process of chemical reagent and the method for dry etching process to remove the first photoresist pattern.

Subsequently, shown in Fig. 6 e, use in the wet etching process of chemical reagent at this, utilize conductor 130 and alignment key 132a and 132b as mask, remove the Seed Layer 126 that the copper layer 124 that exposes by titanium layer 122 with because removing the first photoresist pattern 129 is constituted, conductor 130 and alignment key 132a and 132b fully outwards expose thus.

Then, shown in Fig. 6 f, a certain amount of second photoresist 134 is coated to conductor 130 on the sacrificial substrate 120 and alignment key 132a and fully outwards exposure place of 132b.

At this, when the sacrificial substrate 120 on being installed in rotating suction disc is rotated, second photoresist 134 is sprayed onto on the sacrificial substrate 120 by nozzle, can apply a certain amount of second photoresist 134 thus.

Then, shown in Fig. 6 g, the mask alignment that provides predetermined circuit patterns is coated with second photoresist, 134 places on sacrificial substrate 120, then, with its exposure and development, can form thus and be used for the second photoresist pattern 136 of complete opening conductor 130 middle bodies and alignment key 132a and 132b.

Then shown in Fig. 6 h, assign to form supporting bracket 138 by sealing with dielectric substance such as epoxy resin by the central portion of the conductor 130 of the second photoresist pattern institute complete opening.

At this, can wait the epoxy resin that forms as supporting bracket 138 by adopting printing process.

Then, shown in Fig. 6 i, by the conductor middle body planarization of grinding technics with 138 complete closed of supporting bracket made by dielectric substance such as epoxy resin in the plane on the sacrificial substrate 120.

At this, carrying out described grinding technics is the follow-up grinding technics that carries out on sacrificial substrate 120 tool back planes in order to be beneficial to.

Then, shown in Fig. 6 j, make sacrificial substrate 120 face down, and the tool back plane that grinds sacrificial substrate 120 is to predetermined thickness, in follow-up groove forming process, the etch depth of adjusting sacrificial substrate 120 is in low-level thus.

Then, shown in Fig. 6 k, on the tool back plane of sacrificial substrate 120, apply the photoresist 140 of predetermined thickness.

At this, the painting method of the 3rd photoresist 140 is identical with first and second photoresists 128 and 134.

Then, shown in Figure 61, utilize the mask that provides the particular electrical circuit pattern on it to expose and the 3rd photoresist 140 that develops subsequently, thereby form the 3rd photoresist pattern 142 of the middle body be used for opening the sacrificial substrate tool back plane.

Then, shown in Fig. 6 m, utilize the 3rd photoresist pattern 142 to carry out etch process,, form thus and be used for opening the groove 144 of sacrificial substrate 120 with complete etching Seed Layer 126 as mask.

At this, this etch process is for using the dry etching process of gaseous mixture, wherein with special ratios mixing SF ₆, C ₄F ₈And O ₂

More specifically, this etch process is to use as the so-called Bosh technology that is derived from RIE (reactive ion etching) technology of deep trench etching method and carries out.

Then, shown in Fig. 6 n, a certain amount of adhesive 146 (epoxy resin) is applied in the groove 144, this groove is formed on the tool back plane of sacrificial substrate 120, then to supporting bracket 148 pressurizations that make up by the ceramic wafer of preliminary dimension and be inserted in the groove 144, thus supporting bracket 148 is imbedded and attached in the groove 144.

Then, shown in Fig. 6 o, by the second photoresist pattern 136 and the 3rd photoresist pattern 142 of removing Fig. 6 n, so that outside supporting bracket 148, dielectric plate 138 and conductor 130 be exposed to.

At this, remove the second photoresist pattern 136 and the 3rd photoresist pattern 142 by the wet etching process of dry etching process or use chemical reagent.

At last, shown in Fig. 6 p, by outside sacrificial substrate 120 enterprising enforcements all are exposed to two end portion of each conductor 138 with the wet etching process of chemical reagent.The middle body of each conductor 130 lower plane is insulated with dielectric plate 138, and the middle body on plane on each conductor 130 is supported with supporting bracket 148, obtain probe thus.

At this, remove alignment key 132a shown in Fig. 6 o and 132b and remaining Seed Layer 126.

(embodiment 2-2)

To be explaination be used for the sectional view of method of probe of flat panel display according to another embodiment manufacturing to Fig. 7 a-7i.

Making according to this embodiment in the method for probe; shown in Fig. 7 a; on the sacrificial substrate of making by silicon etc. 200; for example using that the depositing operation of sputtering technology forms the Seed Layer 206 with predetermined thickness, is first photoresist 208 of diaphragm with the predetermined thickness coating functions on Seed Layer 206 then.

Seed Layer 206 is made of titanium layer 202 and copper layer 204.Copper layer 204 major function are seed in follow-up plating technic.It is in order to improve the adhesive property between sacrificial substrate 200 and the copper layer 204 that titanium layer is provided.

Then, shown in Fig. 7 b, form the first photoresist pattern 210 is used for forming conductor in subsequent technique with qualification presumptive area.

Can be by design on it being had mask alignment with the predetermined circuit patterns that forms conductor to first photoresist 208 that is formed on Fig. 7 a on the sacrificial substrate 200, and subsequently with its exposure and development, thereby the first photoresist pattern 210 formed.

Then, shown in Fig. 7 c, by will be for example nickel (Ni) or nickel alloy (Ni-Co, electric conducting material Ni-W-Co) utilize plating technic to be deposited on to be formed with the conducting film 212 that forms on the sacrificial substrate 200 of the first photoresist pattern 212 as contact assembly.Then, come the last plane of planarization sacrificial substrate 200 by flatening process.

This flatening process utilizes CMP (chemico-mechanical polishing) method and polishing to wait to carry out.Be used for forming in the plating technic process of conducting film 212, the function of copper layer 204 is the seed of coating material.Particularly, be used for forming in the desirable plating technic process of conducting film 212, under the situation in conducting film 212 only is formed on the expose portion of the first photoresist pattern 210, flatening process can omit.In addition, for example using PVD (physical vapour deposition (PVD)) method and CVD (chemical vapour deposition (CVD)) method rather than plating technic to form under the situation of conducting film 212, the technology of the formation Seed Layer 203 of before having carried out can be omitted.

Then, shown in Fig. 7 d, after removing the second photoresist pattern 210, utilize conducting film 212 in the expose portion be formed on the second photoresist pattern 210 as removing by titanium layer 202 from the mask that aligns and remaining in the Seed Layer 206 that the copper layer 204 on the second photoresist pattern, 210 bottoms of Fig. 7 c is constituted.

At this, the second photoresist pattern 210 can be removed by wet etch method or dry ecthing method, and Seed Layer 206 also can be removed by wet etch method or dry ecthing method.

Then, shown in Fig. 7 e, a certain amount of the 3rd photoresist 214 is coated on the sacrificial substrate 200 of the second photoresist pattern 210 of removing Fig. 7 c.

At this, the 3rd photoresist 214 can use photoresist spin-coating method commonly used to wait and apply.

Then, shown in Fig. 7 f, mask alignment by will providing the particular electrical circuit pattern on it is on the sacrificial substrate 200 that is coated with the 3rd photoresist 214, and subsequently to its exposure with develop and be used for opening the 3rd photoresist pattern 222 as the middle body of the conducting film 212 of contact assembly with formation.

Then, shown in Fig. 7 g, a certain amount of adhesive such as epoxy resin are applied in the opening section of being opened by the 3rd photoresist pattern 222, will will insert and be attached in the opening section of the 3rd photoresist pattern 222 as ceramic made supporting bracket 218 by dielectric substance subsequently with preliminary dimension.

Then, shown in Fig. 7 h, make that by the 3rd photoresist pattern 222 of removing Fig. 7 g the conductors that are made of supporting bracket 218 and conducting film 212 are exposed to outside.

At last, shown in Fig. 7 i, wait by wet etching process and to remove sacrificial substrate 200 and the Seed Layer 206 on conducting film 212 bottoms that wherein supporting bracket 218 and conducting film 212 are exposed to outer Fig. 7 h, finish the probe that comprises conducting film thus.

At this, preferably utilize the next Seed Layer 206 of removing sacrificial substrate 200 and constituting in proper order of a series of wet etching process of different chemical reagent by copper layer 204 and titanium layer 202.

In addition, additionally carry out dielectric substance such as epoxy resin are attached to technology on conducting film 212 tool back planes of the probe of being finished.

(embodiment 2-3)

To be explaination be used for the sectional view of method of probe of flat panel display according to another embodiment manufacturing to Fig. 8 a-8t.

Making according to described embodiment in the method for probe, shown in Fig. 8 a, first photoresist 252 is coated on the sacrificial substrate of being made by silicon etc. 250.

At this, first photoresist 252 can wait by the photoresist spin-coating method of knowing and apply.

Then shown in Fig. 8 b, form the first photoresist pattern 254 to limit alignment key and moulding contact assembly by on sacrificial substrate 250, carrying out subsequent technique.

At this, also subsequently its exposure and development are formed the first photoresist pattern 254 by alignment predetermined mask on sacrificial substrate 250.

Then, shown in Fig. 8 c, by the first photoresist pattern 254 on the sacrificial substrate 250 is carried out etch process as mask, form the first groove 256a and the 256b and second groove 258 that is used in sacrificial substrate 250, forming alignment key and contact assembly thus.

At this, utilize the dry etching process of reacting gas to carry out the technology of the first groove 256a and the 256b and second groove 258.

Then, shown in Fig. 8 d, after the first photoresist pattern 254 on removing the sacrificial substrate 250 that is formed with the first groove 256a and the 256b and second groove 258, for example utilizing, the depositing operation of sputtering technology forms the Seed Layer 260 with predetermined thickness.

Seed Layer 260 is that the titanium layer 261 of 500  and copper layer that thickness is 5,000  262 constitute by thickness.The major function of copper layer 262 is as Seed Layer in subsequent technique.It is in order to improve the adhesive property between sacrificial substrate 250 and the copper layer 262 that titanium layer 261 is provided.

Then, shown in Fig. 8 e, a certain amount of second photoresist 264 is coated on the sacrificial substrate 250 that is formed with Seed Layer 260.

At this, second photoresist 264 can use the photoresist spin coating proceeding of knowing to wait and apply.

Then, shown in Fig. 8 f,, form the second photoresist pattern 265 thus to limit the zone that forms the first groove 256a and the 256b and second groove 258 with being formed on second photoresist, 264 exposures on the sacrificial substrate 250 and developing.

Then, shown in Fig. 8 g, by will be for example nickel (Ni) or nickel alloy (Ni-Co, electric conducting material Ni-W-Co) utilize plating technic to be deposited on to be formed with on the sacrificial substrate 250 of the second photoresist pattern 265, to form conducting film 266.

At this, during being used for forming the plating technic of conducting film 266, the function of the copper layer 262 in the Seed Layer 260 is the seed of coating material.

Then, shown in Fig. 8 h, planarization is formed with the last plane of the sacrificial substrate 250 of conducting film 266.The flatening process on plane use CMP (chemico-mechanical polishing) method and polishing wait and carry out on the sacrificial substrate 250.

In addition, during being used for forming the desirable plating technic of conducting film 266, only form in the opening section of the second photoresist pattern 265 under the situation of conducting film 266, flatening process can omit.

Then, shown in Fig. 8 i, a certain amount of the 3rd photoresist 268 is coated on the sacrificial substrate 250 of having finished flatening process.

At this, the 3rd photoresist 268 can wait by the photoresist spin-coating method of knowing and apply.

Then, shown in Fig. 8 j, form the 3rd photoresist pattern 270 of the middle body that is used for opening the conducting film 266 that is formed on the sacrificial substrate 250.

At this, the 3rd photoresist pattern 270 can utilize the exposure technology of mask and developing process to form.

Then, shown in Fig. 8 k,, dielectric substance such as epoxy resin forms dielectric plate 272 by being imbedded in the opening section of being opened by the 3rd photoresist pattern 270.

Then, shown in Fig. 8 l, planarization is formed with the last plane of the sacrificial substrate 250 of dielectric plate 272.This flatening process use CMP (chemico-mechanical polishing) method and polishing wait and carry out.

Then, shown in Fig. 8 m, with sacrificial substrate 250 face down, and the tool back plane of grinding sacrificial substrate 250 is to having predetermined thickness.It is extremely low-level in order to form the etch depth of regulating sacrificial substrate 250 in the technology at follow-up groove carrying out this grinding technics.

Then, shown in Fig. 8 n, the 4th photoresist 276 that will have predetermined thickness is coated on the tool back plane of the sacrificial substrate 250 of carrying out grinding technics.The 4th photoresist 274 can use the photoresist painting method of knowing to apply.

Then, shown in Fig. 8 o, be formed on the 4th photoresist 274 on the sacrificial substrate 250 by exposure, and subsequently it developed, form the 4th photoresist pattern 276 of middle body that is used for opening sacrificial substrate 250 tool back planes as the middle body of sacrificial substrate 250.

Then, shown in Fig. 8 p, utilize the 4th photoresist pattern 276 to carry out etch process, on sacrificial substrate 250 tool back planes, form the 3rd groove 278 that is used for opening conducting film 266 thus as mask.At this, this etch process is for using the dry etching process of gaseous mixture, wherein with special ratios mixing SF ₆, C ₄F ₈And O ₂

More specifically, this etch process is to use as the so-called Bosh technology that is derived from RIE (reactive ion etching) technology of deep trench etching method and carries out.

Then, shown in Fig. 8 q, be applied to a certain amount of adhesive 280 in the 3rd groove 278 that is formed on sacrificial substrate 250 tool back planes as epoxy resin, then to by ceramic made supporting bracket 282 pressurization with preliminary dimension and be inserted in the 3rd groove 278, supporting bracket 282 is embedded in and attached in the 3rd groove 278 thus.

Then, shown in Fig. 8 r, supporting bracket 282 places planarization will be imbedded on the tool back plane of sacrificial substrate 250 in the 3rd groove 278 with flatening process.

This flatening process use CMP (chemico-mechanical polishing) method and polishing wait and carry out.

Then, shown in Fig. 8 s, remove the 3rd photoresist pattern 270, the 4th photoresist pattern 276 and Seed Layer 260.

At last, shown in Fig. 8 t, the use etch process is removed sacrificial substrate 250, finishes thus to comprise with the supporting component 282 and the probe that be provided at the dielectric plate 272 of conductor 284 bottoms of adhesive 280 attached to conductor 284 tops.

To be explaination be used for the perspective view of method of probe of flat panel display according to another embodiment manufacturing to Fig. 9.

In manufacture method according to the probe of described embodiment, prepare the conductor 130 of Fig. 6 o wherein and be exposed to outer first sacrificial substrate 280 and second sacrificial substrate 282 fully, or prepare wherein that the conductor 283 of Fig. 8 t is exposed to outer first sacrificial substrate 280 and second sacrificial substrate 282 fully.

At this, alignment key 288, dielectric plate 284 and conductor 286 outwards are exposed on first sacrificial substrate 280 and second sacrificial substrate 282.

Then, by reference alignment key 288 or utilize conductor 284 couplings of operator's eyes with the conductor 284 of first sacrificial substrate 280 and second sacrificial substrate 280, first sacrificial substrate 280 and second sacrificial substrate 282 are interconnected, then stick with glue agent it is adhered to mutually.

Be formed on a plurality of conductors 286 arranged perpendicular on second sacrificial substrate 282 in the clearance space between a plurality of adjacent conductors 286 that are formed on first sacrificial substrate 280, make each conductor 286 equal arranged perpendicular of second sacrificial substrate 282 thus between the adjacent conductor 286 of first sacrificial substrate 280, and more level is outstanding than the terminal part of each conductor 286 of first sacrificial substrate 280 for the terminal part of each conductor 286 of second sacrificial substrate 282, and wherein conductor forms sandwich construction.

Then, utilize the wet etching process identical to remove first sacrificial substrate 280 and second sacrificial substrate 282, can make the multilayer probe that wherein piles up probe thus with previous embodiments.

Though in the present embodiment, described double-deck probe, should be appreciated that according to the purpose of manufacturer and can make three or more multi-layered probe.

Figure 10 a makes the perspective view of elaboration according to the probe of another embodiment, and Figure 10 b is its sectional view.

Shown in Figure 10 a and 10b, form by double-decker according to the probe of the embodiment of this aspect, wherein by piling up first probe 300 and second probe 310 with adhesive substance such as the bonding dielectric plate 306 and 316 that is formed on first probe 300 of adhesive.

In first probe 300 and second probe 310, a plurality of conductors 302 and 312 are respectively with on the bottom of predetermined space attached to the supporting bracket of being made by pottery 308 and 318, and will be attached to respectively on the following middle body of conductor 302 and 312 by the dielectric plate 306 and 316 that dielectric substance such as epoxy resin 304 and 314 are made.

More specifically, in the clearance space of each conductor 312 arranged perpendicular between the adjacent conductor 302 of first probe 300 with second probe 310, be adjusted to the conductor 302 of multilayer probe and the interval between the conductor 312 the shortest thus.

In this stacked structure, the terminal part of each conductor 302 of each conductor 312 to the first probe 300 of second probe 310 is more outstanding in the horizontal direction.

In addition, in another embodiment, be respectively formed at supporting bracket 308 and 318 on first probe 300 and second probe 310 by adhesive substance such as adhesive and adhere to mutually, can make the double-decker that wherein piles up first probe 300 and second probe 310 thus.

Therefore, introduce in the probe groups (not shown) wherein in stacked structure, providing, to verify the normality of the flat-panel monitor that obtains by a series of production technologies by the sandwich construction of first probe 300 and second probe 310.

Each conductor 302 of probe and a terminal part of 312 all contact with the test position (promptly filling up electrode) of flat-panel monitor, and its another terminal part is connected to the TCP that links to each other with chip for driving (band carries encapsulation), verify the normality of flat-panel monitor thus.

(embodiment 2-4)

Figure 11 makes the perspective view of probe that be used for flat panel display of explanation according to another embodiment.As shown in figure 11, probe comprises that each is a plurality of unit conductor 320 of shaft-like bundle element 322, is provided at the most advanced and sophisticated 324a of the detection of restrainting element 322 1 ends with integration mode, with the most advanced and sophisticated 324b that is connected that is provided at bundle element 322 other ends with integration mode.Dispose a plurality of unit conductor with predetermined space respectively.

At this, bundle element 322 and most advanced and sophisticated 324a and 324b are by having excellent conductivity and flexible metal such as nickel (Ni) and nickel alloy (Ni-Co, Ni-W-Co) make, and make the end portion of each most advanced and sophisticated 324a and 324b stand sphering (rounding) technology to suppress the generation of particulate.

In addition, the transparent membrane 342 of will have preliminary dimension, being made by transparent material such as epoxy resin and Parylene (parylene) is attached on a plurality of unit conductor 320 by pressing technology and heating process.

Therefore, a plurality of unit conductor 320 is wherein introduced in the probe groups with the normality of checking by the flat-panel monitor of a series of production technologies acquisitions with the probe tile that film 342 adheres to mutually.

The most advanced and sophisticated 324b of the connection of probe tile is connected to TCP (band carries encapsulation), and this encapsulation links to each other with chip for driving, and the detection tip 324b of probe tile is touched the test position of flat-panel monitor repeatedly, promptly fills up electrode, verifies the normality of flat-panel monitor thus.

In addition, in another embodiment, can omit the most advanced and sophisticated 324b of connection of the bundle element 322 of each unit contact assembly.Omitted each the unit conductor 320 that connects tip 322 and can be connected to TCP (band carries encapsulation) by ACF (anisotropic conductive film).

Figure 12 a-12i is the sectional view that the method for the probe that is used for flat panel display shown in Figure 11 is made in explaination.

Below, with reference to Figure 12 the method for manufacturing according to the probe that is used for flat panel display of the present invention is described.At first, forming the first photoresist pattern 332 that is used in subsequent technique, forming the first groove 334a and the second groove 334b on the sacrificial substrate 330 that the certain party tropism makes as the silicon of (1,0,0) by having.

The first photoresist pattern 332 is made up of the photoresist with better photosensitivity.By on the frontal plane of substrate 330, using the photoresist of the thick about 2 μ m of spin coating proceeding spin coating, then carry out exposure technology and developing process, thereby form the first photoresist pattern 332.

Then, shown in Figure 12 b, the first photoresist pattern 332 that use is formed on the sacrificial substrate 330 carries out first etch process as mask, forms respectively thus wherein will form to detect most advanced and sophisticated 324a and the first groove 334a that is connected most advanced and sophisticated 324b and the second groove 334b.

The etch process that forms groove 334a and 334b can be to use the wet etching process that mixes the chemical reagent of potassium hydroxide (KOH) and deionized water with predetermined ratio.The wet etching process that utilizes chemical reagent anisotropically etching has certain party tropism's sacrificial substrate 330, forms the first groove 334a and the second groove 334b with truncated pyramid or truncated cone shape thus.

Then, shown in Figure 12 c, utilize the first photoresist pattern 332 to carry out second etch process, have the bottom experience sphering technology that the first groove 334a of truncated pyramid or truncated cone shape and the second groove 334b have the dark degree of depth and make groove 334a and 334b thus as etching mask.

At this, second etch process is for using with special ratios mixing SF ₆, C ₄F ₈And O ₂The dry etching process of the gaseous mixture of gas.

More specifically, second etch process is to use as the so-called Bosh technology that is derived from RIE (reactive ion etching) technology of deep trench etching method and carries out.

Then, the first groove 334a with truncated pyramid or truncated cone shape and the second groove 334b that experience first etch process have the dark degree of depth of 30 μ m-500 μ m before, and the bottom of groove 334a and 334b experience sphering technology.

Then, shown in Figure 12 d, utilizing after wet etching process removes the first photoresist pattern 332 of Figure 12 c, the thickness that is formed on function in the subsequent technique and is Seed Layer 336 on the sacrificial substrate 330 that has experienced second etch process before is the copper layer of 2,000 -3000 .

At this, the copper layer can utilize physical deposition method such as sputtering technology to form.

Then, shown in Figure 12 e, form and be used for being open at the second photoresist pattern 338 that will form bundle zone, element 332 place in the subsequent technique.

Utilize spin coating proceeding, exposure technology and developing process to form the second photoresist pattern 338 of the similar first photoresist pattern 332 that constitutes by photoresist with better photosensitivity.

Then, shown in Figure 12 f, by plating technic with having superior electrical conductivity and flexible metal material such as nickel (Ni) and nickel alloy (Ni-Co, Ni-W-Co) make metal film, form bundle element 340 by last plane then with planarization sacrificial substrate 330 such as CMP (chemico-mechanical polishing) method, etch-back method, polishings with predetermined thickness.

Yet, being used for the technology of the formation Seed Layer 336 in the plating technic that carries out technology before can omit, and has the metal film of being made by Ni, Ni-Co, Ni-W-Co etc. of predetermined thickness by formation such as CVD (chemical vapour deposition (CVD)) method, PVD (physical vapour deposition (PVD)) methods.

In addition, after carrying out flatening process, preferably remove organic material and particulate on the sacrificial substrate 330 by the cleaning of adding.

Then, shown in Figure 12 g, remove the second photoresist pattern 338 of Figure 12 f by wet etching process after, the sacrificial substrate that the second photoresist pattern 338 has been removed in cutting.

Then, shown in Figure 12 h, to be configured on the sacrificial substrate 330 of cutting by the film 342 that transparent material such as epoxy resin and Parylene are made, by pressing technology and heating process film 342 will be attached on the last plane of the bundle element 340 that is formed on the sacrificial substrate 330 subsequently.

At this, the top of the bundle element 340 that will be made of the metal film that is formed on the sacrificial substrate 330 by pressurization and heating film 342 is inserted and is attached in the film 342.

At last, shown in Figure 12 i, remove sacrificial substrate 330 by the wet etching process that uses chemical reagent, finish thus and comprise shaft-like bundle element 340, the one end is provided as contact tip 324a and the probe tile that is connected most advanced and sophisticated 324b with the other end.

(embodiment 2-5)

In first embodiment according to the manufacture method of the probe that is used for flat panel display of the present invention, shown in Figure 13 a (a), with the two sides all through the silicon with predetermined thickness (Si) wafer of polishing as sacrificial substrate 400.By adopting grinding technics or glossing, make sacrificial substrate 400 have the thickness of about 400-500 μ m.

Then, shown in Figure 13 a (b), utilize photoetching process on two planes of sacrificial substrate 400, to form first photoresist pattern 402a and the 402b corresponding to probe shape.At this, form pattern 402a and 402b by photoetching process, it can accurately be formed on the desired location thus.Therefore, compare with manual operations and can further eliminate deviation.That is, a plurality of conductors with same size can same intervals be formed on the sacrificial substrate 400, particularly, be formed on the conductor 412a on the last plane A of sacrificial substrate 400 and be formed on the mode that the conductor 412b on the lower plane B of sacrificial substrate 400 can replace mutually and be formed on the accurate position.

Therefore, shown in Figure 13 a (b), the first photoresist pattern 402a that lower plane A and B form on sacrificial substrate 400 and the second photoresist pattern 402b are formed in the dissymmetrical structure at the probe location place that formed in an alternating manner afterwards.

Then, shown in Figure 13 a (c), utilize anisotropic dry etch technology to come zone on the last plane A of the sacrificial substrate 400 that etching opens with the first photoresist pattern 402a, the groove 404 that has probe shape thus is formed on the last plane A of sacrificial substrate 400.

Then, shown in Figure 13 a (d), the lower plane B of sacrificial substrate 400 also utilize with last plane in the same technology come etching, form groove 406 thus with probe shape.At this, be formed on the groove 406 on the lower plane B of sacrificial substrate 400 and the groove 404 that is formed on the last plane A of sacrificial substrate 400 has the dissymmetrical structure that groove 404 and 406 replaces mutually.

In addition, consider in subsequent planarization technology the degree of depth of removing, be formed on the last lower plane A of sacrificial substrate 400 and the etch depth of the groove 404 on the B and 406 and be respectively 70-100 μ m, this etch depth is darker than the degree of depth (i.e. 60 μ m) of the conductor that will obtain relatively thus.

Then, shown in Figure 13 a (e), remove the last lower plane A that remains in sacrificial substrate 400 and first photoresist pattern 402a and the 402b on the B with the wet etching process that uses chemical solvent.

Then, shown in Figure 13 a (f), form Seed Layer 408a and 408b to be used on two planes of sacrificial substrate 400, forming the plating technic of conductor.At this, Seed Layer is that the titanium layer of 500  and copper layer that thickness is 5,000  constitute by thickness.The function of copper layer is the plating Seed Layer in follow-up plating technic, and titanium layer then has the function that increases the adhesive property between sacrificial substrate 400 and the copper layer.

Then, shown in Figure 13 a (g), form second photoresist pattern 410a and the 410b, with two plane A of unlatching sacrificial substrate 450 and the predetermined portions of B by photoetching process.

Then, shown in Figure 13 a (h), on two plane A of sacrificial substrate 400 and B, form by the conductor 412a and the 412b that are opened with second photoresist pattern 410a and the 410b by adopting electroplating technology.That is by utilizing the second photoresist pattern 410a and 410b, with electro-plating method deposits conductive material such as nickel (Ni) or nickel alloy (Ni-Co, Ni-W-Co) next conductor 412a and the 412b of on sacrificial substrate 400, forming as mould.

Figure 13 b (i)-(p) illustrates vertical figure and transverse view, with clear interpretation the present invention.

Shown in Figure 13 a (i), remove part outstanding from two plane A of the second photoresist pattern 410a and 410b and sacrificial substrate 400 and B, make the two plane A and the B planarization of sacrificial substrate 400 thus.At this, this flatening process utilizes CMP (chemico-mechanical polishing) method, polishing, abrasive disc (lapping) method and polishing method etc. to carry out.Yet, only be formed in the groove 404 and 406 with probe shape at conductor 412a and 412b, this conductor utilizes during being used for forming the desirable plating technic of conductor 412a and 412b under the situation that the first photoresist pattern 410a and 410b open, and can omit flatening process.In addition, after planarization conductor 412a and 412b, form Gold plated Layer on the plane thereon, can improve the conductivity of conductor thus by craft of gilding.

In addition, adopting PVD (physical vapour deposition (PVD)) method and CVD (chemical vapour deposition (CVD)) method rather than plating technic to form under the situation of conductor 412a and 412b, formation Seed Layer 408a that before carries out and the technology of 408b are unnecessary.

Then, shown in Figure 13 b (j), form the 3rd photoresist pattern 414 by adopting photoetching process, with the middle body on the last plane A that opens sacrificial substrate 400.

Then, shown in Figure 13 b (k), the zone that utilizes anisotropic dry etching process to come etching to open with the 3rd photoresist pattern 414.Herein, this etching forms first groove 416 thus up to a half thickness that proceeds to the whole sacrifice layer that comprises the part that is formed with conductor 412a.

Then, shown in Figure 13 c (l), after will being applied in first groove 416, and before epoxy resin 420 solidifies, on 418 attached thereto of the ceramic wafers that are used for supporting as dielectric thermosetting epoxy resin 420.Because ceramic wafer 418 is made by hard material, prevents probe in the function that is applied to the supporting component that is out of shape under the external force certain on the probe so ceramic wafer 418 has, and the function of keeping the gained probe shape.

When the technology that forms epoxy resin 420 and ceramic wafer 418 was finished, the technology on the last plane A of sacrificial substrate 400 was promptly finished.

Below, with the residue technology on the lower plane B of description sacrificial substrate 400.

Then, shown in Figure 13 c (m), form the 4th photoresist pattern 424 by adopting photoetching process, with the middle body on the lower plane B that opens sacrificial substrate 400.

Then, shown in Figure 13 c (n), the zone that utilizes anisotropic dry etching process to come etching to open with the 4th photoresist pattern 424.Herein, this etching forms second groove 426 that exposes epoxy resin 420 thus up to a half thickness that proceeds to the whole sacrifice layer that comprises the part that is formed with conductor 412b.

Then shown in Figure 13 d (o), will be applied in second groove 426 as dielectric thermosetting epoxy resin 428.Then, not shown, the ceramic wafer that will make by hard material also on the bottom attached to the epoxy resin 428 among the lower plane B of sacrificial substrate 400, the similar A of plane thereon.

In addition, shown in Figure 13 d (p), utilize predetermined chemicals to remove the photoresist pattern 414 and 424 on the lower plane on the sacrificial substrate 400 simultaneously, utilize the sacrificial substrate 400 of chemical reagent such as potassium hydroxide (KOH) and TMAH (Tetramethylammonium hydroxide) selective etch remnants then.

As a result, finish in an alternating manner the probe that is used for flat panel display that lower conductor 412a and 412b are gone up in configuration according to MEMS technology.

On the other hand, be used for forming Figure 13 b (k) and (n) shown in groove 416 and 426 anisotropic dry etch technology be to use with special ratios mixing SF ₆, C ₄F ₈And O ₂The dry etching process of the gaseous mixture of gas.More specifically, second etch process is to use as the so-called Bosh technology that is derived from RIE (reactive ion etching) technology of deep trench etching method and carries out.

After finishing all technologies of on sacrificial substrate 400, carrying out on the lower plane A and B, cutting sacrificial substrate 400, thus be formed on the probe groups that a plurality of conductors on the plane on the sacrificial substrate 400 can be divided into the scheduled unit that comprises predetermined number of conductors.

In other words, as shown in figure 25, cutting sacrificial substrate 400 then forms probe so that each probe groups can comprise 12 conductors.

Specifically, each conductor that is formed on the A of plane is all more outwards outstanding than the conductor that is formed on the lower plane B, and the identical length of outside ledge together.Thus, have the advantage that is beneficial to probe operation by the probe of preceding method manufacturing, the pressure of probe is identical because be applied to up and down.

According to the preceding method manufacturing probe have as shown in figure 14 shape.

Figure 14 is that explanation is by technology manufacturing shown in Figure 13 and use the perspective view of the probe of single sacrificial substrate.

As shown in figure 14, conductor 360a and 360b respectively with corresponding predetermined space configured in parallel on lower plane on the sacrificial substrate.Conductor 360a and 360b form by electric conducting material is imbedded in first groove, and this groove utilizes photoetching process and etch process to form on the last lower plane of silicon sacrificial substrate.In addition, each conductive layer film that material with conductivity higher than conductor self material is made of all serving as reasons is provided at this conducting film on the plane of each conductor 360a and 360b, thereby improves the conductivity of conductor 360a and 360b.

In addition, dielectric 362a and 362b are formed on the upper and lower plane of probe.Dielectric 362a and 362b form by dielectric substance being applied to be formed in second groove on sacrificial substrate two planes by etch process.At this, the dielectric substance preferred epoxy.

At last, in probe, provide supporting component 364.Supporting component 364 is formed at least one outer side plane of dielectric 362a and 362b.Supporting component 364 is preferably made by hard material.This hard material is preferably by upward forming ceramic wafer attached to dielectric 362a and 362b.

(embodiment 2-6)

Shown in Figure 15 a (a), planar silicon (Si) wafer of polishing both surfaces is made sacrificial substrate 450.Sacrificial substrate 450 has the thickness of the 400-500 μ m that obtains by grinding technics or glossing.

Then, shown in Figure 15 a (b), utilize sputtering technology on sacrificial substrate 450 whole, to form first Seed Layer 452 on the A of plane.At this, Seed Layer is that the titanium layer of 500  and copper layer that thickness is 5,000  constitute by thickness.The major function of copper layer is the Seed Layer in follow-up plating technic.It is in order to increase the adhesive property between sacrificial substrate 450 and the copper layer that titanium layer is provided.

Then, shown in Figure 15 a (c), utilize photoetching process to form the first photoresist pattern 454, with the zone that will form conductor on the last plane A that opens sacrificial substrate 450.

Then, shown in Figure 15 a (d), by (Ni-Co Ni-W-Co) forms first conductor 456 with electro-plating method deposits conductive material such as nickel (Ni) or nickel alloy.

Then, shown in Figure 15 a (e), planarization is partly carried out by the out-of-flatness of removing plane on it in the last plane of first conductor 456.This flatening process utilizes CMP (chemico-mechanical polishing) method, polishing, abrasive disc (lapping) method and polishing method etc. to carry out.

Yet, during the desirable plating technic that forms first conductor 456, under the situation in first conductor 456 only is formed on the part of opening with the first photoresist pattern 454, can omit flatening process.

In addition, using PVD (physical vapour deposition (PVD)) method and CVD (chemical vapour deposition (CVD)) method rather than plating technic to form under the situation of first conductor 456, the technology of formation first Seed Layer 452 of before carrying out can be omitted.

Then, shown in Figure 15 a (e), on the top of first conductor 456, carry out craft of gilding, form first Gold plated Layer 458 thus.The purpose of this technology is to improve the conductivity of probe.

Then, shown in Figure 15 a (f), utilize wet etching process to remove the first photoresist pattern 454.At this, also remove the expose portion of first Seed Layer 452.

Then, shown in Figure 15 a (g), form the second photoresist pattern 460, to open the predetermined portions of first conductor 456 by photoetching process.

Then, shown in Figure 15 a (h), the thermosetting epoxy resin 462 that will have an adhesive function is applied to utilizing on the part that the second photoresist pattern 460 opened of first conductor 456.

Then, shown in Figure 15 a (i), before epoxy resin cure, ceramic wafer 464 is attached on the top of epoxy resin 462.

Then, shown in Figure 15 b (j), utilize the last plane of grinding technics planarization ceramic wafer 464.At this, this flatening process can be identical with first embodiment.When finishing flatening process, just finished the technology on the last plane A of sacrificial substrate 450.

Below, with the technology on the lower plane b of description sacrificial substrate 450.

At first, shown in Figure 15 b (k), with sacrificial substrate 450 face down.

Then, shown in Figure 15 b (l), the lower plane B of sacrificial substrate 450 is removed up to the ID of sacrificial substrate 450 half by grinding technics.Thus, after grinding technics, the degree of depth of remaining sacrificial substrate is about 240-250 μ m.

Then, shown in Figure 15 b (m), form the 3rd photoresist pattern 466, will form dielectric part on the lower plane B that opens sacrificial substrate 450 by utilizing photoetching process.

Then, shown in Figure 15 b (n), utilize anisotropic dry etch technology to remove the predetermined portions of the sacrificial substrate 450 of opening, thus, form groove 467 with the 3rd photoresist pattern 466.Simultaneously, also remove Seed Layer 452.

Then, shown in Figure 15 b (o-l), will be applied in the groove 467 as dielectric thermosetting epoxy resin 468.

Then, shown in Figure 15 b (p-l), utilize the last plane of grinding technics planarization epoxy resin 468.

Then, shown in Figure 15 b (q-l), remove the second photoresist pattern 460 and the 3rd photoresist pattern 466, and utilize the wet etching process of KOH to remove the nubbin of sacrificial substrate 450, finish thus according to individual layer probe of the present invention by wet etching process.

At this, conductor can form have equal length from the side-prominent part of ceramic wafer 464 mediads two.

Below, will the method for double-deck probe constructed in accordance be described.

Then, shown in Figure 15 c (o-2), under the state that the technology of Figure 15 b (n) is finished, after will being applied in the groove 467 as the epoxy resin 472 of dielectric and adhesive, and before epoxy resin 470 solidifies, adhere to ceramic wafer 472.Though the ceramic wafer that adheres to has the rectangular shape of the shape that is similar to groove 467, but it can be the ceramic wafer 810 with parallelogram shape, wherein its two ends 811 and 812 tilt shown in Figure 21 a, or have the ceramic wafer 820 of stairstepping, wherein its two ends 821 and 822 are stepped shown in Figure 21 b.As a result, in the probe of making, the outside ledge of conductor has identical length, thereby can apply identical pressure during the probe operation on all probes.

Then, shown in Figure 15 c (p-2), the last plane of ceramic wafer 472 is by the grinding technics planarization.At this, what this flatening process can be with first embodiment is identical.

Then, shown in Figure 15 d (q-2), when the lower plane B of planarization sacrificial substrate 450, on the whole lower plane B of sacrificial substrate 450, be formed for second Seed Layer 474 that conductor forms plating technic.At this, Seed Layer is that the titanium layer of 500  and copper layer that thickness is 5,000  constitute by thickness.The major function of copper layer is the Seed Layer in follow-up plating technic.It is in order to increase the adhesive property between sacrificial substrate 450 and the copper layer that titanium layer is provided.

Then, shown in Figure 15 d (q-2), when forming second Seed Layer 474, form the 4th photoresist pattern 478 by photoetching process, with the part that will form conductor on the lower plane B that is open at sacrificial substrate 450.

Then, shown in Figure 15 d (r-2), by (Ni-Co Ni-W-Co) forms second conductor 478 with electro-plating method deposits conductive material such as nickel (Ni) or nickel alloy.

Then, shown in Figure 15 d (s-2), planarization is partly come by the out-of-flatness of removing plane on it in the last plane of second conductor 478.At this, this flatening process utilization method identical with first embodiment carried out.Yet, during the desirable plating technic that forms second conductor 478, under the situation in second conductor 478 only is formed on the part of opening with the 4th photoresist pattern 476, can omit flatening process.

In addition, using PVD (physical vapour deposition (PVD)) method and CVD (chemical vapour deposition (CVD)) method rather than plating technic to form under the situation of second conductor 478, the technology of formation second Seed Layer 474 of before carrying out can be omitted.Then, on the top of second conductor 478, carry out craft of gilding, form second Gold plated Layer 480 thus.The purpose of this technology is to improve the conductivity of probe.

Then, shown in Figure 15 d (t-2), utilize wet etching process to remove the 4th photoresist pattern 476.Simultaneously, also remove second Seed Layer 474 from the outwards outstanding part of conductor 478.Then, utilize photoetching process to form the 5th photoresist pattern 482, to open the predetermined portions that will form supporting component of second conductor 478.

Then, shown in Figure 15 d (u-2), thermosetting epoxy resin 484 is applied to utilizing on the part that the 5th photoresist pattern 482 opened of second conductor 478.

Then, shown in Figure 15 e (v-2), utilize the last plane planarization of grinding technics with the epoxy resin 484 that applied.At this, this flatening process is identical with first embodiment.

Then, shown in Figure 15 e (w-2), utilize wet etching process to remove the 5th and second photoresist pattern 482 and 460.

At last, shown in Figure 15 e (x-2), utilize the wet etching process of KOH to remove the nubbin of silicon sacrificial substrate 450.

Has as shown in figure 16 shape according to the probe of preceding method manufacturing.

Figure 16 for explanation use single sacrificial substrate, by the structure of the probe that is shown in the technology manufacturing among Figure 15.

Be included in the dielectric 370 of middle body according to the probe of the technology manufacturing among Figure 15, as shown in figure 16.Dielectric 370 forms by epoxy resin 370a is adhered to mutually with ceramic wafer 370b.In other words, utilize etch process to form groove at the predetermined portions of sacrificial substrate, 370a is applied in the groove with epoxy resin, and before epoxy resin 370a solidifies ceramic wafer 370b is inserted and adhere to, and forms dielectric 370 thus.At this, epoxy resin 370a is used as adhesive.

In addition, with conductor 372a and 372b with the preset space length configured in parallel on lower plane on the dielectric 570.Utilize the predetermined portions of photoetching process on lower plane on the sacrificial substrate to form the first diaphragm pattern, then electric conducting material is deposited on the zone that utilizes the unlatching of the first diaphragm pattern, form conductor 372a and 372b thus.At this,, on lower plane on the sacrificial substrate, form Seed Layer in advance forming under the situation of electric conducting material by galvanoplastic.

In addition, each conductive layer 374a and 374b make by the material with conductivity higher than the material of conductor own, conductive layer 374a and 374b are provided on the plane of each conductor 372a and 372b, to improve the conductivity of conductor.At this, electric conducting material is preferably gold (Au).

At last, protect and fixed conductor 372a and 372b by formation supporting component 376a and 376b on lower plane on the dielectric.Described supporting component 376a and 376b preferably adhere to and the pottery institute fixed is formed by epoxy resin with by epoxy resin.Reference numeral 378 refers to supporting bracket.

(embodiment 2-7)

Shown in Figure 17 a (a), the silicon wafer of polishing both surfaces is made sacrificial substrate 550.Utilize grinding technics or glossing to make sacrificial substrate 550 have the thickness of 400-500 μ m.

Then, shown in Figure 17 a (b), utilize photoetching process to form the first photoresist pattern 552, will form dielectric part to open sacrificial substrate 550.

Then, shown in Figure 17 a (c), by utilize the first photoresist pattern 552 come on the etch sacrificial substrate 550 plane A up to desired depth to form groove 551.At this, the etch depth scope is 240-250 μ m, slightly is deeper than dielectric thickness to be formed, i.e. 240 μ m.

Then, shown in Figure 17 a (d), after the epoxy resin 554 that with function is dielectric and adhesive is applied in the groove 551, and before epoxy resin 554 solidifies, adhere to ceramic wafer 556.Though accompanying ceramic wafer has the rectangular shape that is similar to groove 551 shapes, but can be ceramic wafer 820 with parallelogram shape, wherein two ends 811 and 812 tilt shown in Figure 21 a, or have stairstepping and two ends 821 and 822 are stair-stepping ceramic wafer 820.As a result, in the probe of making, the outside ledge of conductor has equal length, thereby can apply identical pressure during the probe operation to all probes.

Then, shown in Figure 17 a (e), utilize the last plane of grinding technics planarization ceramic wafer 556.At this, this flatening process is identical with first embodiment.On with ceramic wafer during the planarization of plane, utilize sputtering technology on sacrificial substrate 550 whole, to be formed for first Seed Layer 558 that conductor forms plating technic on the A of plane.

At this, Seed Layer is that the titanium layer of 500  and copper layer that thickness is 5,000  constitute by thickness.The major function of copper layer is the Seed Layer in follow-up plating technic.It is in order to increase the adhesive property between sacrificial substrate 550 and the copper layer that titanium layer is provided.

Then, shown in Figure 17 a (f), utilize photoetching process to form the second photoresist pattern 560, to open the predetermined portions that will form conductor on the sacrificial substrate 550 on the A of plane.

Then, shown in Figure 17 a (g), by (Ni-Co Ni-W-Co) forms first conductor 562 with electro-plating method deposits conductive material such as nickel (Ni) or nickel alloy.

Then, shown in Figure 17 a (h), by the out-of-flatness part or the excessive last plane of partly coming planarization first conductor 562 that forms of removing plane on first conductor 562.At this, this flatening process is identical with the disclosed method of first embodiment.

Yet, during forming the desirable plating technic of first conductor 562, under the situation in this conductor only is formed on the part that the second photoresist pattern 560 opens, can omit flatening process.

In addition, using PVD (physical vapour deposition (PVD)) method and CVD (chemical vapour deposition (CVD)) method rather than plating technic to form under the situation of first conductor 562, the technology that forms first Seed Layer 558 can be omitted.

Then, shown in Figure 17 a (i), on the top of first conductor 562, carry out craft of gilding, form first Gold plated Layer 564 thus.The purpose of this technology is to improve the conductivity of probe.

Then, shown in Figure 17 b (j), form first diaphragm 566 and be formed on first conductor 562 on the A of plane and first Gold plated Layer 564 on the sacrificial substrate 550 with protection.At this, with adhesive tape or photoresist as diaphragm.

As a result, the technology on the sacrificial substrate 550 on the A of plane is finished, and begins the technology on its lower plane B.

At first, shown in Figure 17 b (k),, then utilize grinding technics or glossing to grind the lower plane B of sacrificial substrate 550 with sacrificial substrate 550 face down.Grind sacrificial substrate 550 until the thickness that can expose ceramic wafer 556.

Then, shown in Figure 17 b (l), on whole lower plane B of sacrificial substrate 550, be formed for second Seed Layer 568 that conductor forms plating technic.Then, be beneficial to photoetching process and form the 3rd photoresist pattern 570 to open the predetermined portions that will form conductor on the sacrificial substrate 550 lower plane B.

Then, shown in Figure 17 b (m), on the part of utilizing the 3rd photoresist pattern 570 to open, form second conductor 572.

Then, shown in Figure 17 b (n), if the last plane out-of-flatness of second conductor 572, then flatening process is carried out on the plane thereon.At this, this flatening process is identical with the disclosed method of first embodiment.

Yet, during the desirable plating technic that forms second conductor 572, under the situation in second conductor 572 only is formed on the part of opening with the second photoresist pattern 570, can omit flatening process.

In addition, using PVD (physical vapour deposition (PVD)) method and CVD (chemical vapour deposition (CVD)) method rather than plating technic to form under the situation of second conductor 572, owing to do not need Seed Layer, so the technology of formation second Seed Layer 568 of carrying out before can be omitted.

Then, shown in Figure 17 b (o), on the top of second conductor 572, carry out craft of gilding, form second Gold plated Layer 574 thus.The purpose of this technology is to improve the conductivity of probe.Then, utilize wet etching process to remove and be formed on first diaphragm on the A of plane on the sacrificial substrate 550, and remove the second and the 3rd photoresist pattern 560 and 570 simultaneously.At this, the expose portion of second Seed Layer 568 also is removed.

Then, shown in Figure 17 c (p), forming second diaphragm on the plane A on the sacrificial substrate 550 with plane A on protecting.Then, utilize photoetching process to form the 4th photoresist pattern 578 to open the predetermined portions that will form supporting component on second conductor 572.

Then, shown in Figure 17 c (q), thermosetting epoxy resin 580 is applied to utilizes on the part that the 4th photoresist pattern 578 opened.

Then, shown in Figure 17 c (r), utilize the last plane of grinding technics planarization epoxy resin 580.This flatening process is identical with first embodiment.

Then, shown in Figure 17 c (s), remove second diaphragm 576 on the A of plane on the sacrificial substrate 550.Then, form the 5th photoresist pattern 582 to open the predetermined portions that will form supporting component on first conductor 562.

Then, shown in Figure 17 c (t), thermosetting epoxy resin 584 is applied to utilizes on the part that the 5th photoresist pattern 582 opened, then utilize the last plane of grinding technics planarization epoxy resin 584.

At last, shown in Figure 17 c (u), utilize wet etching process to remove the 4th and the 5th photoresist pattern 578 and 582 simultaneously, and take off and use the wet etching process selectivity of KOH to remove the nubbin of the sacrificial substrate 550 between first and second conductors 562 and 572.

When removing sacrificial substrate 550, just finished probe of the present invention.

(embodiment 2-8)

Shown in Figure 18 a (a), the silicon wafer of polishing both surfaces is made sacrificial substrate 650.Utilize grinding technics or glossing to make sacrificial substrate 650 have the thickness of 240 μ m.

Then, shown in Figure 18 a (b), the lower plane B and the adhesive tape of sacrificial substrate 650 adhered to mutually preventing pollute, or apply coating 652 as photoresist.

Then, shown in Figure 18 a (c), utilize slice process along the middle body of cutting part 653 with reservation shape cutting sacrificial substrate 650.

Then, shown in Figure 18 a (d), will have the sacrificial substrate block 654 of reservation shape, promptly the central silicon area piece of being made by slice process is removed from sacrificial substrate 650.As a result, the middle body in sacrificial substrate 650 forms groove 655.

Then, shown in Figure 18 a (e), will be inserted in the groove 655, then, apply epoxy resin 658 to be embedded in the gap between ceramic wafer 656 and the sacrificial substrate 650 as dielectric ceramic wafer 656.At this, epoxy resin has the function of bonded ceramics plate 656 and sacrificial substrate 650.

Then, shown in Figure 18 a (f), the last plane A of planarization sacrificial substrate 650.

Then, shown in Figure 18 a (g), remove the coating 652 that is formed on the sacrificial substrate 650 lower plane B, and as the lower plane B of plane A planarization sacrificial substrate 650 on it.

Then, shown in Figure 18 a (h), on the whole lower plane B of sacrificial substrate 650, be formed for first Seed Layer 660 and 662 that conductor forms plating technic.

At this, first Seed Layer 660 and 662 is that the titanium layer of 500  and copper layer that thickness is 5,000  constitute by thickness.The major function of copper layer is the Seed Layer in follow-up plating technic.It is in order to increase the adhesive property between sacrificial substrate 650 and the copper layer that titanium layer is provided.

Then; shown in Figure 18 a (i); on the lower plane B of sacrificial substrate 650, form first diaphragm 667 of protection Seed Layer 662; and utilize photoetching process on plane A on the sacrificial substrate 650, to form the first photoresist pattern 664, to open the predetermined portions that will form conductor of sacrificial substrate 650.

Then, shown in Figure 18 a (j), on the part of utilizing the first photoresist pattern 664 to be opened, form first conductor 666.At this, by (Ni-Co Ni-W-Co) forms first conductor 666 with electro-plating method deposits conductive material such as nickel (Ni) or nickel alloy.

Then, shown in Figure 18 b (k), partly come the last plane of planarization first conductor 666 by the out-of-flatness of removing plane on first conductor 666.At this, this flatening process is identical with the disclosed method of first embodiment.

Yet, during the desirable plating technic that forms first conductor 666, under the situation in first conductor 666 only is formed on the part of opening with the first photoresist pattern 664, can omit flatening process.

Then, on the whole top of first conductor 666, carry out craft of gilding, form first Gold plated Layer 668 thus.

In addition, using PVD (physical vapour deposition (PVD)) method and CVD (chemical vapour deposition (CVD)) method rather than plating technic to form under the situation of first conductor 666,, can omit so form the technology of first Seed Layer 660 owing to do not need Seed Layer.

Then, shown in Figure 18 b (l), utilize adhesive tape or photoresist to form to be used for second diaphragm 670 of the last plane A that protects the sacrificial substrate 650 that forms first conductor 666.When second diaphragm 670 forms when finishing, just finished the technology on the last plane A of sacrificial substrate 650.Then, with the sacrificial substrate face down, remove the diaphragm 667 of protection sacrificial substrate 650 lower plane B.

Below, with the technology on the lower plane B of description sacrificial substrate 650.

Then, shown in Figure 18 b (m), utilize photoetching process to form the second photoresist pattern 672 to open the predetermined portions that will form conductor on the sacrificial substrate 650 lower plane B.

Then, shown in Figure 18 b (n), form second conductor 674 in the part of utilizing the second photoresist pattern 672 to be opened.At this, by (Ni-Co Ni-W-Co) forms second conductor 674 with electro-plating method deposits conductive material such as nickel (Ni) or nickel alloy.

Then, shown in Figure 18 b (o), partly come the last plane of planarization second conductor 674 by the out-of-flatness of removing plane on second conductor 674.At this, this flatening process is identical with the disclosed method of first embodiment.After this flatening process is finished, on the whole top of second conductor 674, carry out craft of gilding, form second Gold plated Layer 676 thus.

Yet, during the desirable plating technic that forms second conductor 674, under the situation in this conductor only is formed on the part of opening with the second photoresist pattern 672, can omit flatening process.

In addition, using PVD (physical vapour deposition (PVD)) method and CVD (chemical vapour deposition (CVD)) method rather than plating technic to form under the situation of second conductor 674,, can omit so form the technology of Seed Layer 662 before owing to do not need Seed Layer.

Then, shown in Figure 18 b (p), utilize wet etching process to remove the second photoresist pattern 672.At this, also remove the expose portion of second Seed Layer 662.In addition, also can remove the first photoresist pattern of being protected by second diaphragm 670 664 simultaneously.

Then, shown in Figure 18 b (q), utilize photoetching process to form the 3rd photoresist pattern 678 to open the predetermined portions that will form supporting component on second conductor 674.

Then, shown in Figure 18 c (r), epoxy resin 680 is applied to utilizes the opening section of the 3rd photoresist pattern 678 as second conductor 674 of mould.

Then, shown in Figure 18 c (s), utilize the last plane of grinding technics planarization epoxy resin 680.

Then, shown in Figure 18 c (t), remove and be formed on second diaphragm 670 on the A of plane on the sacrificial substrate 650.Then, utilize wet etching process to remove the first photoresist pattern 664, remove the expose portion of Seed Layer 660 simultaneously.

Then, shown in Figure 18 c (u), utilize photoetching process to form the 4th photoresist pattern 682 to open the predetermined portions that will form supporting component on first conductor 666.Then, epoxy resin 684 is applied on the opening section of the conductor 666 that utilizes the 4th photoresist pattern 682.Then, utilize the last plane of grinding technics planarization epoxy resin 684.

Then, (v), utilize wet etching process to remove the third and fourth photoresist pattern 678 and 682 simultaneously, but also utilize the wet etching process of KOH to remove the nubbin of sacrificial substrate 650 as Figure 18 c.

Then, shown in Figure 18 c (w), when removing epoxy resin 658, just finished probe of the present invention.

(embodiment 2-9)

Shown in Figure 19 a (a), the ceramic wafer of polishing both surfaces is made sacrificial substrate 750.Utilize grinding technics or glossing to make the thickness of sacrificial substrate 750 be 400-500 μ m.

Then, shown in Figure 19 a (b), utilize slice process on plane A on the sacrificial substrate 750, to form two grooves 752.

Then, shown in Figure 19 a (c), be formed for first Seed Layer 754 of the plating technic of plated copper structure formation on plane A and described groove on the sacrificial substrate 750 that forms groove 752, tortuous plated copper structure is used as groove and imbeds material.At this, first Seed Layer 754 is made of titanium layer and copper layer,

Then, shown in Figure 19 a (d), utilize photoetching process to form the first photoresist pattern 756 will form the predetermined portions of groove 752 on the last plane A that is open at sacrificial substrate 750.

Then, shown in Figure 19 a (e), utilize plating technic on the groove of being opened with the first photoresist pattern 756, to form the plated copper structure 758 of imbedding material as groove.

Then, shown in Figure 19 a (f), the plated copper structure 758 of removing the first photoresist pattern 756 and projecting upwards, the last plane A of planarization sacrificial substrate thus 750 from sacrificial substrate 750.Carry out this flatening process till the surface of plane A on the sacrificial substrate 750 and plated copper structure 758 adjoin each other.

Then, shown in Figure 19 a (g), on plane A on the sacrificial substrate 750, be formed for second Seed Layer 760 that conductor forms plating technic.At this, second Seed Layer 760 is that the titanium layer of 500  and copper layer that thickness is 5,000  constitute by thickness.The major function of copper layer is the Seed Layer in follow-up plating technic.It is in order to increase the adhesive property between sacrificial substrate 750 and the copper layer that titanium layer is provided.

Then, shown in Figure 19 b (h), utilize photoetching process to form the second photoresist pattern 762 to open the part that will form conductor on the sacrificial substrate 750.

Then, shown in Figure 19 b (i), utilizing formation first conductor 764 on 762 opening sections of the second photoresist pattern.At this, by (Ni-Co Ni-W-Co) forms first conductor 764 with electro-plating method deposits conductive material such as nickel (Ni) or nickel alloy.

Then, shown in Figure 19 b (j), the out-of-flatness on the last plane by removing first conductor 764 partly comes the last plane of planarization first conductor 764.At this, this flatening process is identical with the disclosed method of first embodiment.

Yet, during the desirable plating technic that forms first conductor 764, under the situation in this conductor only is formed on the part of opening with the second photoresist pattern 762, can omit flatening process.

In addition, using PVD (physical vapour deposition (PVD)) method and CVD (chemical vapour deposition (CVD)) method rather than plating technic to form under the situation of first conductor 764,, can omit so form the technology of second Seed Layer 760 before owing to do not need Seed Layer.

Then, shown in Figure 19 b (k), on the whole top of first conductor 764, carry out craft of gilding, form first Gold plated Layer 766 thus.

Then, shown in Figure 19 b (l), form the conductor 764 be used for protecting on the last plane A that is formed on sacrificial substrate 750 and the diaphragm 768 of first Gold plated Layer 766.

Finish aforementioned technology, just finished the technology on the last plane A of sacrificial substrate 750.

Below, with the technology on the lower plane B of description sacrificial substrate 750.

At first, shown in Figure 19 b (m), grind the degree of sacrificial substrate 750 until the lower plane of lower plane B that can expose sacrificial substrate 750 and plated copper structure 758 by grinding technics.

Then, shown in Figure 19 b (n), on the whole lower plane of sacrificial substrate 750, be formed for the third sublayer 770 that conductor forms plating technic.At this, the third sublayer 770 is that the titanium layer of 500  and copper layer that thickness is 5,000  constitute by thickness.The major function of copper layer is the Seed Layer in follow-up plating technic.It is in order to increase the adhesive property between sacrificial substrate 750 and the copper layer that titanium layer is provided.Then, utilize photoetching process to form the 3rd photoresist pattern 772 to open the part that will form conductor on the sacrificial substrate 750.

Then, shown in Figure 19 c (o), on the part of utilizing the 3rd photoresist pattern 772 to be opened, form second conductor 774.At this, by (Ni-Co Ni-W-Co) forms second conductor 774 with electro-plating method deposits conductive material such as nickel (Ni) or nickel alloy.

Then, shown in Figure 19 c (p), the out-of-flatness on the last plane by removing second conductor 774 partly comes the last plane of planarization second conductor 774.At this, this flatening process is identical with the disclosed method of first embodiment.Finish after this flatening process, on the whole top of second conductor 774, carry out craft of gilding, form second Gold plated Layer 776 thus.

Yet, during the desirable plating technic that forms second conductor 774, under the situation in this conductor only is formed on the part of opening with the 3rd photoresist pattern 772, can omit flatening process.

In addition, using PVD (physical vapour deposition (PVD)) method and CVD (chemical vapour deposition (CVD)) method rather than plating technic to form under the situation of second conductor 774,, can omit so form the technology of the third sublayer 770 before owing to do not need Seed Layer.

Then, shown in Figure 19 c (q), remove diaphragm 768, and utilize wet etching process to remove the second and the 3rd photoresist pattern 762 and 772 simultaneously.At this, also remove second and the third sublayer 760 and 770 expose portion.

Then, shown in Figure 19 c (r), utilize photoetching process to form the 4th and the 5th photoresist pattern 778 and 780 to open the predetermined portions that will form supporting component on first and second conductors 764 and 774.

Then, shown in Figure 19 c (s), thermosetting epoxy resin 782 is applied to utilizes on second conductor on the part that the 4th photoresist pattern 778 opened.

Then, shown in Figure 19 d (t), utilize the last plane of grinding technics planarization epoxy resin 782.

Then, shown in Figure 19 d (u), utilize identical technology on plane on the sacrificial substrate 750, to form epoxy resin layer 784.Then, (v), utilize the last plane of grinding technics planarization epoxy resin 784 as Figure 19 d.

Then, shown in Figure 19 d (w), utilize wet etching process to remove simultaneously to remain in the 4th and the 5th photoresist pattern 778 and 780 on the last lower plane of sacrificial substrate 750.

At last, remove sacrificial substrate 750 by on remaining sacrificial substrate 750, applying external force, and remove groove by selective etch and imbed material 758, finished probe of the present invention thus.

On the other hand, Figure 20 illustrates the structure of the probe of making according to method shown in Figure 17,18 and 19.

Figure 20 makes the perspective view of explanation according to the probe of the single sacrificial substrate manufacturing formation of embodiment of the present invention utilization.

As shown in figure 20, provide dielectric 380, and on lower plane on the dielectric 380, dispose conductor 382a and 382b at interval respectively with correspondence at the probe middle body.In addition, with supporting component 384a and 384b respectively on the last lower plane attached to the dielectric 380 of configuration conductor 382a and 382b.In addition, on each each outerplanar that is provided at conductor 382a and 382b by the thin layer 386a that makes than the high material of the conductivity of electrolyte materials of conductor own and 386b.

On the predetermined portions of sacrificial substrate, form and be used for forming dielectric groove, then dielectric substance is imbedded groove, form dielectric 380 thus.The dielectric substance preferably ceramic.The interface at dielectric two ends can have jump shape or tilted shape.Utilize photoetching process on two planes of dielectric 380, to form the first photoresist pattern, form conductor 382a and 382b by deposits conductive material on the zone that utilizes the first photoresist pattern to be opened then.In addition, utilize photoetching process on two planes of the sacrificial substrate that forms conductor 382a and 382b, to form second diaphragm, backing material is imbedded utilized in the zone that second diaphragm opens then, form supporting component 384a and 384b thus.

In addition, the probe of the single sacrificial substrate of making according to embodiment 2-6 of employing has the structure identical with the probe of Figure 32 5.Thus, omission is to the specific descriptions of this probe structure.

Figure 21 a is that explanation is used for perspective view and the sectional view with ceramic wafer of parallelogram shape of the present invention, and Figure 21 b is perspective view and the sectional view that explanation is used for ceramic wafer of the present invention.These shapes go for all embodiments of the present invention.

(first embodiment of probe groups)

Figure 22 a is the perspective view that explaination comprises first probe groups of the aforementioned probe that is used for flat panel display according to the present invention, and Figure 22 b is its sectional view.At this, omit the concrete structure of aforementioned probe tile and the description of manufacture method thereof.

With reference to Figure 22 a and 22b, in the probe groups according to first embodiment of the present invention, the probe that a plurality of cellular constructions are attached and are fixed on the hyaline membrane 901 is fixed on the bottom of probe block 904.At this, each cellular construction comprises having bundle element 900 (not shown) that detect tip 902 and be connected tip 903.

Utilize two-sided tape or adhesive that probe and probe block 904 are adhered to mutually.Probe block 904 is made to guarantee its transparency by transparent material such as acrylic resin (acryl).

In addition, above probe block 904, provide first interface plate, fix by the joint of anchor door bolt 904 each other.Second contact surface plate 910 and probe holder 912 orders are provided at first interface plate, 908 tops, and also fix each other by the joint of anchor door bolt 914.

In addition, first and second interface plate 908 and 910 usefulness gim pegs 907 are engaged with further increase engaging force between the two.Also second contact surface plate 910 and probe holder 912 usefulness gim pegs 911 are engaged with further increase engaging force between the two.

The most advanced and sophisticated (not shown) of connection of a terminal part that is provided at the bundle element 900 of probe tile is connected on the pattern that is provided on the TCP (band carries encapsulation) by guiding film 930.

More specifically, the probe that forms by the connection tip by configuration on the bottom of first interface plate 908 makes up structure, then comes the engages probe and first interface plate with fixation kit 922 and anchor door bolt 924.

More specifically, will by insulating ceramic materials make go up sealing attachment assembly 926 and down sealing attachment assembly 928 be inserted between the probe and first interface plate 908 respectively and between TCP932 and the fixation kit 922.In addition, connect most advanced and sophisticated 902b and TCP932 by interconnecting at the guiding film 930 that seals up and down between attachment assembly 926 and 928.

In addition, further provide extruding anchor door bolt 929 in the bottom of fixation kit 922, the most advanced and sophisticated 902b of connection and the TCP932 of probe can more closely be interconnected thereby utilize the rotation of anchor door bolt 929 to be pressed through guiding film 930.

In addition, utilize anchor door bolt 920 that probe holder 912 and executor 916 are bonded with each other.The probe holder 912 that is connected to executor 916 can move up and down by the downward physical force F that makes progress in the test process.

More specifically, utilize guide rail 918 that a side of probe holder 912 and a side of executor are bonded with each other, so that first interface plate 908, second contact surface plate 910 be connected with probe holder 912, and probe block 904 can move up and down by the downward physical force F that makes progress in the test process.

Especially, the spring 921 that will have predetermined elastic force is provided at around the fixation kit 920 of linking probe fixture 912 and executor 916, so that first interface plate 908, second contact surface plate 910 be connected with probe holder 912, and make the probe block 904 that moves up and down by the downward physical force F that makes progress in the test process can utilize the elastic returning of spring 921 to its initial position.

In another embodiment, as shown in figure 23, omitted the fixation kit on the aforementioned bottom that is provided at first interface plate 908.In addition, will not connect most advanced and sophisticated probe beam element and TCP932 is configured on the anisotropic conductive film (ACF) 935 and utilize pressing technology and heating process that it is interconnected.

Therefore, after will being installed on the detecting devices, on flat-panel monitor, carry out the Electronic Testing process by moving to have the probe block 904 of mobile device and on the pad electrode of flat-panel monitor, apply predetermined physical power by the flat-panel monitor that a series of manufacturing flat-panel monitor technologies obtain.

At this moment, the detection most advanced and sophisticated 902 that will be positioned on the probe block 904 contacts with the pad electrode of flat-panel monitor.The electronic signal of input detecting devices is applied on the electronic pads of flat-panel monitor by TCP932, probe beam element and detection most advanced and sophisticated 902.

(second embodiment of probe groups)

Figure 24 a is the perspective view that explaination comprises second probe groups of the aforementioned probe that is used for flat panel display according to the present invention, and Figure 24 b is its sectional view.At this, omit the concrete structure of aforementioned probe tile and the description of manufacture method thereof.

With reference to Figure 24 a and 24b, in probe groups, will be used to substitute the probe block of making by the transparent material at place, first interface plate, 908 bottoms in first probe groups by the elastomeric metallic plate that has that metal such as stainless steel are made according to second embodiment of the present invention.This metallic plate 936 utilizes anchor door bolt 903 to be fixed on the bottom of first interface plate 908, and utilizes adhesive to pass through high elastic rubber 938 with the bottom of probe stationary at metallic plate 936.

Therefore,, carry out the Electronic Testing process, can increase elasticity by on the electronic pads of flat-panel monitor, applying predetermined physical power F in elastic metal sheet 936 with the place, bottom that is arranged in first interface plate 908 and second probe groups of rubber 938.

(the 3rd embodiment of probe groups)

Figure 25 is the perspective view that explaination comprises second probe groups of the aforementioned probe that is used for flat panel display according to the present invention, and Figure 26 is its sectional view.

With reference to Figure 25 and 26, in probe groups, provide multilayer probe with stacked structure according to the 3rd embodiment of the present invention.As mentioned above, multilayer probe comprises and alternately piling up and the conductor 960 of not overlapped last probe and the conductor 950 of following probe.An end portion of each conductor 960 of last probe is more outside more outstanding than each conductor 950 of following probe, and the exposed parts length of last lower conductor is identical, thereby has identical electric and physical property and conductibility.

Fixture such as anchor door bolt is adhered in the probe utilization of stacked structure to interfix on the clinoplain of probe block 955.Probe block 955 can be made to guarantee its transparency by transparent material such as acrylic resin.

First interface plate 965 and probe 970 usefulness gim pegs 967 are engaged with further raising engaging force between the two.

In addition, also second contact surface plate 975 is fixed on the dorsal part of the probe block 955 on the lower plane of first interface plate 965 by fixing two 967 joint.TCP972 is adhered to and be fixed on the lower plane of second contact surface plate 975.

For adhering to and being fixed on being connected between the TCP972 of the multilayer probe on the clinoplain of probe block 955 and the conductor 950 and 960, by being formed on the guiding in the hole (not pointing out) on the guiding film 974, each conductor 950 of multilayer probe and an end of 960 are connected to the corresponding pattern that is provided on the TCP972 by Reference numeral.

In addition, utilize anchor door bolt 982 that probe holder 970 and executor 980 are bonded with each other.The probe holder that is connected to executor 980 can move up and down by the downward physical force F that makes progress in the test process.

Especially, the spring 986 that will have predetermined elastic force is provided at around the fixation kit 982 of linking probe fixture 970 and executor 980, so that first interface plate 965 is connected with probe holder 970, and make the probe block 955 that moves up and down by the downward physical force F that makes progress in the test process can utilize the elastic returning of spring 986 to its initial position.

Therefore, after will being installed on the detecting devices, on flat-panel monitor, carry out the Electronic Testing process by moving to have the probe block 955 of mobile device and on the pad electrode of flat-panel monitor, apply predetermined physical power by the flat-panel monitor that a series of manufacturing flat-panel monitor technologies obtain.

At this moment, the pin 950 that will be positioned at probe block 955 bottoms is connected with the pad electrode of flat-panel monitor with 960.The electronic signal of input detecting devices is applied on the electronic pads of flat-panel monitor by TCP972, probe beam element and pin 950 and 960.

Commercial viability

According to the present invention, the technology of utilizing slice process and adhering to pin type conductor is easy to make probe on the supporting bracket of being made by hard material, thereby advantage is to reduce the process time of making probe, and correspondingly boosts productivity.

In addition, according to the present invention, can remove with the technology of a plurality of conductors of adhering with epoxy resin and utilize the light aligner to prevent, thereby advantage is the probe that can higher accuracy aligns because the difference of the thermal coefficient of expansion in the bonding process and the probe that manual operations of the prior art is caused do not line up.

In addition, the technology that is different from prior art, can use single sacrificial substrate according to the present invention, can reduce the quantity of highly difficult technology, and cause to improve rate of finished products owing to reduced step and improved accuracy, thereby advantage is to reduce the production prices of probe and improves process yield and productivity ratio.

Though described the present invention and advantage thereof in detail, should be appreciated that and be not limited only to previous embodiments and accompanying drawing, will also be understood that and do not deviating under the spirit and scope of the invention that limit by appended claims that those skilled in the art can make various changes, substitute and replace.

Claims (79)

1. one kind is used for the probe of flat panel display, comprising:

Tabular dielectric;

A plurality of conductors that are parallel to each other; With

Be provided at first groove on described dielectric at least one plane of going up lower plane, be used for a plurality of conductors being fixed in the described dielectric with predetermined arrangement.

2. according to the probe that is used for flat panel display of claim 1,

First and second outburst areas that wherein will have predetermined area are provided at two terminal parts on a described dielectric plane, and drop-center is provided on the described plane; With

Wherein first groove on first and second outburst areas is connected with described drop-center.

3. according to the probe that is used for flat panel display of claim 1,

Wherein provide secondary probe with overlapping with described probe; With

Wherein be parallel to each other and dispose the conductor of described overlapping probe.

4. according to the probe that is used for flat panel display of claim 2, wherein utilize slice process to form described drop-center.

5. according to the probe that is used for flat panel display of claim 1, wherein said conductor has sharp-pointed end.

6. according to the probe that is used for flat panel display of claim 1, wherein said dielectric is made by ceramic material.

7. according to the probe that is used for flat panel display of claim 1, wherein said probe also comprises and is stacked on described dielectric supporting component of going up on plane or the lower plane, conductor is fixed in first groove on the described dielectric.

8. according to the probe that is used for flat panel display of claim 1, wherein utilize photoetching process and first and second etch process to form first groove.

9. the probe that is used for flat panel display according to Claim 8,

Each first groove that wherein lives through first etch process all has truncated pyramid or truncated cone shape; With

Wherein, each first groove that has truncated pyramid or a truncated cone shape by the further etching of second etch process all experiences sphering technology until the bottom of desired depth and each first groove.

10. one kind is used for the probe of flat panel display, comprise with predetermined space and dispose and be fixed on a plurality of unit contact assembly on the film bottom respectively, wherein said film has preliminary dimension, each described unit contact assembly comprises shaft-like bundle element, and wherein provides detection most advanced and sophisticated in the mode that becomes one at an end of described bundle element.

11. according to the probe that is used for flat panel display of claim 10, wherein the other end of described bundle element provide connect most advanced and sophisticated.

12. according to the probe that is used for flat panel display of claim 11, wherein said film is made by epoxy resin or Parylene.

13. a probe that is used for flat panel display comprises:

Sacrificial substrate;

First groove that utilizes photoetching process and etch process to form;

Utilize conducting film to form Process configuration conductor in first groove on sacrificial substrate with predetermined space;

Be formed on first dielectric of described conductor top;

Utilize photoetching process and etch process to form, on the sacrificial substrate lower plane, to expose second groove of described conductor;

By dielectric substance being imbedded formed second dielectric in the 3rd groove.

14. according to the probe that is used for flat panel display of claim 13, wherein said first dielectric is made by epoxy resin.

15. according to the probe that is used for flat panel display of claim 13, wherein said second dielectric is the ceramic wafer that adheres to mutually with epoxy resin.

16. a probe that utilizes single sacrificial substrate to form comprises:

Tabular dielectric; With

Be positioned at a plurality of conductors at the groove place that forms by photoetching process and etch process, wherein electric conducting material is imbedded in the described groove, wherein with predetermined space with described a plurality of conductor arrangement on dielectric on the lower plane, and wherein be formed on the conductor on the plane and the conductor that is formed on the lower plane is a configured in parallel.

17. according to the probe that the single sacrificial substrate of the utilization of claim 16 forms, wherein said probe also comprises the tabular supporting component that is stacked on fixed conductor position on plane on the dielectric or the lower plane.

18. according to the probe that the single sacrificial substrate of the utilization of claim 16 forms, wherein said a plurality of conductors have identical length.

19. probe according to the single sacrificial substrate formation of the utilization of claim 18, wherein be formed on the dielectric the conductor on the plane towards a described dielectric side shifting preset distance, be formed on the conductor of each on the plane on the dielectric thus than being formed on each conductor on the dielectric lower plane and having a more outstanding end and another end of indent more with equal length.

20. according to the probe that the single sacrificial substrate of the utilization of claim 16 forms, wherein dielectric two ends have the jump shape, are formed on dielectric conductor of going up on the lower plane thus and outwards give prominence to equal length from dielectric.

21. according to the probe that the single sacrificial substrate of the utilization of claim 16 forms, wherein dielectric two ends have tilted shape, are formed on dielectric conductor of going up on the lower plane thus and outwards give prominence to equal length from dielectric.

22., be formed on wherein that each conductor on the plane all is configured between two adjacent conductors that are formed on the dielectric lower plane on the described dielectric according to the probe that the single sacrificial substrate of the utilization of claim 16 forms.

23. a probe that utilizes single sacrificial substrate to form comprises:

Tabular first dielectric;

Be stacked on second dielectric on the first dielectric top, wherein form jump;

Provide to pass first and second dielectric a plurality of conductors with predetermined space; With

By utilizing the predetermined coating method conductive layer that the stacked conductive material forms on a plane of each conductor.

24. according to the probe that the single sacrificial substrate of the utilization of claim 23 forms, wherein said probe also comprises the supporting component at least one plane that is stacked on plane and the second dielectric lower plane on first dielectric.

25. a probe that utilizes single sacrificial substrate to form comprises:

By on lower plane on the epoxy resin, piling up the dielectric that ceramic wafer forms;

Be formed on a plurality of conductors on the lower plane on the described dielectric with predetermined space;

Utilize predetermined coating method to be stacked on conductive layer on the plane of each conductor; With

Be stacked on described dielectric supporting component of going up fixing described conductor position on the lower plane.

26. a probe that utilizes single sacrificial substrate to form comprises:

Tabular dielectric;

Be formed on a plurality of conductors on the lower plane on the described dielectric with predetermined space;

Utilize predetermined coating method to be stacked on conductive layer on the plane of each conductor; With

Be stacked on described dielectric supporting component of going up fixing described conductor position on the lower plane.

27. a manufacturing is used for the method for probe of flat panel display, may further comprise the steps:

Form first groove on dielectric at least one plane of lower plane, thereby first groove that a plurality of conductors are fixed on the described dielectric is formed step with predetermined arrangement;

Stack supported assembly on dielectric or on the lower plane, thus the supporting component that conductor is fixed in first groove on the described dielectric forms step.

28. be used for the method for probe of flat panel display according to the manufacturing of claim 27,

Wherein said method also is included in the drop-center that forms drop-center on dielectric middle section and forms step, thereby form first outburst area and second outburst area in dielectric two side portions, and described first and second outburst areas has predetermined area; With

First groove that wherein is positioned on described first and second outburst areas is connected with drop-center.

29. be used for the method for probe of flat panel display according to the manufacturing of claim 27, wherein secondary probe is stacked on the described probe, and the wherein conductor of secondary probe and the conductor configured in parallel of described probe.

30. be used for the method for probe of flat panel display according to the manufacturing of claim 28, wherein first groove and drop-center utilize slice process to form.

31. be used for the method for probe of flat panel display according to the manufacturing of claim 28, the interval that wherein is formed on first groove of first outburst area is different from the interval of first groove that is formed on second outburst area.

32. be used for the method for probe of flat panel display according to the manufacturing of claim 27, wherein described dielectric on or form supporting component on the lower plane conductor is fixed in first groove on the described dielectric.

33. a manufacturing is used for the method for probe of flat panel display, may further comprise the steps:

Utilize photoetching process and conducting film to form technology and at least one plane of lower plane on the single sacrificial substrate with predetermined thickness, form photoresist pattern, thereby the conductor that forms conductor forms step with predetermined thickness;

Utilize photoetching process to form the photoresist pattern of the middle body of opening each conductor, and on the middle body that each conductor is opened, form dielectric dielectric formation step;

Utilize photoetching process and etch process form groove with expose each conductor lower plane groove form step;

Form step by backing material being imbedded the supporting component that forms supporting component in the groove; With

Remove the end step of sacrificial substrate.

34. be used for the method for probe of flat panel display according to the manufacturing of claim 33, wherein before conductor forms step, the Seed Layer that Seed Layer is formed at the top that described method also is included in sacrificial substrate forms step.

35. be used for the method for probe of flat panel display according to the manufacturing of claim 33, wherein form in the step at conductor, form conductor and alignment key simultaneously, described alignment key is with preset distance and conductor separation.

36. be used for the method for probe of flat panel display according to the manufacturing of claim 33, wherein form in the step at conductor, before conductor forms, form Seed Layer on the top of sacrificial substrate.

37. be used for the method for probe of flat panel display according to the manufacturing of claim 33, wherein form step and supporting component forms in the step at dielectric, after forming dielectric and supporting component, grind described dielectric and supporting component.

38. a manufacturing is used for the method for probe of flat panel display, may further comprise the steps:

First groove that utilizes photoetching process and first and second etch process to form first groove with bottom of passing through sphering technology forms step;

Utilize photoetching process to open the middle body that comprises first groove, electric conducting material is imbedded in the described unlatching zone then, thereby the conductor that forms conductor forms step;

Utilize photoetching process and dielectric film to form technology and form dielectric dielectric formation step on the top of each conductor; With

Remove the end step of sacrificial substrate.

39. be used for the method for probe of flat panel display according to the manufacturing of claim 38, wherein after first groove forms step and before conductor forms step, described method also comprises the Seed Layer formation step that forms Seed Layer.

40. be used for the method for probe of flat panel display according to the manufacturing of claim 38,

Wherein each first groove through first etch process all has truncated pyramid or truncated cone shape;

Wherein each first groove that has truncated pyramid or truncated cone shape by the further etching of second etch process is until desired depth, and makes the bottom experience sphering technology of each first groove.

41. a manufacturing is used for the method for probe of flat panel display, may further comprise the steps:

On sacrificial substrate, form the first diaphragm pattern, thereby limit the zone at the place, tip that will form a plurality of unit contact assembly;

Thereby, the first diaphragm pattern on sacrificial substrate, forms groove by being carried out etch process as etching mask;

Remove the first diaphragm pattern;

On sacrificial substrate, remove the first diaphragm place and form the second diaphragm pattern, thereby qualification will form the zone at the bundle element place of unit contact assembly;

Form the bundle element that metal film forms the unit contact assembly by on sacrificial substrate, forming the second diaphragm pattern place;

Open the bundle element of unit contact assembly by removing the second diaphragm pattern;

Sentence preliminary dimension cutting sacrificial substrate at the bundle element of opening the unit contact assembly;

The film that will have preliminary dimension is positioned on the sacrificial substrate of cutting, and the bundle element of unit contact assembly adhered to and is fixed on the bottom of film; With

By the tip of opening the unit contact assembly except that the sacrificial substrate of attachment removal and fixed film.

42. be used for the method for probe of flat panel display according to the manufacturing of claim 41, the step that wherein forms the first and second diaphragm patterns is:

On sacrificial substrate, apply the step of photoresist; With

The step of the exposure and the described photoresist that develops.

43. be used for the method for probe of flat panel display according to the manufacturing of claim 41, wherein said film is made by epoxy resin or Parylene.

44. a method of utilizing single sacrificial substrate to make probe comprises:

First groove that utilizes photoetching process and etch process to form first groove on lower plane on single sacrificial substrate forms step, and wherein said single sacrificial substrate has predetermined thickness;

Form step by electric conducting material being imbedded the conductor that forms conductor in first groove;

Second groove that utilizes photoetching process and etch process to form second groove in the bottom of described conductor forms step;

By being imbedded, dielectric substance forms dielectric dielectric formation step in second groove;

On at least one plane of lower plane on the sacrificial substrate, form the supporting component formation step that the dielectric place forms supporting component; With

Remove the end step of sacrificial substrate.

45. according to the method for the single sacrificial substrate manufacturing of the utilization of claim 44 probe, wherein said sacrificial substrate is a silicon wafer.

46. make the method for probe according to the single sacrificial substrate of the utilization of claim 44, wherein said dielectric formation is by being applied to epoxy resin in the groove and before epoxy resin cure ceramic wafer being inserted subsequently and attached to carrying out in first groove, wherein said ceramic wafer is prefabricated into the size that is fit to be inserted in the groove.

47. make the method for probe according to the single sacrificial substrate of the utilization of claim 44, wherein said dielectric formation is by ceramic wafer being inserted in the groove and subsequently epoxy resin being applied and attached to carrying out in the gap that forms between described groove and the described ceramic wafer, wherein said ceramic wafer being prefabricated into the size that is fit to be inserted in the groove.

48. the method according to the single sacrificial substrate manufacturing of the utilization of claim 44 probe wherein forms in the step at conductor, forms conductor by forming Seed Layer and carry out electroplating technology subsequently above sacrificial substrate.

49. according to the method for the single sacrificial substrate manufacturing of the utilization of claim 44 probe, wherein said method comprises that also the conductive layer by utilizing plating technic stacked conductive material on plane on the conductor to form conductive layer forms step.

50. a method of utilizing single sacrificial substrate to make probe comprises:

First diaphragm that forms first diaphragm above single sacrificial substrate forms step, and wherein said single sacrificial substrate has predetermined thickness, and wherein the first diaphragm pattern is used to form conductor;

Form step by electric conducting material being imbedded the upper conductor that forms upper conductor in the first diaphragm pattern;

Form second diaphragm formation step that the conductor place forms second diaphragm on sacrificial substrate, wherein second diaphragm is used to form supporting component;

The upper support that forms the upper support assembly in the second diaphragm pattern forms step;

The groove that utilizes photoetching process and etch process to form the groove that exposes upper conductor on the lower plane of sacrificial substrate forms step;

By being imbedded, dielectric substance forms dielectric dielectric formation step in the described groove; With

Remove the step of sacrificial substrate.

51. according to the method for the single sacrificial substrate manufacturing of the utilization of claim 50 probe,

Wherein before removing the step of sacrificial substrate, described method also comprises by forming the 3rd diaphragm pattern above the dielectric in being formed on dielectric formation step and subsequently electric conducting material being imbedded the lower conductor formation step that forms lower conductor in the 3rd diaphragm pattern; With

Wherein after lower conductor formation step, described method also is included in the lower supporting assembly formation step that the lower conductor top forms the 4th diaphragm pattern and form lower supporting assembly subsequently in the 4th diaphragm pattern.

52. according to the method for the single sacrificial substrate manufacturing of the utilization of claim 50 probe, wherein said sacrificial substrate is a silicon wafer.

53. make the method for probe according to the single sacrificial substrate of the utilization of claim 50, wherein said dielectric formation is by being applied to epoxy resin in the groove and before epoxy resin cure ceramic wafer being inserted subsequently and attached to carrying out in first groove, wherein said ceramic wafer is prefabricated into the size that is fit to be inserted in the groove.

54. make the method for probe according to the single sacrificial substrate of the utilization of claim 50, wherein said dielectric formation is by ceramic wafer being inserted in the groove and subsequently epoxy resin being applied and attached to carrying out in the gap that forms between described groove and the described ceramic wafer, wherein said ceramic wafer being prefabricated into the size that is fit to be inserted in the groove.

55. the method according to the single sacrificial substrate manufacturing of the utilization of claim 50 probe wherein forms in the step at conductor, forms conductor by forming Seed Layer and carry out electroplating technology subsequently above sacrificial substrate.

56. according to the method for the single sacrificial substrate manufacturing of the utilization of claim 50 probe, wherein said method comprises that also the conductive layer by utilizing plating technic stacked conductive material on plane on the conductor to form conductive layer forms step.

57. the method according to the single sacrificial substrate manufacturing of the utilization of claim 50 probe wherein forms in the step at supporting component, utilizes photoetching process and etch process to form groove, subsequently backing material is applied in the described groove, thereby forms supporting component.

58. a method of utilizing single sacrificial substrate to make probe comprises:

First groove that forms first groove on the predetermined position of single sacrificial substrate forms step, and wherein said single sacrificial substrate is made by predetermined material and experienced glossing to have predetermined thickness, and wherein said groove is used to form dielectric;

Form step by dielectric substance being imbedded in first groove to form dielectric dielectric;

Form the diaphragm pattern and subsequently electric conducting material is imbedded the conductor formation step that forms conductor in the diaphragm pattern by forming the dielectric place on the lower plane on described sacrificial substrate; With

Remove the end step of described sacrificial substrate.

59. according to the method for the single sacrificial substrate manufacturing of the utilization of claim 58 probe, wherein said sacrificial substrate is a silicon wafer.

60., wherein utilize dry etching process to form first groove according to the method for the single sacrificial substrate manufacturing of the utilization of claim 58 probe.

61., wherein utilize slice process to form first groove according to the method for the single sacrificial substrate manufacturing of the utilization of claim 58 probe.

62. make the method for probe according to the single sacrificial substrate of the utilization of claim 58, wherein said dielectric formation is by being applied to epoxy resin in first groove and before epoxy resin cure ceramic wafer being inserted subsequently and attached to carrying out in first groove, wherein said ceramic wafer is prefabricated into the size that is fit to be inserted in first groove.

63. make the method for probe according to the single sacrificial substrate of the utilization of claim 58, wherein said dielectric formation is by ceramic wafer being inserted in first groove and subsequently epoxy resin being applied and attached to carrying out in the gap that forms between described first groove and the described ceramic wafer, wherein said ceramic wafer being prefabricated into the size that is fit to be inserted in first groove.

64. the method according to the single sacrificial substrate manufacturing of the utilization of claim 58 probe wherein forms in the step at conductor, forms conductor by forming Seed Layer and carry out electroplating technology subsequently above sacrificial substrate.

65. make the method for probe according to the single sacrificial substrate of the utilization of claim 58, wherein said method also is included in the supporting component formation step that forms supporting component on the plane of last lower plane of sacrificial substrate.

66. the method according to the single sacrificial substrate manufacturing of the utilization of claim 65 probe wherein forms in the step at supporting component, applies epoxy resin, and subsequently with on the last plane of ceramic wafer attached to described epoxy resin.

67. the method according to the single sacrificial substrate manufacturing of the utilization of claim 65 probe wherein forms in the step at supporting component, utilizes photoetching process to form groove, and subsequently backing material is applied in the described groove, thereby form supporting component.

68. according to the method for the single sacrificial substrate manufacturing of the utilization of claim 58 probe, wherein said method comprises that also the conductive layer by utilizing plating technic stacked conductive material on plane on the conductor to form conductive layer forms step.

69. a method of utilizing single sacrificial substrate to make probe comprises:

The groove that forms the groove with desired depth on the presumptive area on plane on single sacrificial substrate forms step;

On sacrificial substrate, form the groove place and form the first diaphragm pattern, thereby the first diaphragm pattern of opening described groove forms step;

Groove is imbedded the groove that material imbeds in the groove of being opened by the first diaphragm pattern imbed step, wherein remove described groove and imbed material by etch process;

The second diaphragm pattern that utilizes photoetching process to form second diaphragm on lower plane on the sacrificial substrate forms step, and wherein the second diaphragm pattern is used to form conductor;

The conductor that forms conductor in the specific location that is limited by the second diaphragm pattern forms step;

Form the 3rd diaphragm pattern formation step that the conductor place forms the 3rd diaphragm pattern on lower plane on the sacrificial substrate, wherein the 3rd diaphragm pattern is used to form supporting component;

The supporting component that forms supporting component in the specific location that is limited by the 3rd diaphragm pattern forms step; With

Remove by groove and imbed the partial sacrifice substrate that material separates and remove the end step that groove is imbedded material subsequently.

70. make the method for probe according to the single sacrificial substrate of the utilization of claim 69; before forming conductor, described method also comprises the planarisation step of utilizing grinding technics to remove to be formed on the diaphragm pattern on the plane on the sacrificial substrate and imbedding material from the groove that sacrificial substrate projects upwards.

71. make the method for probe according to the single sacrificial substrate of the utilization of claim 69; wherein form in the step at the second diaphragm pattern; before forming conductor on the sacrificial substrate lower plane, described method also comprises utilizes grinding technics to remove sacrificial substrate to expose dielectric planarisation step.

72. according to the method for the single sacrificial substrate manufacturing of the utilization of claim 69 probe, wherein said sacrificial substrate is made by ceramic material.

73. according to the method for the single sacrificial substrate manufacturing of the utilization of claim 69 probe, wherein said groove forms by slice process.

74. according to the method for the single sacrificial substrate manufacturing of the utilization of claim 69 probe, wherein said groove is imbedded material and is formed by electroplating technology.

75. according to the method for the single sacrificial substrate manufacturing of the utilization of claim 69 probe, wherein conductor forms step and is included in the formation conductor forms Seed Layer before on lower plane on the sacrificial substrate Seed Layer formation step.

76. according to the method for the single sacrificial substrate manufacturing of the utilization of claim 69 probe, wherein said method comprises that also the conductive layer that utilizes electric conducting material stacked conductive layer on plane on each conductor forms step.

77. the method according to the single sacrificial substrate manufacturing of the utilization of claim 76 probe wherein forms in the step at conductive layer, by sputtering technology electric conducting material is stacked on the last plane of conductor.

78., wherein in end step, remove described groove by the wet etching process selectivity and imbed material according to the method for the single sacrificial substrate manufacturing of the utilization of claim 69 probe.

79. a probe that is used for flat panel display comprises:

Tabular dielectric;

A plurality of conductors; With

Be provided at first groove on described dielectric at least one plane of going up lower plane, be used for a plurality of conductors being fixed in the described dielectric with predetermined arrangement,

Wherein, two end portion on a described dielectric plane provide first and second outburst areas with predetermined area, and provide drop-center on a described plane,

Wherein, first groove on described first and second outburst areas is connected to described drop-center;

Wherein, the interval that is formed on first groove on described first outburst area is different from the interval that is formed on first groove on second outburst area.

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