CA1132265A - Direct memory access revolving priority apparatus - Google Patents
Direct memory access revolving priority apparatusInfo
- Publication number
- CA1132265A CA1132265A CA337,335A CA337335A CA1132265A CA 1132265 A CA1132265 A CA 1132265A CA 337335 A CA337335 A CA 337335A CA 1132265 A CA1132265 A CA 1132265A
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- CA
- Canada
- Prior art keywords
- dma
- peripheral
- signals
- cycles
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
- G06F13/30—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal with priority control
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
Abstract
ABSTRACT
In a terminal system comprising a central processor subsystem, a memory subsystem and a plurality of peripheral subsystems all connected in common to a system bus. The system bus timing is divided into a plurality of fixed times including a central processor (CPU) bus cycle and a plurality of direct Memory Access (DMA) bus cycles. The central processor subsystem communicates with the memory subsystem during CPU bus cycles and the peripheral subsystems communicate with the memory subsystem on DMA bus cycles.
Particular peripheral subsystems are assigned to particular DMA channels. These DMA channels communicate with the memory subsystem on particular DMA bus cycles which are operative in a revolving priority with the first DMA bus cycle occurring after the last DMA bus cycle of the previous sequence of DMA bus cycles.
A plurality of peripheral subsystems are wired to a particular DMA channel in a daisy chain fashion with the peripheral subsystem wired closes to the system bus having top priority. The peripheral subsystem having top priority may be wired either to relinquish the assigned DMA bus cycle after communicating with memory or "hog" the assigned DMA
bus cycle.
In a terminal system comprising a central processor subsystem, a memory subsystem and a plurality of peripheral subsystems all connected in common to a system bus. The system bus timing is divided into a plurality of fixed times including a central processor (CPU) bus cycle and a plurality of direct Memory Access (DMA) bus cycles. The central processor subsystem communicates with the memory subsystem during CPU bus cycles and the peripheral subsystems communicate with the memory subsystem on DMA bus cycles.
Particular peripheral subsystems are assigned to particular DMA channels. These DMA channels communicate with the memory subsystem on particular DMA bus cycles which are operative in a revolving priority with the first DMA bus cycle occurring after the last DMA bus cycle of the previous sequence of DMA bus cycles.
A plurality of peripheral subsystems are wired to a particular DMA channel in a daisy chain fashion with the peripheral subsystem wired closes to the system bus having top priority. The peripheral subsystem having top priority may be wired either to relinquish the assigned DMA bus cycle after communicating with memory or "hog" the assigned DMA
bus cycle.
Description
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Related Patent United States Patent No. 1~,263,6ll8, issued April 21, 19~1, entitled "Split System Bus Cycle for Direct Memory Access of Peripherals in a Cathode Ray Tube Display System", inventors - John P. Stafford~ Richard A. Slater, Gerald Winfrey, Frederick E. Kobs and Joseph L. Ryan.
Background of the Inv ntion Field of the Invention This invention relates generally to terminal systems and more partic-ularly to display systems with apparatus ~or generating a Direct Memory Access priority system.
Description of the Prior ~rt Terminal systems having a central processor (CPU), a memory subsystem and a number o~ peripherals. One method of controlling the system is by ha~ing the CPU, under program operation, con-trol the peripheral input/output communica-tion with memory through the CPU. This type of operation is satisfactory for low speed peripherals or ~or dedicated applications. This type o~ operation is not satisfactory ~or peripherals with high speed input/output requirements with mem-ory.
To solve this probIem the prior art designed systems whereby the high per~ormance peripherals communicated with memory without the intervention o~ the CPU. The CPU communicated with memory on CPU cycles and the peripherals communi-cating with memory during Direct Memory Access (DMA) cycles- with the peripherals stealing CPU cycles to communicate with memory. This system had the disadvantage o~ reducing system throughput in an application whereby the high performance peripheral prevented CPU cycles.
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To solve this problem, system~ with dedicated CPU
channels and DMA channels were designed. This had the problem that peripheral I/O throughput could be reduced by having high priority peripherals hogging the DMA cycles 5 thereby preventing low priority peripherals from accessing memory. This problem is somewhat alleviated by the invention of U.S. Patent 3,553~656 by D. E. Bernhardt, entitled "Selector for the Dynamic Assignment of a Priority on a Periodic Basis" wherein user devices are selectively 10 assigned highest priority depending upon the last device granted access. This however, still ha~ the problem of the device assigned highest priority hogging the memory bws.
These problems were eased somewhat by the system described in an article from Computer Design, January, 1978, 15 pages 117~124, by Joseph Nissam, entitled "DMA Controller Capitalizes on Clock Cycles to Bypass CPU". A systam is described having CPU cycles and DMA cycles. CPU cycles are stolen by the DMA devic~s~ however, the CPU can interrupt the DMA cy de. I !
Also, a DMA controller has eight DMA request/acknowledge lines to providelbidirectional control between the peripherals and the DMA controller. Each DMA line has a fixed priority.
Each channel has a rQgister to store the data length of the peripheral accessing the channel. The device relinquishes 25 the channel when (a) the register has counted down to zero, (b) a request from a peripheral on a higher priority channel is received by ~he DMA controller, or (c) the CPU requests a CPU cycle.
This solution requires considerable DMA logic and "housekeeping", and retains some of the raduced throughput problems of the CPU cycle stealing systams discussed abov~
and still has the problem of high priority peripherals hogging the bus.
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3L~32'~
OBJECTS OF TH~ INVENTION
Accordingly, it is an ob~ect of this invention to provide a terminal system with improved throughput.
It is another object of this in~ention to provide apparatus for a Direct Memory Access re~olving priority system.
It is still another object of this invention to provide apparatus for a priority system for peripheral subsystems operative during one Direct Memory Access bus cycle.
It is still another object of this invention to provide apparatus for a priority system where~y a pre-determined peripheral subsystem may "hog" a particular Direct Memory Access bus cycle.
It is still another object o~ this invention to provide apparatus for a priority sy~tem whereby the peripheral subsystem connacted closest to the system bus has top priority.
SU~ARY OF THE INVENTION
-These objects are accomplished in a preferred embodiment of the invention. A central processor subsystem, a mem~ry gubsystem and a plurality of peripheral subsystems are all connected in common to a system bus. The memory is available to the central proce sor subsystem and to the peripheral subsystems on alternate bus cycles~ The central processor subsystem is operative with memory during Central Processor Unit (CPU) sy~tem bus cycles and the peripheral subsystems are operative with me ry during Direct Memory Access (DMA) system bus cycles. The 39 successive DMA bus cycles, DMAl, DMA2, DMA3, ... DMAn, DMAl, DMA2 ... are as igned specific peripheral su~ystems.
The preferred embodiment has 4 DMA bus cycles. The cathode ray tube display i5 wired to be operative during the DMAl bus cycle. The remainder of the peripheral subsystems are selectively wired to be operative on bus cycles DMA2, DMA3 or DMA4.
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' _4_ A plurality of peripheral subsystems assigned to a particular DMA bus cycle, for example DMA2 have their priority logic wired in a daisy chain fashion.
A ~erminal system with the revolving DMA channel can be configured to give a balanced peripheral subsyst~M, memory subsystem throughput. A device raquiring a large amount of data from the memory subsystem may have the exclusive use of a DMA channel. In the preferred embodi-ment, the cathode ray tube has the exclusiv~ use of the DMAl bus cycle.
Some examples of other configurations are as follows.
Two peripheral subsyste~s may be wired in a daisy chain fashion to the DMA2 channel and have, if required, alternate access to the DMA2 bus cycle.
A plurality of peripheral subsystems may be wired in a daisy chain fashion to the DMA3 channel with the peripheral subsystem closest to the system bus having top priority and the peripheral subsystem at the other end of the daisy chain having lowest priority in access to ~0 the DM~3 bus cycle.
As a final axample, a high performance peripheral subsystem may be connected in daisy chain fashion to the DMA4 sy~tem bus with a plurality of very low performance peripheral subsystems. The high performance peripheral may be wired to hog the DMA4 bus cycle since it may operate in a burst mode. ~he activity would not be so great as to prevent the lower performance peripheral subsystem's access to the DMA4 bus cycle.
The system bus includes an address bus, a data bus and a control bus. ~he control bus includes ~ignal lines associated with each DMA cycle. Each peripheral subsystem is operative during a selected DMA cycle by being connected to a particular control bus signal lines identifying that DMA cycle. Logic, in one mode of operation in each peri~
pheral ~ubsystem requests the DMA cycle if (a) another peripheral w:ired to this DMA channel has not requested this D~A cycle, (h) there is not a DMA bu~ acknowladge signal, ~3;~265 and (c) the previous reques-t by this peripheral is completed. This assures that another peripheral subsystem wired to this DMA channel and requesting the D~
channel will be operative the next cycle in which this DMA channel is active.
In a second mode of operation, logic on some peripheral subsystems associated with a particular DMA channel are wired in such a manner that a partic-ular peripheral subsys-tem wired in that manner reques-ting the DMA channel and being operative with that DMA channel may remain connected to that DMA channel on successive DMA cycles of that particular channel even though other peripheral subsystems connected to that DMA cnannel desire access to the channel. In this case, the logic is wired in such a manner that a request for access by the partic-ular peripheral subsystem on the DMA cycles is accepted each time -the request is made by that peripheral subsystem. This allows a peripheral subsys-tem to "hog"
that DMA channel for as long as required. A peripheral subsystem operating in a burst mode may have this hogging requirement.
In accordance with the present invention, there is provided a terminal system with revolving priority direct memory access (DMA) apparatus, said system comprising: a system bus being operatively timed to provide control signals for defining central processor (CPU) cycles and a plurality of DMA cycles; a memory subsystem operatively connected to said system bus during said CPU cycles and said plurality of DMA cycles; a plurality of peripheral subsystems coupled to said system bus and connected to said memory during said plurality of DMA cycles for transferring data between one of said plurality of peripheral subsystems and said memory, said plurality of DMA cycles being operative in a predetermined re-volving priority &equence, and each of sai.d plurality of peripheral subsystems reques.ting access to s:aid memor~ being connected with said memory on a preassign-ed DMA cycle; wherein said peripheral subsystem, heing operatively connected to said memory on s.aid preassigned DMA cycle is responsive to a memory request sig-nal from`said peripheral suhsystem to dis.connect from said memory for a next one .~
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22~5 of said preassigned Dr~A cycle when another of said peripheral subsystems connect-ed with said memory on said preassigned Dr~A cycle requests access to said memory for the next one of said preassignea Dr~A cycles.
In accordance with the present invention, there is further provided a terminal system with revolving priority direct memory access (,Dr~A) apparatus, said system comprising: a system bus being operatively timed to provide control signals for defining central. processor (CPU) cycles and a plurality of' Dr~A
cycles; a memory subsystem operatively connected to said system bus during said CPU cycles and said plurality of DMA cycles; a plurality of peripheral subsystems coupled to said system bus and connected to said memory during said plurality of Dr~A cycles for transferring data between one of said plurality of peripheral sub-systems and said memory, said plurality of Dr~A cycles being operative in a pre-determined revolving priority sequence, and each of said plurality of peripheral subsystems requesting access to s,aid memory b.eing operatively connected with said memory on a preassigned Dr~A cycle; w.herein said peripheral sub.system being opera-tively coupled to said memory on said preassigned Dr~A cycle is responsive to a device request signal to remain operatively coupled to said memory on suhsequent preassigned Dr~A cycles.
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~3~2~5 .~
BRIEF DESCRIPTION OF THE DRAWINGS
. .
Figure 1 shows the system bus timing cycles.
Figure 2 is a block diagram of the system.
Figure 3 is a detailed logic diagram of the revolving 5 priority apparatus.
Figure 4 is a timing diagram of the Direct Memory Access priority logic interacting with system bus signals.
~ ~' : , :
- , .
:
: ,, DESCRIPTION OF THE PRE~ERRED EMBODIMENT
Figure 1 shows the system bus timing cyle with the data bu~ 16 offs~t from the address bus by 305 nanoseconds.
This split bus timing is disc:losed in the incorporated application.
The DMA1 time slot is reserved for the cathode ray tube display. Peripheral subsystems are assigned to the DMA2, DMA3 and DMA4 time slots. The system bus is avail-able to the microprocessor on CPU cycles.
..
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Figure 2 is a block diagram of a portion of the overall terminal sy~tem comprising a microprocesqor #ubsy~tem 4, ~ memory subsy~em 10, a CRT ~ubsy~tem 12 includlng a CRT controller 12-2 and a DMA link and synchronizer 12-4, timing and control logic 2, a DMA priority networ~ 6, option controllers 14a, 14b, ... and option data lin~ ~nd synchronizer 22a, 22b, ... . The data bus 16, the addre~s bus 18 and a control bus 20 are operatively connected to the above subsystems as shown in Figure 2.
The timing and control logic 2 generates the CPUAV~-and CPUDAT- bus timing signals which define the DMA and CPU cycle timings of address bus 18 and d~ta bus 16 respectively.
The DMA priority network 6 generates the sequential DMAK10, DM~K20, DMAK30 and DM~K40 timing signals. Timing ~ignal DMAK10 defines the DMAl address bus 18 and data bus 16 cycle time. Similarly timing signal DMAK20 defines DMAl cycle time, and timing signal DMAK40 defines DMA4 cycle time.
An option i8 jumpered serially into one of the timing signal lines to be operative during that DMA cycle. ~n Figure 2, option "N" is jumpered serially into timing signal DMAK20 and is operative during the DMA2 address bus 18 and data bus 16 cycle timeO Other options (not shown) that would ~e operative during DMA2 cycle time would be jumpered serially into the continuation of signal line DMAK20, signal lines DMAK21, DMAK22, etc.
Other options would be jumpered serially into the timing signal chain DMAK30, DMAK31, DMAK32, etc., to be operative at DMA3 time or jumpered serially lnto the ~iming ~ignal chain DMAK40, DMAK41, DMAK42, etc., to be operative at DMA4 time.
CRT subsystem 12 is jumpered to timing signal line DMAK10 and is operative at DMAl time. Since the CRT sub-system requires continuous rewriting the DMAl time slotis assigned exclusively to the CRT.
Related Patent United States Patent No. 1~,263,6ll8, issued April 21, 19~1, entitled "Split System Bus Cycle for Direct Memory Access of Peripherals in a Cathode Ray Tube Display System", inventors - John P. Stafford~ Richard A. Slater, Gerald Winfrey, Frederick E. Kobs and Joseph L. Ryan.
Background of the Inv ntion Field of the Invention This invention relates generally to terminal systems and more partic-ularly to display systems with apparatus ~or generating a Direct Memory Access priority system.
Description of the Prior ~rt Terminal systems having a central processor (CPU), a memory subsystem and a number o~ peripherals. One method of controlling the system is by ha~ing the CPU, under program operation, con-trol the peripheral input/output communica-tion with memory through the CPU. This type of operation is satisfactory for low speed peripherals or ~or dedicated applications. This type o~ operation is not satisfactory ~or peripherals with high speed input/output requirements with mem-ory.
To solve this probIem the prior art designed systems whereby the high per~ormance peripherals communicated with memory without the intervention o~ the CPU. The CPU communicated with memory on CPU cycles and the peripherals communi-cating with memory during Direct Memory Access (DMA) cycles- with the peripherals stealing CPU cycles to communicate with memory. This system had the disadvantage o~ reducing system throughput in an application whereby the high performance peripheral prevented CPU cycles.
-1- ~
:. ~ . - . . , ~L3Z~
To solve this problem, system~ with dedicated CPU
channels and DMA channels were designed. This had the problem that peripheral I/O throughput could be reduced by having high priority peripherals hogging the DMA cycles 5 thereby preventing low priority peripherals from accessing memory. This problem is somewhat alleviated by the invention of U.S. Patent 3,553~656 by D. E. Bernhardt, entitled "Selector for the Dynamic Assignment of a Priority on a Periodic Basis" wherein user devices are selectively 10 assigned highest priority depending upon the last device granted access. This however, still ha~ the problem of the device assigned highest priority hogging the memory bws.
These problems were eased somewhat by the system described in an article from Computer Design, January, 1978, 15 pages 117~124, by Joseph Nissam, entitled "DMA Controller Capitalizes on Clock Cycles to Bypass CPU". A systam is described having CPU cycles and DMA cycles. CPU cycles are stolen by the DMA devic~s~ however, the CPU can interrupt the DMA cy de. I !
Also, a DMA controller has eight DMA request/acknowledge lines to providelbidirectional control between the peripherals and the DMA controller. Each DMA line has a fixed priority.
Each channel has a rQgister to store the data length of the peripheral accessing the channel. The device relinquishes 25 the channel when (a) the register has counted down to zero, (b) a request from a peripheral on a higher priority channel is received by ~he DMA controller, or (c) the CPU requests a CPU cycle.
This solution requires considerable DMA logic and "housekeeping", and retains some of the raduced throughput problems of the CPU cycle stealing systams discussed abov~
and still has the problem of high priority peripherals hogging the bus.
: . :
3L~32'~
OBJECTS OF TH~ INVENTION
Accordingly, it is an ob~ect of this invention to provide a terminal system with improved throughput.
It is another object of this in~ention to provide apparatus for a Direct Memory Access re~olving priority system.
It is still another object of this invention to provide apparatus for a priority system for peripheral subsystems operative during one Direct Memory Access bus cycle.
It is still another object of this invention to provide apparatus for a priority system where~y a pre-determined peripheral subsystem may "hog" a particular Direct Memory Access bus cycle.
It is still another object o~ this invention to provide apparatus for a priority sy~tem whereby the peripheral subsystem connacted closest to the system bus has top priority.
SU~ARY OF THE INVENTION
-These objects are accomplished in a preferred embodiment of the invention. A central processor subsystem, a mem~ry gubsystem and a plurality of peripheral subsystems are all connected in common to a system bus. The memory is available to the central proce sor subsystem and to the peripheral subsystems on alternate bus cycles~ The central processor subsystem is operative with memory during Central Processor Unit (CPU) sy~tem bus cycles and the peripheral subsystems are operative with me ry during Direct Memory Access (DMA) system bus cycles. The 39 successive DMA bus cycles, DMAl, DMA2, DMA3, ... DMAn, DMAl, DMA2 ... are as igned specific peripheral su~ystems.
The preferred embodiment has 4 DMA bus cycles. The cathode ray tube display i5 wired to be operative during the DMAl bus cycle. The remainder of the peripheral subsystems are selectively wired to be operative on bus cycles DMA2, DMA3 or DMA4.
. ~:
' _4_ A plurality of peripheral subsystems assigned to a particular DMA bus cycle, for example DMA2 have their priority logic wired in a daisy chain fashion.
A ~erminal system with the revolving DMA channel can be configured to give a balanced peripheral subsyst~M, memory subsystem throughput. A device raquiring a large amount of data from the memory subsystem may have the exclusive use of a DMA channel. In the preferred embodi-ment, the cathode ray tube has the exclusiv~ use of the DMAl bus cycle.
Some examples of other configurations are as follows.
Two peripheral subsyste~s may be wired in a daisy chain fashion to the DMA2 channel and have, if required, alternate access to the DMA2 bus cycle.
A plurality of peripheral subsystems may be wired in a daisy chain fashion to the DMA3 channel with the peripheral subsystem closest to the system bus having top priority and the peripheral subsystem at the other end of the daisy chain having lowest priority in access to ~0 the DM~3 bus cycle.
As a final axample, a high performance peripheral subsystem may be connected in daisy chain fashion to the DMA4 sy~tem bus with a plurality of very low performance peripheral subsystems. The high performance peripheral may be wired to hog the DMA4 bus cycle since it may operate in a burst mode. ~he activity would not be so great as to prevent the lower performance peripheral subsystem's access to the DMA4 bus cycle.
The system bus includes an address bus, a data bus and a control bus. ~he control bus includes ~ignal lines associated with each DMA cycle. Each peripheral subsystem is operative during a selected DMA cycle by being connected to a particular control bus signal lines identifying that DMA cycle. Logic, in one mode of operation in each peri~
pheral ~ubsystem requests the DMA cycle if (a) another peripheral w:ired to this DMA channel has not requested this D~A cycle, (h) there is not a DMA bu~ acknowladge signal, ~3;~265 and (c) the previous reques-t by this peripheral is completed. This assures that another peripheral subsystem wired to this DMA channel and requesting the D~
channel will be operative the next cycle in which this DMA channel is active.
In a second mode of operation, logic on some peripheral subsystems associated with a particular DMA channel are wired in such a manner that a partic-ular peripheral subsys-tem wired in that manner reques-ting the DMA channel and being operative with that DMA channel may remain connected to that DMA channel on successive DMA cycles of that particular channel even though other peripheral subsystems connected to that DMA cnannel desire access to the channel. In this case, the logic is wired in such a manner that a request for access by the partic-ular peripheral subsystem on the DMA cycles is accepted each time -the request is made by that peripheral subsystem. This allows a peripheral subsys-tem to "hog"
that DMA channel for as long as required. A peripheral subsystem operating in a burst mode may have this hogging requirement.
In accordance with the present invention, there is provided a terminal system with revolving priority direct memory access (DMA) apparatus, said system comprising: a system bus being operatively timed to provide control signals for defining central processor (CPU) cycles and a plurality of DMA cycles; a memory subsystem operatively connected to said system bus during said CPU cycles and said plurality of DMA cycles; a plurality of peripheral subsystems coupled to said system bus and connected to said memory during said plurality of DMA cycles for transferring data between one of said plurality of peripheral subsystems and said memory, said plurality of DMA cycles being operative in a predetermined re-volving priority &equence, and each of sai.d plurality of peripheral subsystems reques.ting access to s:aid memor~ being connected with said memory on a preassign-ed DMA cycle; wherein said peripheral subsystem, heing operatively connected to said memory on s.aid preassigned DMA cycle is responsive to a memory request sig-nal from`said peripheral suhsystem to dis.connect from said memory for a next one .~
,:. - : . . , ~
:: ' . ' :::
::': : ~: : ::.
:: : : .
22~5 of said preassigned Dr~A cycle when another of said peripheral subsystems connect-ed with said memory on said preassigned Dr~A cycle requests access to said memory for the next one of said preassignea Dr~A cycles.
In accordance with the present invention, there is further provided a terminal system with revolving priority direct memory access (,Dr~A) apparatus, said system comprising: a system bus being operatively timed to provide control signals for defining central. processor (CPU) cycles and a plurality of' Dr~A
cycles; a memory subsystem operatively connected to said system bus during said CPU cycles and said plurality of DMA cycles; a plurality of peripheral subsystems coupled to said system bus and connected to said memory during said plurality of Dr~A cycles for transferring data between one of said plurality of peripheral sub-systems and said memory, said plurality of Dr~A cycles being operative in a pre-determined revolving priority sequence, and each of said plurality of peripheral subsystems requesting access to s,aid memory b.eing operatively connected with said memory on a preassigned Dr~A cycle; w.herein said peripheral sub.system being opera-tively coupled to said memory on said preassigned Dr~A cycle is responsive to a device request signal to remain operatively coupled to said memory on suhsequent preassigned Dr~A cycles.
- 5a -.
~3~2~5 .~
BRIEF DESCRIPTION OF THE DRAWINGS
. .
Figure 1 shows the system bus timing cycles.
Figure 2 is a block diagram of the system.
Figure 3 is a detailed logic diagram of the revolving 5 priority apparatus.
Figure 4 is a timing diagram of the Direct Memory Access priority logic interacting with system bus signals.
~ ~' : , :
- , .
:
: ,, DESCRIPTION OF THE PRE~ERRED EMBODIMENT
Figure 1 shows the system bus timing cyle with the data bu~ 16 offs~t from the address bus by 305 nanoseconds.
This split bus timing is disc:losed in the incorporated application.
The DMA1 time slot is reserved for the cathode ray tube display. Peripheral subsystems are assigned to the DMA2, DMA3 and DMA4 time slots. The system bus is avail-able to the microprocessor on CPU cycles.
..
~ ' ' . . ` ' -: ~:
:~L3;2~
Figure 2 is a block diagram of a portion of the overall terminal sy~tem comprising a microprocesqor #ubsy~tem 4, ~ memory subsy~em 10, a CRT ~ubsy~tem 12 includlng a CRT controller 12-2 and a DMA link and synchronizer 12-4, timing and control logic 2, a DMA priority networ~ 6, option controllers 14a, 14b, ... and option data lin~ ~nd synchronizer 22a, 22b, ... . The data bus 16, the addre~s bus 18 and a control bus 20 are operatively connected to the above subsystems as shown in Figure 2.
The timing and control logic 2 generates the CPUAV~-and CPUDAT- bus timing signals which define the DMA and CPU cycle timings of address bus 18 and d~ta bus 16 respectively.
The DMA priority network 6 generates the sequential DMAK10, DM~K20, DMAK30 and DM~K40 timing signals. Timing ~ignal DMAK10 defines the DMAl address bus 18 and data bus 16 cycle time. Similarly timing signal DMAK20 defines DMAl cycle time, and timing signal DMAK40 defines DMA4 cycle time.
An option i8 jumpered serially into one of the timing signal lines to be operative during that DMA cycle. ~n Figure 2, option "N" is jumpered serially into timing signal DMAK20 and is operative during the DMA2 address bus 18 and data bus 16 cycle timeO Other options (not shown) that would ~e operative during DMA2 cycle time would be jumpered serially into the continuation of signal line DMAK20, signal lines DMAK21, DMAK22, etc.
Other options would be jumpered serially into the timing signal chain DMAK30, DMAK31, DMAK32, etc., to be operative at DMA3 time or jumpered serially lnto the ~iming ~ignal chain DMAK40, DMAK41, DMAK42, etc., to be operative at DMA4 time.
CRT subsystem 12 is jumpered to timing signal line DMAK10 and is operative at DMAl time. Since the CRT sub-system requires continuous rewriting the DMAl time slotis assigned exclusively to the CRT.
2~
g The options 22a, 22b, assigned to be operative during DMA2~ DMA3 or DMA4 time are ~umpered to signal lines DMAREQ-l, DMAREQ-2 or DMAREQ~3 resp~ctively. One of these lines low indicates that one of the optlons ln that daisy chain is requesting acces~ to its DMA cycle and prevents the other options in that daisy chain from gaining access to that DMA cycle. Figure 2 ~hows option "N" 22a jumpered to signal line DMAREQ-2 and option "N~l" 22b jumpered to signal line DMAREQ-3.
Logic signal DMAREQ-~00, an output of CRT controller 12-2, when high, requests access to the DMAl cycle by inputting DMA link and synchronizer 12-4O Logic signal BUSAKl-02 outputs DMA link 12-~ and acknowledges access to the DMA0 cycle when high by inputting CRT controller 12-2.
Each option or device operatively connectad to the bus durings its DMA cycle either transfers data to or receives data from the memory subsystem over data bus 16 at an addres~ specified by the option or device and sent to memory 10 over addres~ bus 18. Microprocessor subsystem 4 i5 operative with memory 10 during CPU bus cycles.
CPUPHl and CPUPH2 timing signals generated by timing and control logic 2,time the microprocessor ~ubsystem 4 to the address bus 18 and data bus 16.
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Figure 3 shows the DMA priority network 6 comprising a free running counter 6~2 and a decoder 6-4 and the DMA
linking network 22a.
Counter 6-2 increments hy ONE each time the SRBIT3-timing ~ignal goes high. As is obvious to one of ordinary skill in the art, the output signals PRlCOD+Ol and PRlCOD~02 indicate a binary count of 00, 01, lO and ll on successive positive pulses to the counter 6 2 by timing ~ignal SRBIT3-, Signals PRlCOD+Ol and PRlCOD+02 are applied to terminals 1 and 2 of a decoder 6-4 which force output signa~s DMAKlO-, DMAK20-~ DMAK30- and DMAK40- on succeqsive S~BIT3- signals.
The REFRSH~ output signal of counter 6-2 is forced high every 16th rise of the SRB~T3- ~ignal. The REFRSH signal i8 applied to the ENABLE terminal of decoder 6-4 which re~ults in every 4th DMAK10- signal remaining high during the DMAl time slot. This DMAl time ~lot is used to refresh memory lO. The memory refresh operation i5 not pertinent to the understanding of the invention and is therefore not discussed further.
The option "N" controller requests access to memory 10 by ~orcing signal MYDMAS, an input to a NAND gate 22-2 high. Option "N" is arbitrarily wired in serie~ with signal DMAK20-10 which is inverted by inverter 22-24 and ayain by inverter 22-4 and inputs NAND 22-2 as signal DMAK20-20.
Signal DMAK20-20 when low deine~ DMA2 cycle time. Signal DMAREQ-02 i~ jumpered to the DMAREQ-02 signal llne and i~
high when no other option connected in series with signal line DMAK20-lO has requested access to memory lO. The DMAREQ-02 signal inputs NAND 22-2. The MYDMAG- signal input to NAND 22-2 is high. When the 4 inputs to NAND 22-2 are high, its output, which inputs the K terminal of a flop 22-6 signal MYDMAG+ is low. Timing and control logic 2 generates a DEVSTR- strobe signal which is inverted by in-verter 22-Z2, me output signal DEVSTR+ i~ connected to the clock terminal of flop 22-6 which is set on the rise of signal DEVSTRt. Flop 22-6 can be set on any rise of device strobe DEVSTR~ when the DMAK20-10 signal is high and no - .
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2t~
other device on the dai~y chain reque~ted memory 10 acce~.
Flop 22-6 i~ a 74S109 JK flop dcscrib~d in The ~TL D~ta Book for Da~lgn Engineer~, 2~d ~ditlon, 1976, publl~hed by ~exas Instruments Inc. The f:Lop 22-6 output ~ignal MYDMA~
input~ an OR gate 22-8 and forces the signal DMAK21- high thereby preventing other options responsive to the DMA2 timing cycle from being operative during this DMA2 cycle.
Signal MYDMAF+ is inverted by an inverter 22-10 whose output DMAREQ-02 is connected to the DMAREQ-02 bus and to the input of NAND 22-2. This signal when low prevents the other options re ponsive to the DMA2 timing cycle from being operative by forcing the output of the NAND 22-2 high.
(Note that the circuitry described herein is repeated for each option. The DMAREQ-0~ is connected to the input of NA~D 22-2 for each option connected to signal lines DMAK21-and 3!)MAREQ~02a ) The options that are active during a particular DMAcycle are wired in "daisy chain" fashion. Initially, the option wired closest to the DMA priority network 6 has highest priority and the option wired farthest from the DMA priority network 6, that is, at the end of daisy chain has the lowest priority. The output of OR 22-8 remaining high prevents lower priority options from access to memory 10 during this DMA2 cycle and the output of inverter 22-10 high prevents higher priority options from access to memory 10 durin~ this DMA~ cycle.
The DMA20-20 ~ignal i~ inverted by inverter 22-24 whose output i~ connected to the input an AND gate 22-12 and an AND gate 22-14. Signal MYDMAF+ connects to another input Of AND 22-12. Address bus 18 timing signal CPUADR- is connected to the third input of AND 22-12. The CPUADR-~ignal, when high, gates the valid DMA address signals on address bus 18. When the 3 inputs to AND gate 22-12 are high the output signal MYDMAA goes high signalling the option "N" controller 14a to send the memory 10 address on address bus 18. Signal MYDMAF- connects to the input of ., .
Zt~S
a NAND gat~ 22-16 and when low forces the output of NOR 22-16 high. The output of NAND 22-16 connect~ to another input of AND 22-14. Data bus 16 timing signal CPUDAT- is generated in timing and control logic 2 and is inverted by an inverter 22-20. The output signal CPUDAT+ connects to another input of AND 22-14. When the 3 inputs to AND 22-14 are high the output signal MYDMAD goe~ high signalling the option "N"
controller to either send or receive data over data bus 16. Data bus 16 and address bus 18 operation and timing lU are described in the ~ee~@~E~t~ a~ 3~.
The signal MYDM~A+ also connect~ to the J inputs of a JK flop 22-18. When strobe signal DEVSTR~ which connects to the clock input goes high flop 22-18 sets forcing the output signal MYDMAG- low. Signal MYDMAG- connects to an input of NAND 22-16 and forces the output high to assure ~hat the MYDMAD signal output of AND 22-14 remains high until after signal CPUDAT~ goes low.
The MYDMAG~ output signal of flop 22-18 forces the J input of flop 22-6 high. The output of NAND 22-2 is also high since the DMAREQ-02 input to NAND 22-2 is low.
This forces the K input of flop 22-6 high resetting the flop on the next DEVSTR+ ~ignal. Resetting flop 22-6 allows the DMAREQ-02 reque~t line output of inverter 22-10 to go high. Since the MYDMAF flop 22-6 cannot set again until the MYDMAG flop 22-1~ resets, another option in the "daisy chain" can request the next DMA2 bus cycle. It may be a requirement that this option access memory 10 on successive DMA2 cycles. In that case the signal DMAREQ-02 input to NAND 22-2 is removed and flop 22-6 can set and access memory 10 during the next DMA2 bus cycle if requested by the option "N" controller 14a, signal MYDMAS.
Output signal MYDMAA goes low when flop 22-6 re~ets 6ince signal MYDMAF+, the input to AND 22-12 goes low.
mi8 reset~ flop 22-18 on the next rise of the ~trobe signal DEVSTR+ ~ince both the J and K input signals MYDMAA
and MYD~AF~ are both low.
, :
;, :~
: ,: .
.. :
, :: ;
. ~ : , Figure 4 shows a timing diagram of the DMA priority operation. The CPUPHl and CPUPH2 signal timings are to show the relationship of the microprocessor ~ubsystem 4 to the DMA cycles. CPUADR- defines the time DMA address signals are on the address bus 18. CPUDAT- defines the time DMA data signals are on the data bus 16. DEVSTR~
times the option devices to the memory 10 timing. Flops set on the rise of the signal.
T~e above timings are described in detail in the incorporated application. DMAK20-10 defines the DMA2 bus cycle. MYDMA~+ is set on any rise of DEVSTR+ when DMAK20-lO is high. MY~M~G+ is set on the rise o~ DEVSTR~
when MYDMAF+ is high.
MYDMAA is defined by CPUADR- and MYDMAD is defined by CPUDAT-. Note that MYDMAF+ may go high on any rise of DEVSTR+ with the exception of those marked A. The dotted portion of MYDMAF+ shows the signal going high on the rise of DEVSTR+ marked B.
While in accordance with the provisions and statutes there has been illu~trated and described the bQSt form of the invention known, certain changes may be made to the system described without departing from the spirit of ~he invention as set forth in the appended claim~ and in some cases, certain features of the inven ion may be used to advantage without a corresponding use of other features .
What is claim2d is : ~ ~ - ' ,' , . .
. :
g The options 22a, 22b, assigned to be operative during DMA2~ DMA3 or DMA4 time are ~umpered to signal lines DMAREQ-l, DMAREQ-2 or DMAREQ~3 resp~ctively. One of these lines low indicates that one of the optlons ln that daisy chain is requesting acces~ to its DMA cycle and prevents the other options in that daisy chain from gaining access to that DMA cycle. Figure 2 ~hows option "N" 22a jumpered to signal line DMAREQ-2 and option "N~l" 22b jumpered to signal line DMAREQ-3.
Logic signal DMAREQ-~00, an output of CRT controller 12-2, when high, requests access to the DMAl cycle by inputting DMA link and synchronizer 12-4O Logic signal BUSAKl-02 outputs DMA link 12-~ and acknowledges access to the DMA0 cycle when high by inputting CRT controller 12-2.
Each option or device operatively connectad to the bus durings its DMA cycle either transfers data to or receives data from the memory subsystem over data bus 16 at an addres~ specified by the option or device and sent to memory 10 over addres~ bus 18. Microprocessor subsystem 4 i5 operative with memory 10 during CPU bus cycles.
CPUPHl and CPUPH2 timing signals generated by timing and control logic 2,time the microprocessor ~ubsystem 4 to the address bus 18 and data bus 16.
: - , - - :
, .
~L~3f~ S
Figure 3 shows the DMA priority network 6 comprising a free running counter 6~2 and a decoder 6-4 and the DMA
linking network 22a.
Counter 6-2 increments hy ONE each time the SRBIT3-timing ~ignal goes high. As is obvious to one of ordinary skill in the art, the output signals PRlCOD+Ol and PRlCOD~02 indicate a binary count of 00, 01, lO and ll on successive positive pulses to the counter 6 2 by timing ~ignal SRBIT3-, Signals PRlCOD+Ol and PRlCOD+02 are applied to terminals 1 and 2 of a decoder 6-4 which force output signa~s DMAKlO-, DMAK20-~ DMAK30- and DMAK40- on succeqsive S~BIT3- signals.
The REFRSH~ output signal of counter 6-2 is forced high every 16th rise of the SRB~T3- ~ignal. The REFRSH signal i8 applied to the ENABLE terminal of decoder 6-4 which re~ults in every 4th DMAK10- signal remaining high during the DMAl time slot. This DMAl time ~lot is used to refresh memory lO. The memory refresh operation i5 not pertinent to the understanding of the invention and is therefore not discussed further.
The option "N" controller requests access to memory 10 by ~orcing signal MYDMAS, an input to a NAND gate 22-2 high. Option "N" is arbitrarily wired in serie~ with signal DMAK20-10 which is inverted by inverter 22-24 and ayain by inverter 22-4 and inputs NAND 22-2 as signal DMAK20-20.
Signal DMAK20-20 when low deine~ DMA2 cycle time. Signal DMAREQ-02 i~ jumpered to the DMAREQ-02 signal llne and i~
high when no other option connected in series with signal line DMAK20-lO has requested access to memory lO. The DMAREQ-02 signal inputs NAND 22-2. The MYDMAG- signal input to NAND 22-2 is high. When the 4 inputs to NAND 22-2 are high, its output, which inputs the K terminal of a flop 22-6 signal MYDMAG+ is low. Timing and control logic 2 generates a DEVSTR- strobe signal which is inverted by in-verter 22-Z2, me output signal DEVSTR+ i~ connected to the clock terminal of flop 22-6 which is set on the rise of signal DEVSTRt. Flop 22-6 can be set on any rise of device strobe DEVSTR~ when the DMAK20-10 signal is high and no - .
.. .: . . .
. ~
2t~
other device on the dai~y chain reque~ted memory 10 acce~.
Flop 22-6 i~ a 74S109 JK flop dcscrib~d in The ~TL D~ta Book for Da~lgn Engineer~, 2~d ~ditlon, 1976, publl~hed by ~exas Instruments Inc. The f:Lop 22-6 output ~ignal MYDMA~
input~ an OR gate 22-8 and forces the signal DMAK21- high thereby preventing other options responsive to the DMA2 timing cycle from being operative during this DMA2 cycle.
Signal MYDMAF+ is inverted by an inverter 22-10 whose output DMAREQ-02 is connected to the DMAREQ-02 bus and to the input of NAND 22-2. This signal when low prevents the other options re ponsive to the DMA2 timing cycle from being operative by forcing the output of the NAND 22-2 high.
(Note that the circuitry described herein is repeated for each option. The DMAREQ-0~ is connected to the input of NA~D 22-2 for each option connected to signal lines DMAK21-and 3!)MAREQ~02a ) The options that are active during a particular DMAcycle are wired in "daisy chain" fashion. Initially, the option wired closest to the DMA priority network 6 has highest priority and the option wired farthest from the DMA priority network 6, that is, at the end of daisy chain has the lowest priority. The output of OR 22-8 remaining high prevents lower priority options from access to memory 10 during this DMA2 cycle and the output of inverter 22-10 high prevents higher priority options from access to memory 10 durin~ this DMA~ cycle.
The DMA20-20 ~ignal i~ inverted by inverter 22-24 whose output i~ connected to the input an AND gate 22-12 and an AND gate 22-14. Signal MYDMAF+ connects to another input Of AND 22-12. Address bus 18 timing signal CPUADR- is connected to the third input of AND 22-12. The CPUADR-~ignal, when high, gates the valid DMA address signals on address bus 18. When the 3 inputs to AND gate 22-12 are high the output signal MYDMAA goes high signalling the option "N" controller 14a to send the memory 10 address on address bus 18. Signal MYDMAF- connects to the input of ., .
Zt~S
a NAND gat~ 22-16 and when low forces the output of NOR 22-16 high. The output of NAND 22-16 connect~ to another input of AND 22-14. Data bus 16 timing signal CPUDAT- is generated in timing and control logic 2 and is inverted by an inverter 22-20. The output signal CPUDAT+ connects to another input of AND 22-14. When the 3 inputs to AND 22-14 are high the output signal MYDMAD goe~ high signalling the option "N"
controller to either send or receive data over data bus 16. Data bus 16 and address bus 18 operation and timing lU are described in the ~ee~@~E~t~ a~ 3~.
The signal MYDM~A+ also connect~ to the J inputs of a JK flop 22-18. When strobe signal DEVSTR~ which connects to the clock input goes high flop 22-18 sets forcing the output signal MYDMAG- low. Signal MYDMAG- connects to an input of NAND 22-16 and forces the output high to assure ~hat the MYDMAD signal output of AND 22-14 remains high until after signal CPUDAT~ goes low.
The MYDMAG~ output signal of flop 22-18 forces the J input of flop 22-6 high. The output of NAND 22-2 is also high since the DMAREQ-02 input to NAND 22-2 is low.
This forces the K input of flop 22-6 high resetting the flop on the next DEVSTR+ ~ignal. Resetting flop 22-6 allows the DMAREQ-02 reque~t line output of inverter 22-10 to go high. Since the MYDMAF flop 22-6 cannot set again until the MYDMAG flop 22-1~ resets, another option in the "daisy chain" can request the next DMA2 bus cycle. It may be a requirement that this option access memory 10 on successive DMA2 cycles. In that case the signal DMAREQ-02 input to NAND 22-2 is removed and flop 22-6 can set and access memory 10 during the next DMA2 bus cycle if requested by the option "N" controller 14a, signal MYDMAS.
Output signal MYDMAA goes low when flop 22-6 re~ets 6ince signal MYDMAF+, the input to AND 22-12 goes low.
mi8 reset~ flop 22-18 on the next rise of the ~trobe signal DEVSTR+ ~ince both the J and K input signals MYDMAA
and MYD~AF~ are both low.
, :
;, :~
: ,: .
.. :
, :: ;
. ~ : , Figure 4 shows a timing diagram of the DMA priority operation. The CPUPHl and CPUPH2 signal timings are to show the relationship of the microprocessor ~ubsystem 4 to the DMA cycles. CPUADR- defines the time DMA address signals are on the address bus 18. CPUDAT- defines the time DMA data signals are on the data bus 16. DEVSTR~
times the option devices to the memory 10 timing. Flops set on the rise of the signal.
T~e above timings are described in detail in the incorporated application. DMAK20-10 defines the DMA2 bus cycle. MYDMA~+ is set on any rise of DEVSTR+ when DMAK20-lO is high. MY~M~G+ is set on the rise o~ DEVSTR~
when MYDMAF+ is high.
MYDMAA is defined by CPUADR- and MYDMAD is defined by CPUDAT-. Note that MYDMAF+ may go high on any rise of DEVSTR+ with the exception of those marked A. The dotted portion of MYDMAF+ shows the signal going high on the rise of DEVSTR+ marked B.
While in accordance with the provisions and statutes there has been illu~trated and described the bQSt form of the invention known, certain changes may be made to the system described without departing from the spirit of ~he invention as set forth in the appended claim~ and in some cases, certain features of the inven ion may be used to advantage without a corresponding use of other features .
What is claim2d is : ~ ~ - ' ,' , . .
. :
Claims (10)
1. A terminal system with revolving priority direct memory access (DMA) apparatus, said system comprising.
a system bus being operatively timed to provide control signals for defining central processor (CPU) cycles and a plurality of DMA cycles;
a memory subsystem operatively connected to said system bus during said CPU cycles and said plurality of DMA cycles;
a plurality of peripheral subsystems coupled to said system bus and connected to said memory during said plurality of DMA cycles for transferring data between one of said plurality of peripheral subsystems and said memory, said plurality of DMA cycles being operative in a predeter-mined revolving priority sequence, and each of said plurality of peripheral subsystems requesting access to said memory being connected with said memory on a preassigned DMA
cycle;
wherein said peripheral subsystem, being operatively connected to said memory on said preassigned DMA cycle is responsive to a memory request signal from said peripheral subsystem to disconnect from said memory for a next one of said preassigned DMA cycle when another of said peripheral subsystems connected with said memory on said preassigned DMA cycle requests access to said memory for the next one of said preassigned DMA cycles.
a system bus being operatively timed to provide control signals for defining central processor (CPU) cycles and a plurality of DMA cycles;
a memory subsystem operatively connected to said system bus during said CPU cycles and said plurality of DMA cycles;
a plurality of peripheral subsystems coupled to said system bus and connected to said memory during said plurality of DMA cycles for transferring data between one of said plurality of peripheral subsystems and said memory, said plurality of DMA cycles being operative in a predeter-mined revolving priority sequence, and each of said plurality of peripheral subsystems requesting access to said memory being connected with said memory on a preassigned DMA
cycle;
wherein said peripheral subsystem, being operatively connected to said memory on said preassigned DMA cycle is responsive to a memory request signal from said peripheral subsystem to disconnect from said memory for a next one of said preassigned DMA cycle when another of said peripheral subsystems connected with said memory on said preassigned DMA cycle requests access to said memory for the next one of said preassigned DMA cycles.
2. The system of claim 1 wherein said revolving priority DMA apparatus comprises:
timing means coupled to said system bus and generating said control signals including a plurality of DMA timing signals for defining said DMA cycles;
counter means coupled to said timing means and responsive to a clock signal from said timing means for generating revolving priority coding signals; and decoder means coupled to said system bus and to said counter means and responsive to said revolving priority coding signals for generating a plurality of DMA
signals defining said plurality of DMA cycles, said plurality of DMA signals being operative in said predetermined revolving priority sequence.
timing means coupled to said system bus and generating said control signals including a plurality of DMA timing signals for defining said DMA cycles;
counter means coupled to said timing means and responsive to a clock signal from said timing means for generating revolving priority coding signals; and decoder means coupled to said system bus and to said counter means and responsive to said revolving priority coding signals for generating a plurality of DMA
signals defining said plurality of DMA cycles, said plurality of DMA signals being operative in said predetermined revolving priority sequence.
3. The system of claim 2 wherein each of said peri-pheral subsystems comprises:
a peripheral controller coupled to said system bus for transferring information between said peripheral controller and said memory;
a data link synchronizer coupled to said system bus and to said peripheral controller, and being responsive to a device request signal from said peripheral controller to generate an address timing signal and a data timing signal, said timing signals being applied to said peripheral controller for connecting said peripheral controller to said memory during said preassigned DMA cycle.
a peripheral controller coupled to said system bus for transferring information between said peripheral controller and said memory;
a data link synchronizer coupled to said system bus and to said peripheral controller, and being responsive to a device request signal from said peripheral controller to generate an address timing signal and a data timing signal, said timing signals being applied to said peripheral controller for connecting said peripheral controller to said memory during said preassigned DMA cycle.
4. The system of claim 3 wherein said system bus signals coupled to said data link synchronizer includes:
said control signals for defining said plurality of DMA cycles;
a selected one of said plurality of DMA signals for defining said preassigned DMA cycle, said control signals and said DMA signal gating said timing signals;
a selected one of said plurality of peripheral subsystem request signals indicating that one of said peripheral subsystems operative during said preassigned DMA cycle requested access to said system bus.
said control signals for defining said plurality of DMA cycles;
a selected one of said plurality of DMA signals for defining said preassigned DMA cycle, said control signals and said DMA signal gating said timing signals;
a selected one of said plurality of peripheral subsystem request signals indicating that one of said peripheral subsystems operative during said preassigned DMA cycle requested access to said system bus.
5. The system of claim 4 wherein said data link synchronizer comprises:
peripheral subsystem request means responsive to said selected one of said plurality of peripheral request signals for indicating to said data link synchronizer that another of said peripheral subsystems operative during said preassigned DMA cycle will be operative with said memory during the next one of said preassigned DMA
cycle, said peripheral subsystem request means also generating said peripheral request signal when said peri-pheral subsystem requests access to said system bus to indicate to said data link synchronizer to disconnect said peripheral subsystem from said memory after said preassigned DMA cycle in which said peripheral subsystem was operatively connected to said memory, and also to indicate to others of said peripheral subsystems operative during said pre- -assigned DMA cycle that said peripheral subsystem will be operatively connected during said preassigned DMA cycles;
DMA request means coupled to said peripheral subsystem request means, said encoder means, said timing means, and to said peripheral controller for generating a system bus request signal indicating that said data link synchronizer has requested said system bus; and DMA acknowledge means coupled to said DMA request means and to said timing means, said DMA request means being responsive to a disconnect signal from said DMA
acknowledge means for disconnecting said peripheral sub-system from said system bus;
wherein said timing means is coupled to said DMA
request means and to said DMA acknowledge means being responsive to a device strobe signal from said timing means for synchronizing said DMA request means and said DMA
acknowledge means with said DMA cycle timing, said timing means being further coupled to said DMA request means, said DMA request means being responsive to said control signals from said timing means for defining said plurality of DMA cycles;
wherein said encoder means is coupled to said DMA request means, said DMA request means being responsive to said selected one of said DMA signals for defining said preassigned DMA cycle;
wherein said DMA request means is responsive to said device output signal, said selected one of said DMA
signals, said selected one of said plurality of peripheral request signals and said disconnect signal for generating said system bus request signal indicative of said peripheral subsystem requesting said system bus;
wherein said system bus request signal, said control signals for defining said plurality of DMA cycles, and said selected one of said DMA signals are gated for generating said address and data timing signals.
peripheral subsystem request means responsive to said selected one of said plurality of peripheral request signals for indicating to said data link synchronizer that another of said peripheral subsystems operative during said preassigned DMA cycle will be operative with said memory during the next one of said preassigned DMA
cycle, said peripheral subsystem request means also generating said peripheral request signal when said peri-pheral subsystem requests access to said system bus to indicate to said data link synchronizer to disconnect said peripheral subsystem from said memory after said preassigned DMA cycle in which said peripheral subsystem was operatively connected to said memory, and also to indicate to others of said peripheral subsystems operative during said pre- -assigned DMA cycle that said peripheral subsystem will be operatively connected during said preassigned DMA cycles;
DMA request means coupled to said peripheral subsystem request means, said encoder means, said timing means, and to said peripheral controller for generating a system bus request signal indicating that said data link synchronizer has requested said system bus; and DMA acknowledge means coupled to said DMA request means and to said timing means, said DMA request means being responsive to a disconnect signal from said DMA
acknowledge means for disconnecting said peripheral sub-system from said system bus;
wherein said timing means is coupled to said DMA
request means and to said DMA acknowledge means being responsive to a device strobe signal from said timing means for synchronizing said DMA request means and said DMA
acknowledge means with said DMA cycle timing, said timing means being further coupled to said DMA request means, said DMA request means being responsive to said control signals from said timing means for defining said plurality of DMA cycles;
wherein said encoder means is coupled to said DMA request means, said DMA request means being responsive to said selected one of said DMA signals for defining said preassigned DMA cycle;
wherein said DMA request means is responsive to said device output signal, said selected one of said DMA
signals, said selected one of said plurality of peripheral request signals and said disconnect signal for generating said system bus request signal indicative of said peripheral subsystem requesting said system bus;
wherein said system bus request signal, said control signals for defining said plurality of DMA cycles, and said selected one of said DMA signals are gated for generating said address and data timing signals.
6. A terminal system with revolving priority direct memory access (DMA) apparatus, said system comprising:
a system bus being operatively timed to provide control signals for defining central processor (CPU) cycles and a plurality of DMA cycles;
a memory subsystem operatively connected to said system bus during said CPU cycles and said plurality of DMA cycles;
a plurality of peripheral subsystems coupled to said system bus and connected to said memory during said plurality of DMA cycles for transferring data between one of said plurality of peripheral subsystems and said memory, said plurality of DMA cycles being operative in a pre-determined revolving priority sequence, and each of said plurality of peripheral subsystems requesting access to said memory being operatively connected with said memory on a preassigned DMA cycle;
wherein said peripheral subsystem being operatively coupled to said memory on said preassigned DMA cycle is responsive to a device request signal to remain operatively coupled to said memory on subsequent preassigned DMA cycles.
a system bus being operatively timed to provide control signals for defining central processor (CPU) cycles and a plurality of DMA cycles;
a memory subsystem operatively connected to said system bus during said CPU cycles and said plurality of DMA cycles;
a plurality of peripheral subsystems coupled to said system bus and connected to said memory during said plurality of DMA cycles for transferring data between one of said plurality of peripheral subsystems and said memory, said plurality of DMA cycles being operative in a pre-determined revolving priority sequence, and each of said plurality of peripheral subsystems requesting access to said memory being operatively connected with said memory on a preassigned DMA cycle;
wherein said peripheral subsystem being operatively coupled to said memory on said preassigned DMA cycle is responsive to a device request signal to remain operatively coupled to said memory on subsequent preassigned DMA cycles.
7. The system of claim 6 wherein said revolving priority DMA apparatus comprises:
timing means coupled to said system bus and generating said control signals including a plurality of DMA
timing signals for defining said DMA cycles;
counter means coupled to said timing means and responsive to a clock signal from said timing means for generating revolving priority coding signals; and decoder means coupled to said system bus and to said counter means and responsive to said revolving priority coding signals for generating a plurality of DMA signals defining said plurality of DMA cycles, said plurality of DMA signals being operative in said predetermined revolving priority sequence.
timing means coupled to said system bus and generating said control signals including a plurality of DMA
timing signals for defining said DMA cycles;
counter means coupled to said timing means and responsive to a clock signal from said timing means for generating revolving priority coding signals; and decoder means coupled to said system bus and to said counter means and responsive to said revolving priority coding signals for generating a plurality of DMA signals defining said plurality of DMA cycles, said plurality of DMA signals being operative in said predetermined revolving priority sequence.
8. The system of claim 7 wherein each of said peri-pheral subsystems comprises:
a peripheral controller coupled to said system bus for transferring information between said peripheral controller and said memory;
a data link synchronizer coupled to said system bus and to said peripheral controller, and being responsive to said device request signal from said peripheral controller to generate an address timing signal and a data timing signal, said timing signals being applied to said peripheral controller for disconnecting said peripheral controller to said memory during said preassigned DMA
cycle and during said subsequent preassigned DMA cycles.
a peripheral controller coupled to said system bus for transferring information between said peripheral controller and said memory;
a data link synchronizer coupled to said system bus and to said peripheral controller, and being responsive to said device request signal from said peripheral controller to generate an address timing signal and a data timing signal, said timing signals being applied to said peripheral controller for disconnecting said peripheral controller to said memory during said preassigned DMA
cycle and during said subsequent preassigned DMA cycles.
9. The system of claim 8 wherein said system bus signals coupled to said data link synchronizer includes:
said control signals for defining said plurality of DMA cycles;
a selected one of said plurality of DMA signals for defining said preassigned DMA cycle, said control signals and said DMA signal gating said timing signals.
said control signals for defining said plurality of DMA cycles;
a selected one of said plurality of DMA signals for defining said preassigned DMA cycle, said control signals and said DMA signal gating said timing signals.
10. The system of claim 8 wherein said data link synchronizer comprises:
peripheral subsystem request means generating said peripheral request signal. when said peripheral subsystem requests access to said system bus to indicate to others of said peripheral subsystems operative during said preassigned DMA cycle that said peripheral subsystem will be operatively connected during said preassigned DMA
cycles and subsequent preassigned DMA cycles;
DMA request means coupled to said peripheral subsystem request means, an encodor means, said timing means and to said peripheral controller for generating a system bus request signal indicating that said data link synchronizer has requested said system bus; and DMA acknowledge means coupled to said DMA request means and to said timing means, said DMA request means being responsive to a disconnect signal from said DMA
acknowledge means for disconnecting said peripheral sub-system from said system bus;
wherein said timing means is coupled to said DMA
request means and to said DMA acknowledge means, said DMA
request means and said DMA acknowledge means being responsive to a device strobe signal from said timing means for synchronizing said DMA request means and said DMA acknowledge means with said DMA cycle timing;
said timing means being further coupled to said DMA request means, said DMA request means being responsive to said control signals from said timing means for defining said plurality of DMA cycles;
wherein said encoder means is coupled to said DMA
request means, said DMA request means being responsive to said selected one of said DMA signals for defining said preassigned DMA cycle;
wherein said DMA request means is responsive to said device output signal, said selected one of said DMA
signals, said selected one of said plurality of peripheral request signals and said disconnect signal for generating said system bus request signal indicative of said peripheral subsystem requesting said system bus;
wherein said system bus request signal, said control signals for defining said plurality of DMA cycles, and said selected one of said DMA signals are gated for generating said address and data timing signals.
peripheral subsystem request means generating said peripheral request signal. when said peripheral subsystem requests access to said system bus to indicate to others of said peripheral subsystems operative during said preassigned DMA cycle that said peripheral subsystem will be operatively connected during said preassigned DMA
cycles and subsequent preassigned DMA cycles;
DMA request means coupled to said peripheral subsystem request means, an encodor means, said timing means and to said peripheral controller for generating a system bus request signal indicating that said data link synchronizer has requested said system bus; and DMA acknowledge means coupled to said DMA request means and to said timing means, said DMA request means being responsive to a disconnect signal from said DMA
acknowledge means for disconnecting said peripheral sub-system from said system bus;
wherein said timing means is coupled to said DMA
request means and to said DMA acknowledge means, said DMA
request means and said DMA acknowledge means being responsive to a device strobe signal from said timing means for synchronizing said DMA request means and said DMA acknowledge means with said DMA cycle timing;
said timing means being further coupled to said DMA request means, said DMA request means being responsive to said control signals from said timing means for defining said plurality of DMA cycles;
wherein said encoder means is coupled to said DMA
request means, said DMA request means being responsive to said selected one of said DMA signals for defining said preassigned DMA cycle;
wherein said DMA request means is responsive to said device output signal, said selected one of said DMA
signals, said selected one of said plurality of peripheral request signals and said disconnect signal for generating said system bus request signal indicative of said peripheral subsystem requesting said system bus;
wherein said system bus request signal, said control signals for defining said plurality of DMA cycles, and said selected one of said DMA signals are gated for generating said address and data timing signals.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US97319678A | 1978-12-26 | 1978-12-26 | |
| US973,196 | 1978-12-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1132265A true CA1132265A (en) | 1982-09-21 |
Family
ID=25520615
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA337,335A Expired CA1132265A (en) | 1978-12-26 | 1979-10-10 | Direct memory access revolving priority apparatus |
Country Status (7)
| Country | Link |
|---|---|
| JP (1) | JPS5588121A (en) |
| AU (1) | AU534761B2 (en) |
| CA (1) | CA1132265A (en) |
| DE (1) | DE2951055A1 (en) |
| FR (1) | FR2445556B1 (en) |
| GB (1) | GB2039105B (en) |
| YU (1) | YU40587B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2551236B1 (en) | 1983-08-30 | 1990-07-06 | Canon Kk | IMAGE PROCESSING SYSTEM |
| US5241661A (en) * | 1987-03-27 | 1993-08-31 | International Business Machines Corporation | DMA access arbitration device in which CPU can arbitrate on behalf of attachment having no arbiter |
| US4901234A (en) * | 1987-03-27 | 1990-02-13 | International Business Machines Corporation | Computer system having programmable DMA control |
| JP2550496B2 (en) * | 1989-03-30 | 1996-11-06 | 三菱電機株式会社 | DMA controller |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NL154023B (en) * | 1969-02-01 | 1977-07-15 | Philips Nv | PRIORITY CIRCUIT. |
| US3553656A (en) * | 1969-06-03 | 1971-01-05 | Gen Electric | Selector for the dynamic assignment of priority on a periodic basis |
| JPS5147298B2 (en) * | 1971-08-30 | 1976-12-14 | ||
| US3961312A (en) * | 1974-07-15 | 1976-06-01 | International Business Machines Corporation | Cycle interleaving during burst mode operation |
-
1979
- 1979-10-10 CA CA337,335A patent/CA1132265A/en not_active Expired
- 1979-11-20 AU AU53006/79A patent/AU534761B2/en not_active Ceased
- 1979-12-06 JP JP15752779A patent/JPS5588121A/en active Granted
- 1979-12-19 DE DE19792951055 patent/DE2951055A1/en active Granted
- 1979-12-19 GB GB7943695A patent/GB2039105B/en not_active Expired
- 1979-12-20 FR FR7931270A patent/FR2445556B1/en not_active Expired
- 1979-12-25 YU YU316779A patent/YU40587B/en unknown
Also Published As
| Publication number | Publication date |
|---|---|
| JPS636891B2 (en) | 1988-02-12 |
| GB2039105B (en) | 1983-02-16 |
| GB2039105A (en) | 1980-07-30 |
| JPS5588121A (en) | 1980-07-03 |
| YU316779A (en) | 1982-06-30 |
| FR2445556A1 (en) | 1980-07-25 |
| YU40587B (en) | 1986-02-28 |
| DE2951055C2 (en) | 1990-08-30 |
| FR2445556B1 (en) | 1988-03-18 |
| AU5300679A (en) | 1980-07-03 |
| DE2951055A1 (en) | 1980-07-17 |
| AU534761B2 (en) | 1984-02-16 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MKEX | Expiry |