CA1064621A - Modular transaction terminal with microprocessor control - Google Patents

Abstract

MODULAR TRANSACTION TERMINAL
WITH MICROPROCESSOR CONTROL

Abstract of the Disclosure A versatile readily serviced transaction terminal includes a credit card control mechanism, a user keyboard, a user display, a document handling system for cash and printed transaction statements, and a system for controlling terminal operation. The terminal receives a user credit card having a magnetic stripe with prerecorded account information, reads the account information, and then receives a user personal ID number through the keyboard. As an available option, the terminal may require a predetermined correspondence between the personal ID
number and the account information. After any required correspondence is satisfied, the user is permitted to operate the keyboard to indicate a selected one of an unlimited range of possible transaction requests. The control system, which includes a programmable microprocessor and a plurality of passive terminal elements interconnected by a terminal information bus, operates to assemble user supply information, terminal status information, communicate transaction requests to a host, and provide central information to terminal modules for the execution of requested transactions in a manner consistent with host generated transaction reply messages. Each terminal element handles one or more terminal functions such as the control of hardware or the control of user communications in direct response to microprocessor control information. All decision making is handled by the microprocessor with only specific, well defined commands being executed by the bus connected modules.

Description

~ i4623L
This application is a divisional of Canadian Application 225,805, filed April 23, 1975, and assigned to the same applicant.

1 Background o the Invention

2 1. Field of the Invention

3 This invention relates to transaction execution

4 terminals which may issue cash, transfer -funds, or execute -other requested transactions and more particularly to trans-6 action execution terminals having a microprocessor and modular 7 subsystems which are interconnected by an information bus. ~
8 2. History of the Prior Art ~-9 Transaction execution terminals are currently avail~
able for the performance of extremely limited, specific trans~
11 actions For instance, cash issue terminals are available 12 which will issue cash in return for the deposit of a check or `~
13 the debiting of a credit card account. Such terminals typically 14 require the insertion of a credit card containing account information written on a magnetic stripe and the keyboard entry ` ;
16 of a personal ID number which corresponds in a predetermined 17 manner to the credit card account information. The terminal 18 then receives a requested dollar amount through a numerlc key~
19 board and issues the desired amount of cash if the credit card ~ -20 and ID number are found to be in order. ~ ~ ;
21 Such terminals are able to perform only an extremely .
22 limited range of transaction functions and are not readily 23 adaptable to the execution of additional functions. The systems 24 for controlling terminal operation are relatively inflexible 25 in nature and are able to perform only the limited range of ~
26 available functions. ; ;~ -27 Summar~ of the Invention 28 A transaction execution terminal in accordance with 29 the invention includes a credit card control mechanism, a user 30 keyboard, a user display, a document handling system including -.-~ SA974017 -3 '.

~0646~:1 1 a cash issue mechanism and a transaction statement printing 2 mechanism, and a modular control system. The modular control ~ --3 system, which controls all mechanical, electrical, and electro-4 mechanical terminal functions, includes a terminal information bus, a programmable microprocessor connected to the bus, and a 6 plurality of passive terminal subsystems conn~cted to the bus.
7 The terminal subsystems contain the functional ~ .
8 actuators and sensors which are required to maintain terminal 9 operation, but merely serve as a conduit for microprocessor ;;
10 commands without acting to make decisions themselves. The `-~
11 terminal elements operate in response to specific, well defined 12 data signal commands to control the entry of information 13 into function control registers, to accumulate terminal 14 operating status irlformation and present this information on 15 the terminal information bus as terminal data on command. ` Y-~
16 The terminal actuators, whether they be motors, 17 solenoids, relays, displays, or other devices, respond directly 18 to stored terminal data information. For example, a DC motor 19 for driving a credit card transport mechanism~has the armature - , ~ .
20 drive input thereto connected through two switches. The first ` ~ `
21 is a single pole double throw switch which selectively connects 22 the motor to a positive supply voltage or a negative supply 23 voltage. The second is an on -off switch connected in series;`
24 with the first switch. The first and second switches are responsive to first and second bit positions in a storage 26 register, to selectively drive the motor in forward or reverse 27 directions or turn the motor off in accordance with information 28 written into the two bit positions by the microprocessor. ~
29 Photocells are positioned at various points along the credit ~ --~ .
30 card transport path to detect a position of the credit card. ~
~ .

1~6411;2~

l When a photocell lightpath is interrupted by a credit card, 2 a latch is set within ~he subsystem and an interrupt request 3 is generated. The microprocessor processes the interrupt 4 request by reading terminal status information accum~llated by the subsystem to detect the photocell signal. If the credit 6 card is to be stopped at this photocell, the logic 0 is then '~
7 written into the second bit position of the function control ' 8 register to terminate the motor operation, The terminal 9 element thus plays no active decision making rule but mPrely ,, serves a conduit to receive and e~ecute clearly defined specific 11 commands generated by the microprocessor. ,-12 This control system arrangement imparts to the , ,~, 13 transaction terminal and extremely precise but flexible control ,'~
14 over the execution of requested transactions. The number of transactions which may be requested and executed are expandable ~, 16 without limit by merely modifying the program for the micro~
17 processor and connecting any additional hardware that might 18 be required to the terminal information bus. In addition, 19 each terminal proprietor and owner may specify;,particular 20 options for the processing of user transactions by merely ~ , 21 inserting selected program options. ~o modification of the 22 terminal hardware is required. '' ' ., 23 Brief Description of the Drawings - ~,s ~ -24 A better understanding of the invention may be had 25 from a consideration of the following detailed"description ,`'';-26 taken in conjunction with the accompanying drawings in whic~
27 Fig. 1 is a perspective view of a transaction ' ~,' ' 28 terminal in accordance with the invention; ' ' 29 ~ Fig. 2 is a block diagram representation of a function ',','~
3~ control system for the terminal shown in Fig. l; ~'~

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1 Fig. 3 is a block diagram representation of a 2 processor support subsystem included within the control system 3 shown in Fig. 2;
4 Fig. 4 is a block diagram representation of a :-.
mechanical control subsystem included within the control 6 system shown in Fig. 2;
7 Fig. S is a side view representation of a document `-8 handling system included within the mechanical control sub-9 system shown in Fig. 4;
10 Fig. 6 is a rear view representation of a document -11 handling system shown in Fig. 5;
12 Fig. 7 is a block diagraml schematic representation ~ ;~
13 of information gathering logic used in the mechanical control ~ ;
14 subsystem shown in Fig. 4;
,.
15 Fig. 8 is a block diagram, schematic representation ~ ~-16 of a depository mechanism included within the mechanical control 17 subsystem shown in Fig. 4;
18 Fig. 9 is a block diagram, schematic representation 19 of a card~handiing mechanism for the mechanica~ control sub~
system shown in Fig. 4;
21 Fig. 10 is a block diagram, perspective representation 22 of a panel door mechanism included in the mechanical control 23 subsystem shown in Fig. 4;
24 Fig. 11 is a block diagram representation of a user communication subsystem for the control system shown in , ~ .. . .
26 Fig. 2;
27 Fig. 12 is a block diagram representation of a . 28 transaction statement dispenser subsystem included within the ;
29 control system shown in Fig. 2; and ` 30 Fig. 13 is a block diagram representation of an ' , , ` : : , ~ :

~06462~

1 operator function subsystem included within the control 2 system shown in Fig. 2.
3 Detailed Desc~ ion 4 A transaction terminal 10 in accordance with the invention includes an outer protective shell or cover 12, and 6 a user panel 14. An access panel (not shown) at the rear 7 of the machine permits access to an operator panel as well as 8 access which is required for normal terminal maintenance such ;
9 as the repunishment of bills and transaction statement forms and the clearance o any jam that might occasionally occur.
ll A user panel door 16 is shown in a raised condition. The -~--12 panel door 16 is normally closed to protect the user panel.
13 A user requested transaction is initiated by 14 inserting a user credit card having information recorded on a `;
magnetic strip thereon through a credit card slot 16. A
16 credit card transport system within the terminal lO senses 17 the presence of the credit card in the slot 16 and carries 18 the credit card into the machine and past a readhead to a i~
` . -l9 temporary holding position. If the information read from the 20 card 18 indicates that the~terminal 10 is to process a trans- i 21 action request related to that card, the panel door 16 is opened~ -22 to make a keyboard 22, optical display 24, deposit flap 26, 23 and a document issue slot 28 available to the user. The ~s 24 optical display 24 then instructs the user to enter his persona] ID number through a numerical field 26 of keyboard 26 24. A 6 digit personal ID number is then entered through the 27 keyboard. At the option of the owner of terminal 10, this 28 number may be tested to correspond to information read from ~;
29 the credit card. The user is next directed by optical display 24 to indicate the type of transaction he wishes to request by SA974017 _7_ :~ ' ' ' ~
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1 activating a key within a function selection field 28 of 2 keyboard 22. The user indicates the transaction type by 3 a desired key~ such as a withdraw key or a funds transfer 4 key, within the function selection field 28. I~ the trans~

5 action requires,the user is then directed by the optical :~

6 display to indicate the account from which funds are to be

7 withdrawn or transferred by activating a key within a "from ~; 8 account" field 30 of keyboard 22~ As typical examples the : 9 user might select a credit card account, a savings account ::`
10 or a checking account. If the transaction requires, the ~ :
11 optical display next directs the user to select the account .-~
12 to which funds are to be transferred by activating a key within : 13 a "to account" field 32 o keyboarcl 22. The same accounts are `
~ .
14 ;typically available for selection by both the from account . .15 field 30 and the to account field 32. A withdrawn transaction :
16 would of course require no key activation within the to ~ ` :, 17 account field 32 and the optical display 24 would direct the : ~ 18 user to enter a dollar amount through the numeric field 26. .
~ .
19 Upon entry of the dollar amount, this amount is presented on optical display 24 and the~user is requested to verify the 21 amount by activating a "proceed" key 34 within a transaction .
22 control field 36 of keyboard 22;. If the amount is incorrect -~
' : - -~, ~ ~ .
- 23 the user may enter a new amount through the numer~c field 26~S
` 24 or terminate the transaction by activating a cancel key 38 -:
.. ..
within control field 36. The canceled key may be activated 26 at any time during the course oE a transaction up to cash ```
. 27 issue and causes the transaction to be cancelled with the . . 28 credit card 18 being returned through slot 20 and the :~
29 panel door 16 closing. ~:
If the dollar amount i.s verified by an activation of :,-: SA974017 -8-,.... ., : ., ,-: ~ , :

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~ 2 l the yroceed key 34, the terminal lO assembles the information -2 read from the credit card and the information received through -~;
3 the keyboard 22 into a transaction request message which is ``
4 communicated to a host data processing system. The host data 5 processing system responds with a transaction reply message `
6 and also stores the transaction information for the terminal 10. ;
7 Stored transaction information can then be used for updating

8 user accounts in accordance with executed transactions~ ~

9 Alternatively, the host data processing system may be an on-line ~ `
processing system with access to a large data base of storing 11 user account information. In this case, the host data 12 processing system, upon receipt of the transaction reques-t `
13 message, would access the indicated user account files. The 14 account information would be utilized to authenticate the user ;. ;
15 ID number and check for any restrictions such as overdrawn -16 limits or cash withdrawn limits that might prevent execution 17 o~ the transaction.
18 If the transaction is approved, a transaction reply ,' , `
19 message showing approval is communicated to the terminal 10 2Q which responds by executing the requested transaction. This 21 execution mig~ht involve the issuance of cash, the issuance of `~`
22 a credit transaction statement, the display o~ account informa~
23 tion or simply an indication that the requested transaction , 24 had been executed. Upon execution of the transaction, the ; ~`~
terminal I0 returns the credit card 18 through slots 20, closes 26 the user panel doo~ 16 and communicates a status message to the .
27 host data processing system to indicate that a transaction has 28 been executed. This status message allows the host data ; ;~
29 processing system to close the transaction which opened with the 30 transaction request message. The terminal 10 then awaits the ~

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1 insertion of a new credit card.
2 In order to further aid the user in selecting keys 3 of the keyboard 22 which are to be activated, the keys within 4 the function selection ield 28, ~he from account field 30 S and the to account field 32 are color coded and each contains 6 a backlight. When a key is to be next activated in one of ~-7 these ields 28, 30, 32, ~all of the backlights in the Eield 8 are illuminated. When a key from this field is selected, the 9 activated key remains backlighted to provide audit trail which ~`;
is indicative of the requested transaction while all other 11 backlights within the field are extinguished. The backlights 12 and optical display are operated under program control to 13 prompt a sequence of keyboard entry by the user which is , 14 consistent with a requested transaction and will not necessarily `
be the same for every requested transaction. For example, a 16 funds transfer request would requixe the identification of an 17 account through the to account field 32 while a cash issue ~ `
18 request would not. Furthermore, a user may revise or change `;
19 h~s transaction request by selecting a different key within a `~
previously selected function select or account field 28, 30 or-21 32 by merely activatlng a different kèy. The process of 22 entering the transaction request then continues from that 23 revision point.
24 Referring now to Fig. 2, a terminal control system 50 ." ~ ~
for terminal 10 includes a terminal information bus 52, a 2~6 programmable data processor 54 coupled via inEormation bus 52 -, . ..
27 to a plurality of terminal adapters or elements 60-65. In ~
28 general, the terminal elements 60-65 do not actively make any -`
29 decision but merely act as a conduit for terminal data signals ;
30 which are generated by the data processor 54 and communicated - ~
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1 to control a driver circuitry for controlling the operation 2 of actuators wi~hin the element. Each elemen~ also accumulates 3 terminal status information which may be transferred along ~ 4 terminal information bus 52 to the data processor 54.
- 5 clock signal generator 68 generates a clock signal for the data ; 6 processor 54 and a 1 MHz clock signal which is utilized by ;~ 7 operational hardware subsystem element 60 for providing timing 8 functions within control system 50. A remote signal connector - ;
9 70 allows a communication between the terminall0 and a central control panel which may be used to monitor and control plurality 11 of terminals similar to terminal 10. The remote control panel ` 12 (not shown) may include lights to :indicate when the terminal 13 is opened, when a terminal is in use, when a cash low condition 14 exists, when a forms out condition exists, or when an exception condition such as a document jam exists. Control switches 16 available at the remote control panel permit the terminal 10 17 to be turned on or off, to be connected or disconnected from r`
18 the communication line and to an internal communic~tion function ,: . : .. :-19 "wrap test". The remote control panel is a convenience which is not necessary to the operaticn of the terminal 10 and of i~
-~ 21 course additional status or control functions could be assigned 22 to the remote signal connector.
23 The data processor 54 includes an 8 bit parallel - 24 mi~roprocessor 72 and data storage 74. The microprocessor 72 may be any conventional parallel processor. Data storage 74 :,`'J 26 includes read only storage (ROS) for the storage of fixed 27 program and table information and random access storage (RAM) 28 for the storage of scratch pad information, information which ~; 29 may be varied so as to select the desired options of each 30 customer, display message text, optical character fonts and -:, ~" ~',' .-~'.' : ~ ' .. . ' ' . ;

~0~46Z~
1 other information that may vary during the course of the2 operation of control system 50. The information retained by 3 by the random access storage is lost each time the terminal 10 4 loses power and thus must be reinstated by an initialization image supplied by the host data processing system each time 6 the ~erminal 10 goes from a power off to power on condition.
7 The terminal information bus 52 may be conventional 8 in nature. The bus and the interface logic for controlling the 9 transfer of information along the bus may be of the type described in U. S. Patent No. 3,336,582 or U. S. Patent No.
11 3,488,633. Other suitable bus and interface circuitry is 12 described by the various makers of mini-computers. As described ~;
13 herein all data transfers are referenced with respect to the "~
14 microprocessor 72. Thus, a write operation represents a data -~
15 transfer from the microprocessor 72 to a subsystem element and -16 a read operation represents a trans~er from a subsystem element 17 to the microprocessor 72.
18 While this invention is in no way dependent upon th~
.
19 exact nature o~ the terminal information bus 52 it will be presumed that the bus 52 includes 9 data out-lines (8 bit +
21 parity), 9 data in-lines (8 bits f parity), control out-lines 22 and control in-lines. Three mutually exclusive time periods 23 -are established by the control signals for the communication of ~ -24 bus inormation. At an address time, an address signal is generated by the microprocessor 72 to select one of the sub-26 system elements 60-65. At a command data signal time, command 27 information is communicated from the microprocessor to a selected `~
28 subsystem element. Finally, at data signal time terminal data 29 may be either transferred on the data out bus to a selected subsystem element or on a data in bus from the selected element 1~6~6Zl .
1 to the mic~processor 72. The direction of the terminal data 2 transfer is dependent upon the nature of the preceding command :~
3 data signal. Interrupt request generated by the subsystem 4 elements 60-65 may also be communicated along the information .~ 5 bus 52. ~.
; 6 The processor support subsystem 60 operates as a 7 logical extension of the microprocessor 72 by providing 8 system control functions that are preferably implemented with .~.
9 hardware rather than software. One element of the processor `~

10 support subsystem 60 is a ten bit binary counter 100 which ~

11 receives the one MHz clock signal from clock signal generator -~ :

12 68 and generates lower frequency clock signals which are used .--: :

13 throughout the control system for the terminal 50 for terminal `.

14 10. Counter 100 is resettable by a terminal reset signal ; 15 which is also generated by the processor support subsystem 60. ~: :
16 This terminal reset signal is generated by a single shot 102 ~ . :
.. . . . .
17 which is activated in response to either a reset switch on 18 the operator panel of the terminal or in response to a hangup `~ .-.
. 19 signal 104 from a hang detector 106. The hang.... detector 106 .. ~:.
- 20 is implemen~ed as a single shot which provides an output on "~
l; 21 signal line 104 only after a period of time ~T following the ~.
.' 22 triggering of the single shot. The single shot is connected . ;
23 to be triggered in response to activity on the control out ' ;.~ .
i 24 portion of the terminal information bus lines 52. Thus, each ~ ~.
` 25 time there is activity on the data bus that causes activity, ~
26~ the single shot 106 of hang detector 106 is triggered to reset .:
' 27 the delay time ~ T. Delay time ~ T is chosen to be on the . 28 order of 0.5 seconds so that the time is extremely long with :~ 29 respect to the normal time between the bus activity but yet relatively short from the point of view of a person using the SA974017 -13~

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1 terminal 10. The hang detector 106 causes the microprocessor 72 2 to reset to a predetermined program instruction in the event 3 that an unrecoverable error condition causes interruption of 4 the normal program execution. For example, as a result of an error occurring as data is transferred from the memory 24 to 6 the microprocessor 72, an instruction received by the micro-7 processor 72 may contain an operation code which is ~leaningless 8 to the microprocessor 72 and which does not permit the micro-9 processor to continue the execution of instructi~ns. In the event that such an error occurs, the microprocessor merely comes ;-11 to a complete halt. Normally some kind of operator intervention 12 would then be re~uired. However, the hang detector 106 detects ~-13 the lack of any bus activity and generates an output signal on 14 line 104 which causes a single shot 102 to generate a terminal reset signal. The terminal reset signal causes the micro-16 processor 72 to fetch an instructionfrom a predetermined location 17 in data storage 74 which permits the microprocessor 72 to 18 restart normal operation if further unrecoverable errors do not ~
19 occur. Terminal reset signal is also carried by information ` ~-bus 52 to other subsystems which are connected to the bus and 21 utilized to r~set registers and latches within the other sub-22 systems where appropriate. The terminal reset signal generating 23 single shot 102 is responsive to a switch that may be locatéd~
24 on an operator panel as well as to the hang detector 106. The : .
customer is thus given the option of resetting terminal 10 26 manually at any time even though a manual reset is not required 27 to permit recovery by the microprocessor 72 from what would - , - . ,.
28 normally be an unrecoverable error. Other signals as appropriate 29 for various microprocessors may of course be monitored to drive the hang detector 106. For example, the control lines, the SA974017 ` -14-~ .

1~6A6;Zl' 1 address lines, or even the data lines which connect the j . .
2 microprocessor 72 to the data storage module 74 might be 3 monitored. I~ the microprocessor 72 is working properly, it 4 must execute memory fetch cycles at regular intervals and `~
monitoring of these memory control and data signals would 6 permit a determination of whether the memory fetch cycles are - 7 occurring. In addition, some data processors have an output ; 8 signal which drives a panel indicator to indicate whether or 9 not the processor is executing instructions. This signal could ; lO of course be monitored by the hang detector 106 where available.
11 A run detector 108 also monitors the control out : , .
12 signals on the information bus 52 and is connectable to drive ;
13 an indicator light on an operator control panel and also which 14 indicates that the terminal lO is operating satisfactorily. --~

15 Run detector 108 monitors signal transitions the same as hang ;

16 detector 106 except that the output of run detector 108 is `~

17 active so long as microprocessor 72 is operating in a normal

18 (non-error) manner while the output of hang detector 106 becomes ;
l9 active when microprocessor 72 ceases to operate. The output of run detector 108 i5 also communicated ~o an intervention relay 21 which is connect~ble to drive an intervention required indicator ;`-~
22 light on the remote customer control panel whenever the output 23 of run detector 108 becomes inactive or whenever a control signal 24 which turns on the main power to the electromechanical actuators of terminal 10 becomes inactive. The intervention required 26 relay is also controllable by the microprogram via mechanical 27 control subsystem 61, thus providing means for either the micro-28 program or host via microprogram to indicate system detected 29 errors. The intervention required remote control indicator light thus indicates an exception condition for terminal 10, . . :
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1 which typically needs operator intervention.
2 Processor support subsystem 60 also generates 3 interrupt requests at 10.24 msec. intervals to provide micro~
4 processor 72 a time base to permit the timing of various opera- -;
tions associated with the terminal 10. The interrupt generating ~;
6 circuitry includes a counter 112, decoder 114 and OR gate 116 ;~
7 driving a reset input to counter 112, a toggling flipflop 118 -8 and a pair of AND gates 120, 122. The counter 112 receives a -9 976.5 Hz signal from counter 100 and operates in conjunction with -~
decoder 114 to count by five. Decoder 114 senses a count of fivé
11 to activate the reset input to counter 112. Counter 112 thus 12 actually goes through six count states (0-5) but because count -13 state 5 and count state O occur within the same count pulse 14 cycle it functions as a divide by 5 circuit. OR gate 116 also -responds to the terminal reset signal to reset counter 112.
16 Decoder 114 also generates a short output pulse upon detection 17 of count 5. This output pulse drives flipflop 118 as well as 18 AND gates 120 and 122. As the pulse output from decoder 115 -~

19 goes high, one of the AND gates 120, 122 becomes enabled, ~

20 dependent upon the state of flip-flop 118. As the pulse goes ~ -;

21 low, the AND gates 120, 122 are disabled and the flipflop 118 .

22 is toggled by the falling edge. 'AND gate 120 thus generates

23 a signal A having short duration pulses which occur at 10.24 ; 'b ' '` .'

24 msec. intervals. Similarly, AND gate 122 generates an output signal B having short duration pulses which also occur at ;: ~:
~ 26 10.24 msec. intervals except that signals A and B have an - ;
,...................................................................... . .
27 opposite phase relationship.
28 Read circuitry 124 within the processor support sub-'~! 29 system 60~receives the signal from the read circuitry 124 and 30 includes conventional amplification and logic detection circultry ;

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1 for reading information which is stored on a magne~iccard 2 stripe in a conventional double frequency binary format.
3 However, it should be noted that read circuitry 124 includes 4 an 8 bit accumulation register and an 8 bit buffer register.
Data is accumulated in the 8 bi~ accumulation register 128 in 6 bit-by-bit serial fashion. Ater the accumulation register `
7 128 is loaded, a buffer clock signal (BCK) is generated to - ~ -8 transfer the contents of the accumulation register in parallel 9 to a buffer register 130. The clock signal BCK simultaneously : . - .-:
is utilized to toggle a flip-flop 132 from the reset state to 11 the set state to cause the generation of a credi~ card interrupt` ``
12 signal at the Q output therefrom. This signal causes the 13 generation of a processor support subsystem 60 interrupt `~
14 request. As the microprocessor 72 processes the interrupt~
request, it addresses the processor support subsystem 60 and 16 causes a read CCR signal to be generated by a command decoder 17 and latch 140. The read circuits 124 respond LO Lhe read CCR
18 command by generating a read byte signal which simultaneously 19 gates theparallel contents of buffer register 130 onto a -. . , - . .
processor support subsystem data bus 142 and activates an OR '~ -21 gate 144 to simultaneously reset toggling flip-flop 132 and an 22 SR flip-flop 146. If, however,'`the buffer register 130 is -.
23 loaded and then the accumulation register 128 becomes completely 24 reloaded before the contents of the buffer register 130 are read by microprocessor 72, the buffer clock singal, BCK, is 26~ still generated causing the contents of the accumulation `~
27 register 128 to be transferred to buffer register 130. When 28 this happens, the original contents of buffer register 130 " -29 are lost and it becomes impossible for the microprocessor 72 to acquire all of the information from the magnetic stripe of , . ~:

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106462~ ~

l the credit card without requesting reinsertion of the card. ~ ~
2 When the original information was loaded into buffer register `-3 130, signal BCK caused ~ip-flop 132 to toggle to the set 4 state. The subsequent signal BCK which causes buffer 130 to overflow, toggles flip-flop 132 back to the reset state. The 6 ~ output of flip-flop 132 drives the set input to flip-flop 7 146 to generate a credit card overrun signal 3 CCOR, at the Q
8 output of flip-flop 146. Normally, the output of OR gate 144 9 generates the resetting signal which resets both flip-flop 146 and flip-flop 132. However, when flip-flop 132 is toggled by 11 BCK back to the reset condition, the reset signal to ~lip-flop 12 146 is not present and flip-flop 146 is permitted to enter `~
` 13 the set state 14 Eaeh of the subsystems 60-65 includes a certain ` 15 amount of standar~ized circuitry that is repeated for each of ;- ~;~
- 16 the subsystems. This standardized circuitry includes bus : . .
17 interface logic 150, data bus 142, command decoder and latch 18 140, an 8 bit basic status register 152, basic status register 19 control logic 154, and an output gate 156 for basic status register 152. Bus interfa~e logic 150 is connected to the -21 control and data lines of information`bux 52 and includes the 22 circuitry which is necessary for transferring information over 23 terminal information bus 52. This eireuitry is eonventional 24 in nature and is therefore not described in detail herein.
,~ ~

25 In general, the bus interface logic 150 handles the receipt ;~ -2~ and generation of signals which permit microprocessor 72 to be ;; 27 assured that data transfers are accomplished without error. ~`~
28 It will be appreciated by those skilled in the art that the 29 requirements of the bus interface logic 150 will be in large determined by the particuIar microprocessor chosen for 72.

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1 More syecifically, the bus interface logic 150 2 recogniæes the presence on the terminal information bus 52 of 3 an address signal corresponding to a predetermined address and ; 4 thereafter acts during a subsequent command time to gate the data out lines of terminal information bux 52 to the data lines 6 of data bus 142. A command signal is simultaneously outputted ~ -~
7 to command decoder and latch 140 which causes the command 8 decoder and latch 140 to decode the information on subsystem 9 data bus 142 and to generate a single subsystem command control ;~ ~
10 signal. This command control signal is latched as the signal ;
11 command is removed by the bus interface logic 150. It will be 12 appreciated that each of the subsystems 60-65 includes a command ~ ;
13 decoder and latch such as command decoder and latch 140. It 14 should be further appreciated that wh~ e all of the command , ,, ~ .
decoder and latches operate in similar manner, the decoder 16 circuitry and number of latches will depend upon the control 17 commands and predetermined binary data combinations which are 18 selected to indicate commands. The command decoder and latch 19 140 thus contains five latches to sLore and decoder circuitry for recognizing each of five predetermined information signals 21 which indicate the commands. Bus intèrface logic 150 also 22 responds by connecting the data~out lines of terminal information .. .
23 bus 52 to the subsystem data bus 142 for a write command and 24 connecting the data in lines of terminal information bus 152 ;~
to the subsystem data bus 142 for a read command with the command

26 decod~r and latch 140 outputs having established the proper

27 gate signals to select the proper source for the data transfer. ~ ;

28 Thus, if the preceding command were a read CCR

29 command, during the time that signal data is active the read CCR command is output to read circuits 124 which respond by '~

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1 generating the read byte command signal which gates the 2 contents of buffer register 130 onto subsystem data bus 142 3 and also the data in lines of terminal information bus 52 ~-4 to make the contents o~ buffer register 130 available to microprocessor 72. Read byte signal simultaneously resets 6 flip-flops 132 and 146 as e~plained previously. I~ the previous 7 command from the microprocessor 72 had been a read basic ~ `
8 status regis~er command,the command decoder and latch 140 ~ .
9 responds to the signal data by outputting a command control , -~
10 signal read B.S. which gates the contents of basic status ~ -~
11 register 152 onto subsystem data bus 142 and the data in lines ~
12 of terminal information bus 52. The remaining commands which ~ -13 are applicable to processor support subsystem 60 are e~ecuted in 14 a similar manner. A set basic status command is actually a write command for which information generated on the data out 16 bus lines is communicated to the subsystem data bus 42. As 17 the set B.S. command control signal is generated, the individual 18 basic latches of the basic status register 152 are set in 19 accordance with a processor support subsystem 60 status signal `~
only if the line of subsystem data bus 142;(ADB0 through ADB7) 21 which corresponds to a particular latch contains à logic 1.
22 Any latch which corresponds to a subsystem data bus line 23 carrying a logic 0 remains unchanged. A reset basic status 24 command operates in a similar manner except that a basic status register latch corresponding to a bus l~ine carrying a logic 1 : .
26 is reset independent of the subsystem status information which 27 the latch is connected to represent. The IAD reset signal is -28 a command signal which is applicable only to the processor support 29 subsystem 60 and permits a resetting of processor support sub-system 60 without resetting the microprocessor 72 or any of the . . . , ~ . . .

~0~;46 ~ .
1 other subsystems in the terminal 10.
2 Latch 0 of basic status register 152 is connected 3 to indicate the generation of the credit card interrupt signal, 4 CCIRPT, by flip-flop 132. Latch 0 has the set and reset ~ ;
5 commands respectively controlled by the signals: `
6 SET BSO = CCIRPT-READ B.S.+ADB0-SET B.S.
7 RST BSO = IAD RST+ADB0-RST B.S.+RESET
8 Basic Status Latch 1 is the interval timer interrupt latch and 9 has the set and reset inputs respectively driven by the logical functions~
11 SET BSl = ITIRPTA-READ B.S.+ADBl-SET B.S.
12 RST BSl = IAD RST+ADBl RST B.S.+RESET
13 Latch 2 has not assigned signiicance. Latch 3 is used to 14 selectively inhibit the 10.24 msec. interrupt signal from : , l~ 15 generating an interrupt request. The control inputs are: -, 16 SET BS3 = ADB3-SET B.S. ;
17 RST BS3 = IAD RST+ADB3-RST B.S.+RESET ;
18 Latch 4 is the credit card overrun latch and is set and reset 19 in accordance with the respective logical func~ions:
SET BS4 = CCOR-RE~D B.S.+ADB4-SET B.S.
21 RST BS4 = IAD RST+ADB4-RST B.S.+RESET
, , . ~
22 Latches 5 and 6 are not implemented.
23 Latch 7 is the interrupt request latch and a logic 1. -;~
24 output indicates a pending interrupt request. The output of latch 7 isconnected to gate 156 along with the.outputs of the 26 other latches but is also connected directly to the bus inter-27 face logic 150 on a line which bypasses gate 156. Bus inter-28 face loglc 150 responds to this bit 7 signal by communicating ;~
29 an interrupt signal to microprocessor 72 via terminal information bus 52. Latch 7 is set concurrently with latches 0, 1 and 4 and "~ .

;4~Z~

l is set and reset ,in accordance with the respective logic 2 functions: ~ :
3 SET BS7 = (ITIRPTA+CCOR~CCI)-RE~D B.S.~D7-SET B.S.
4 RST BS7 = ADRST+AD7 RST B . S . +RESET
5 The signals ADBO-ADB7 indicate the separate bit ;` ':~
6 signals on the subsystem data line 142 and permit the selective 7 loading and resetting ~ each individual basic latch in the ,-8 basic status register 152.
9 Mechanical Control Subsystem Reference is now made to Figs. 4-10 and more particu- ' '`:~ -11 larly to Fig. 4 which shows the logic portion of the mechanical ' 12 control subsystem 61 of the control system 50 for terminal 10. '~
13 The circuitry included within the mechanical control subsystem .' 14 61 which is similar in nature to circuitry within each of the subsystems 60-65 includes bus interface logic 200, an interrupt 16 request flip-~lop 202, a command decoder and latches 204, a 17 basic status register '206, an output gate 208 for basic status "
18 register 206, basic register control logic 210 and a subsystem 19 data bus 212. These circuits operate in a manner as described ' in conjunction with the pracessor support subsystem 60 except 21 that command decoder and latch 204 responds to control commands '~
22 which are particularly related to the mechanical control sub~
23 system 61 and the terminal status input to the basic status ~ "'`:
24 register control logic 210 are unique to the mechanical "~
control adapter 61. In addition to decoding a,nd latching three 26 read commands, read 0, read 1, and read 2, three write ' :.' 27 commands, load A) load B and load C, a subsystem reset command ~.. `''.
28 CADRST, a set basic status command, and a reset basic status ~ -29 command, the command decoder and latches 204 generates a read ,~.' `.
gate signal concurrently with the outputing of a read 0, read 1 '`.: ~:
SA974017 . -22~
:. . !.

: ",, .

~0646Zl 1 or read 2 command during the data time.
2 The mechanical control adapter 61 executes direct ~-3 and specific instructions from microprocessor 72 to control the 4 operation of the mechanical equipment required to operate the terminal 10. The individual command signal for the operating 6 hardware are stored in three 8 bit registers A 216, register 7 B 218 and register C 220. All three registers are connected 8 to be reset by a reset signal ADRST generated by an OR gate 222 9 as the logical OR of a terminal reset signal, T. RESET, or a 10 mechanical control subsystem reset control command, CADRST. ~ .
11 The data input to the 8 bit positions of register A 216, 12 register B 218, and register C 220 are coupled respectively -13 to the 8 corresponding lines oE subsystem data bus 212. The 14 clock input o~ the register which causes the contents thereof to assume the data state of information appearing on bus 212 16 are coupled respectively to command control signals from ;, 17 command decoder and latches 204 load A, load B and load C.
18 Bi~ O of register A controls the direction o~
19 operation of a credit card transport mechanism 26 and an escrow transport mechanism 228. This bit position does not control !'`"'' 21 the turning on and off of the mechanism but only the direction 22 of travel when the drive motors'are turned on by other bit 23 position control signals. A logic 1 in register A bit s ~-24 establishes direction control such that if the motors were 25 running a credit card would be transported into terminal 10 ``
26 by transport mechanism 226 or a document held in escrow would 27 be transported toward a reject beam 230 by a document escrow 28 transport system 228. Register A bit 1 controls the energization 29 of the motor for the credit card transport mechanism 226 whereby a logic 1 will cause the motor to be turned on. Register A

.-. --: - . ...... ... . . ................. .. ..
.. . . . ..

~0646;~
1 bit 2 controls the activation of a motor which drives the 2 escrow transport system 228 whereby a logic 1 will cause the 3 motor to be energized. Register A bit 3 controls the activation 4 of an escrow clamp mechanism 234. A logic 1 causes an escrow clamp mechanism to be energized to hold the contents of escrow 6 in a transport position. A logic 0 causes clamp 234 to be 7 released to permit the loading of additional documents into 8 escrow. Register A bit 4 is not assigned. Register A bit 5 9 determines which of a pair of bill feed clutches 236, 238 for `
cash issue mechanisms 240, 242 respectively may be activated.
11 A logic 1 selects a clutch 238 for a second document feed ` -12 mechanism 242 and a logic 0 selects clutch 236 for first docu~
13 ment feed mechanism 240. Register A bit 6 is a power on control 14 bit and when set to logic 1 energizes a relay which makes power available to motors 244, 246 which drive stacker wheels 245-248 16 and document transport mechanisms for the document feed -17 mechanisms 240 and 242. This bit position also controls relays;
18 which make AC power available to a transaction statement printing 19 mechanism 250 and high voltage DC power available to the user guidance display 24. Register A bit 7 controls the activation 21 of whichever feed clutch 236 or 238 wa's selected by bit A5.
22 This bit when set to logic 1 allows the energization of the -23 clutch and is reset when the first photocell detecEs the feeding `
. . ~
24 of a bill. The stacker wheels 245-248 contain serpentine tines ` 25 260 at the periphery thereof which receive and guide issued ~
26 documents. A light emitter 262 and photosensor 264 operate ~ ;;
- 27 in conjunction with an indexing wheel 266 which rotates with the ~`
, ~
28 stacker wheels 245-248 to provide an output signal to AND
29 gate 252 whenever a document which if fed at that instant will ' ; 30 reach the stacker wheel at the appropriate time to enter hetween ., '`

. . ~ . " ,, . :

1~3646Z~

1 two adjacent serpentine ~ines 260. 'rhe output of AND 252 is ... .
~ 2 used to set latch 253 which in turn activates bit A7 of driver - 3 326 which actually drives the clutch. Register A bit 7 is `~ 4 unique in that it is connected to be reset by a signal RSTB7 - 5 which occurs as soon as the feeding of a bill from a selected . 6 document feed mechanism is complete. The signal RSTB7 turns .. 7 off register A bit 7 which in turn resets latch 253 to :~
.. 8 deenergize driver A7 and thus the selected clutch. This unique : -9 reset signal RSTB 7 is utilized because the timing for deactivating~
the clutch 236 or 238 is too critical to wait for microprocessor -. 11 72 to sense the fitting of a bill and then load a 0 into register .` 12 A bit 7. The output o the clutch driver, Driver A7, is also ' 13 used to control relay 256 to energize restraint belt drive -~ 14 motors 237, 239 only when a corresponding clutch 236,238 is ... .
15 energized as defined by the activation of relay 257 by bit A5. ~i~
16 Bit 0 of register B controls the operation of user 17 door 16. When this bit is set to a 1, the user door is opened, 18 when set to a 0 the door is closed. Bit position 1 and 2 of ~ ~;
19 ~register B are unassigned. A 1 in bit position 3 of register B
activates a solenoid 264 wh.ich drives an open/close indicator 266 21 to an open position and a detent 268 to a releasè position to `~
22 permit entry of a user credit càrd 270 past a blocking roller 23 272. A logic 1 at bit 4 of register B activates a deposit ..
24 mechanism 274 by energizing a motor 276 which drives a deposit 25 transport mechanism and unlocks a flap 278 which blocks the :
26 deposit entry 26.- Bit 6 of register B.drives an attention Z7 : required relay which is logically ORed with a run signal from 28 a process support subsystem 60 to provide a contact set which 29 can be used to drive an indicator light on a remote control panel to indicate that attention is required by the terminal 10.

,.
~', SA974017 -25- .

. ~.

.
. .

!

~06~6Z~ ;
:.
1 The relay ard driver are arraL1--ed suc'. ~it power must be available r.~ ::he~ relay and a logic 1 must be stored at bit 6 3 of register B in order to prevent the activation of the ;
4 attention require signal at the remote control panel. Bit position 7 of register B is unassigned as are all bit 6 positions of register C.
7 Corresponding to each of the registers 216, 218 and ~
8 220 are eight bit drivers, driver DA 326, driver DB 328, and ~ ~`
9 driver DC 330. ~s illustrated by way of example for bit posi~
tion AO, each of the drivers outputs is a grounded emitter, 11 open collector NPN transistor 232. The base of each transistor 12 is connected through a suitable predriver stage to a Q output 13 of a corresponding latch in the control registers 216, 218 and 14 220. The collector of each driver transistor 332 is connected through a resistor 334 to a positive voltage supply, and to 16 an output control line 336 from the driver, through a common ~
17 cathode diode 328 and to a common 14K resistor 340 in series ~ ~`
18 with the input of a Schmidt trigger 342. The output of Schmidt `~
19 trigger 342 is fed to a driver wrap test bit OP~ in the status :
input circuit 344.
21 The Schmidt trigger 342 acts as a negative input OR
22 gate in that it generates a logic 1 output signal in the event 23 that any of the drivers 332 are not on. This rela~ionship 24 permits use of the driver wrap bit, bit 00, to test the drivers.
First, all of the drivers are turned on simultaneously, then 26 if all drivers properly turn on~ a logic O should be read from 27 the driver wrap bit. Thus, a malfunctioning open driver would be 28 detectable. Next1 the drivers are tested for shorted drivers 29 by turning on all but one driver. If the driver wrap bit goes to logic 1 the driver is properly turning off because it is ...

~L06~6Z~l -1 known that all drivers are properly turning on and only the 2 driver under consideration has been commanded to turn off, and 3 in facL is off. This test is repeated for all drivers.
4 The resistor 334 insures a logic 1 output for unconnected drivers while being sufficiently large in magnitude to have 6 substantially no effect on connected drivers. This eliminates 7 the need for many special tests dependent on features installed 8 in a given machine. The drive wrap test need not have any 9 effect upon terminal operating hardware mechanisms because the rel~ys and solenoids which control these mechanisms operate 11 relatively slowly in comparison to the speed at which the drivers 12 may be turned on and off during the course of a driver wrap 13 test.
14 Status input circuit 344 contains eight RC input lS circuits of which only input circuit 350 is shown by way of 16 example. These input circuits 350 serve as low pass filters to 17 reduce switch bounce or other high Erequency noise on inputs 18 thereto. Inputs circuits 346, 348 are identical to input cir-~: . .
19 cuit 344 and each include eight of the RC input networks 350. ~
.,1 ~
Gates 352, 354 and 356 permit the gating of one of the 21 status circuits 344, 346 or 348 to an OR gate 358 in response ;~-~
.
22 to a read 0 command, read l command or read 2 command respectively.
23 A reset signal is generated as the complement of a gate signalD
24 and normally holds the contents of an 8 bit latch 360 in a reset ~ ;
condition. How~ver, as one of the read command signals 0-2 goes 26 active during the data time, the read gate signal is activated 27 to terminate the reset signal to register 260-and enable a Z8 gate 362 which passes the contents of read register 360 on to 29 the subsystem data bus 212. As the reset signal for register 360 goes inactive the 8 latches are permitted to assume the ~(~6~62~
1 respective states of the eight signals which are transferred 2 through OR gate 358 from one of the gates 352, 354 or 356 3 depending on which read command is executed. It is thus 4 possible to selectively load 24 drivers by setting bits in 5 registers 216, 218 and 220 and to selectively read 24 bits of `~
6 subsystem status information by selectively sampling the 7 status of the three data input circuits 344, 346 or 348.
8 The inputs to the subsystem status circuitry 344, 9 346 and 348 have the following assigned meanings:
Bit 00 is responsive to an escrow issue switch 11 which indicates that documents have been transported by the 12 escrow transport mechanism to a position where they are avail~
13 able to a terminal user.
14 ~ Bit 01 is an escrow reject switch signal which indicates that documents within the escrow area have reached 16 an escrow dump bin. Continued energization of the escrow 17 transport mechanism for a predetermined period of time following 18 the appearance and subsequent loss of the escrow reject signal 19 provides assurance that all escrow documents have been dumped -20 into the reject bin. ~` -21 Bit 02 is responsive to the document feed mechanism ~;
22 selection status condition with a logic 1 indicating t~ t ..
23 document feed mechanism 2 has been selected by bit position A5;.3 24 Bit position 03 assumes a logic 1 when the light path is interrupted to the third photocell, PC3, of the selected 26 document feed mechanism. -' ~?~
27 Bit position 04 assumes a logic l when the light 28 path to a second photocell, PC2,of a selected document feed 29 mechanism'is interrupted.
Bit 05 assumes a logic 1 when the light path to a ~064~2~L

1 first photocell, PCl, is interrupted for a selected document 2 feed mechanism. It is this cell that originates the signal ~ ;
; 3 which causes bit A7 to be reset.
4 Bit 06 remains a~ logic 1 so long as there is adequate ;
cash in both of the document feed mechanisms. A cash out 6 condition in either mechanism causes bit 06 to assume a logic 0 7 condition.
8 Bit 07 indicates that bi~ A7 (feed request) is turned 9 on.
10 Bit 10 is a credit card input switch which indicates ~:
., ~ . .
ll that a credit card has been inserted into the terminal 10 by a 12 user.
13 Bit 11 is a credit card sense switch which indicates 14 that a credit card is adequately returned so that a user may easily remove the card. This switch also allows detection of 16 exit jams and cards pushed back in rather than removed.
.. . . .
i 17 Bit 12 is a credit card escrow station switch which 18 indicates that a credit card has reached an escrow area adjacent 19 a retention bin. Transportation of a credlt card into the terminal 10 for a predeter~ined time subsequent to the appearanc`e 21 and subsequent disappearance of a logic l at bit 12 provides 22 assurance that a credit card has been dumped into a credit card~
23 retention bin should card retention be desired. - i ~`? '~
24 Bit 13 assumes a lo~ic 1 state while the clutch for `-the second document feed mechanism is selected.
26 Bit 14 indicates that the user panel door is in a 27 closed condition. ~ ;
., . ... ~
28 Bit 15 indicates that the user panel door is in an 29 open condition. `
,' 30 ~ Bit 16 is not assigned.
'' ;. ~:

" - '', , I' ' ~` ~

1~6~L6Z:~
1 Bit 17 is the driver wrap error bit and indicates 2 that not all drivers are on as sensed by Schmidt.
3 Bits 20-24 are not assigned.
4 Bit 25 indicates that either an escrow door through ;
which cash and transaction statements are issued or a deposit 6 door is not locked.
7 Bit 26 indicates that a deposited document has ~ -8 passed a first sensor, sensor A, along a deposit transport ~
~ . . .
9 path. ~ ~;
10 Bit 27 indicates that a deposited document has ;
11 passed a second deposit sensor, sensor B, along the document -12 transport path.
13 Because of the large number of status conditions 14 which are sensed by the mechanical control subsystem, an interrupt request is not generated each time a status condition 16 changes. Instead, the microprocessor 72 is expected to maintain 17 the system status information current by reading the status -18 inputs at regular intervals. The set input to interrupt request `~
19 1ip-flop 202 is responsive to a power out warning indicator signal POWI which is generated by a power condition sensor 21 within operator unction subsystem 64.
22 As shown in Figs. 5 and 6 the document handling system 23 i~ ludes a first document feed mechanism 240, a second document ., :- .
` 24 feed mechanism 242 which is positioned forward of document feed 25 mechanism 240 and a printer mechanism 250 which is positioned . -~
; 26~ in line with the first document feed mechanism 240. Trans~
27 action statements issued by printer 250 and cash issued by - -. 28 document feed mechanisms 240, 242 are transported to an escrow 29 area 380 where they are selectively transported by an escrow

30 document transport mechanism 382. ~
'. ` ,, , SA974017 _30_ . ~ .

~0646Zl 1 The printer 250 includes a hopper of cards 386, a 2 forms low sensor 388 generating a signal F.L. and a forms out 3 sensor 390 which becomes active to generate a signal F. OUT
4 when there are no longer su~ficient forms to insure the 5 completion of a transaction. ...
6 Control circuits 388 receive data information for each 7 print line as well as feed and print/increment signals from the '~
8 transaction statement subsystem 63. Upon receipt of a feed 9 command, a feed mechanism solenoid 390 within feed mechanism 10 392 is activated to cause a single transaction statement form ~ ' 11 to be removed from hopper 386 and transported to a position 12 within a print mechanism 396 where it is ready for the start 13 of printing. A card in position switch 394 senses the position 14 of a form beneath the printing mechanism to stop the feed ~, mechanism 392.
16 After a form is in place, a print/increment si~nal 17 causes a column of information to be printed on the form with , , ' 18 the form being positionally incremented in preparation for the ,~
19 next print increment command. In~ormation is p,rinted on a form ~ -~beginning at the lefthand edge with four rows of infoxmation ' '~ ' 21 being simultaneously printed a column àt a time. The print ' ~.; ;
22 mechanism 396 includes 4 print wheels 398 which rotates in 23 contact with an inking roller 400, a hammer assembly 402 con~
. . .
24 taining four print hammers which are positioned on the top side '''~
. :~
" 25 of the statement forms opposite the print wheels 398 and a ,~
,~ 26 forms increment mechanism 404 which includes a rachet wheel ' ', 27 406, and a pawl 408 which is positioned and connected to advance , 28 a form one column position each time a solenoid 410 is activated ",~
.... .
29 on command from control circuits 388. A sensor 412 provides indexing information to control circuits 388 to permit the , SA974017 -31- '`
, ,~ ~
P: .. .. . ~ ,., :,, . . ,, . , . ~ , ., . . , ~ , .

~0~46Z~

1 activation of one of the hammers 402 whenever the corresponding 2 print wheel is in proper alignment for the printing of a ; 3 character as indicated by a data register within the transaction 4 statement dispenser subsystem 63. As soon as the proper -;
character has been printed at each of the four lines, the 6 solenoid 410 is incremented in preparation for the next print/ `~
7 increment command. An interrupt request is generated at the -8 completion of each feed command or print increment command to 9 inform the microprocessor of the execution of the command so ~`~
that another operation may be commanded.
11 After 40 print/increment steps, a transaction state~
12 ment form reaches a form transport mechanism 416 which carries 13 the printed form to stacker wheels 247 and 248 for stacking in 14 a vertical position opposite the first document feed mechanism 240.
16 After the completion of the printing and stacking of ~, 17 transaction statements cash may be issued by the document feed -18 mechanism 240. It will be appreciated that document feed 19 mechanism 242 is substantially identical to the first document 20 feed mechanism 240 and for this reason only the first document ~`
21 feed mechanism 240 will be described in detail. The document 22 feed mechanism 240 includes a hopper subassembly 420, a bill 23 feed mechanism 422, a transport mechanism 424 and tlie stacker .,'b ;.' 24 wheels 247, 248.
The hopper subassembly includes a hopper 428 for ~ -~
26 storing the currency 430. Beneath the hopper 428, a feed belt ~ ?~
27 432 drives a backing plate 434 which forces the bills 430 toward ~`
28 the front!of the hopper. As bills are removed from the hopper 29 428 a pressure sensitive switch 436 is closed to activate a ` 30 relay 438 to energize a motor 440 and increase the forward -~

; ,, ' ~.:
., .. ,. ~ ., . , ,. , , , . . , . . ~

1~64623L
1 pressure on the currency 430 until switch 436 is again opened 2 in response to the increased pressure. The currency 430 is 3 thus continuously urged into communication with the bill 4 feed mechanism 422 under substantially constant force. Forms low sensors FLl and FL2 for the first and second document 6 feed mechanisms 240, 242 are closed as the backing plate 434 7 reaches a predetermined switch sensing position. The switches 8 FLl and FL2 can be connected through remote signal connector 70 9 to a remote panel to activate an indicator signal in the event that either of the switches FLl or FL2 becomes closed. In a 11 similar manner, forms out switches F01 and F02 are positioned 12 to sense the presence of the backing plate 434 at an even more 13 forward position at which the proper feeding of currency 430 14 can no longer be assured. The switches F01 and F02 are connected to activate bit 06 in the status sensing circuitry 344 in the 16 event that either of the two switches is activated.
17 The bill feed mechanism 422 includes a separator belt 18 444 and a restraint belt 446. The separator belt 444 is posi~
19 tioned at the forward most end of the hopper 420 in contact with the forward most bill and driven in a direction to urge ;~
21 the forward most bill downward toward the document transport 22 mechanism 424. While the belt 444 is urging a bill downward, ~ -~ ~, 23 the restraint belt 446 is positioned beneath the hopper 420 on~b 24 an opposite side of a bill feed path and driven in a direction 25 tending to urge bills back toward the hopper. ~he coefficient `-~
26 of friction of restraint belt 446 is selected such that the ~ ~ .
27 friction between belt 446 and a bill is greater than the friction ..
. 28 between two bills. Similarly, the coefficient of friction for 29 belt 444 is selected such that the frictional forces between ~, 30 belt 444 and a bill are greater than the frictional forces ``'' ` '' SA974017 -33- ;
; ' '`:
" , ,;i :~

1~64621 1 between belt 446 and a bill. Thus, as a bill passes between 2 the two oppositely directed belts 444 and 446, the greater ~-~
3 frictional force e~erted by belt 444 causes the bill to be ~-4 moved downward toward the document transport mechanism 424.
However, should two bills be simultaneously urged downward by 6 belt 444, the frictional force exerted by restraint belt 446 -7 causes all except the bill which is in direct contact with 8 belt 444 to be retained in the hopper 420. ~-~
9 Once a bill is issued by the feed mechanism 422 and `~
reaches the transport mechanism 424 it is moved at a more rapid 11 speed toward the stacker wheel 247, 248. In order to insure 12 proper engagement of a bill within the tines 260 of the rela- `~
13 tively slowly rotatin~ stacker wheels 247, 248 the bill feed 14 mechanism 422 must be activated in synchronism with the stacker -15 wheels 245-248 such that the stacker wheels are in the correct "-16 position for receiving the bill. ~or this reason photo sensor ~
17 264 responds to light signals passed through the indexing wheel :
18 266 to generate a document feed enable signal DFE at the 19 proper time for initiating a document feed command.
As shown more particularly in F~g. 4, AND gate 252 21 ~eceives the document feed command from bit position A7 as 22 well as the document feed enable signal (DFE). The output of "` ~;
23 AND gate 252 is used to set a latch 253 which in turn is connected 24 to the driver which controls the feed clutch. The document 25 feed clutch 236 is thus energized at the proper time to cause ~
26 a bill to reach the stacker wheels 247, 248 while they are at ~-27 a proper position to receive and decelerate the bill. A first ;~`~
28 PCl photocell 450 is positioned near the document feed mech~nism 29 422 to sense thè release of a fed bill. Bit A7, the clutch `
activation command signal, is immediately reset to terminate SA974017 -34~ ;

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. ,. , . ,: . ~

:
~64~;Z~ :

1 the further feeding of bills. Because belts 452 and 454 2 within the document transport system travel at a much higher 3 rate of speed than the belt 444, a first bill is assured ot ~;
4 reaching PCl photosensor 450 before a second bill can be fed.
a second photosensor (PC2) 456 is positioned a distance which 6 is slightly greater than the width of a bill downstream from - ., 7 sensor PCl. If two overlapping bills should somehow escape 8 the document feed mechanism 422~ both sensors PCl and PC2 would 9 be activated simultaneously to indicate an error condition. A
photocell PC3 is positioned at the terminal end of the document 11 transport mechanism 424 near the stacker wheels 447, 448.
12 Activation of cell PC3 thus indicates the completion of a bill . ~:
13 feed step. The failure of a bill to reach photocell PC3 also 14 indicates a jam or other error cond:ition. Sequence checks are ;~
executed to insure that a bill passes PCl, PC2 and PC3 in the 16 correct order. An incorrectA order would be an indication tha~
17 two bills have been fed, or that some other error condition ;-18 has occurred.
; . .~
19 Upon reaching the stacker wheels 247~ 248 a bill is -engaged by the tines ~ the stacker wheels and decelerated to 21 permit orderly stacking as the tines rotate countèrclockwise.
` 22 This counterclockwise rotation causes the lower edge of a : .
23 document to engage a stacking surEace 460 so that the document~ -24 is stacked in a vertical orientation as it is removed from the ~
- :~
tines. As the stacker wheels 247, 248 continue to rotate in ,~ 26 a counterclockwise direction, the other surface of subsequent `
27 tines engaged the document in sliding relationship to maintain . 2~ it in its vertical position and in contact with a transport ;~
29 belt 462 of escrow transport mechanism 382.
The escrow transport mechanism which is best shown in ;
..
~ SA974017 -35--, , ' "

~069~6Z~ :

1 Fig. 6, includes the belt 462 which defines an escrow transport ~,~
2 path, the clamping mechanism 234, the reiect bin 230 and a belt , 3 drive system 480 for bel~ 462. The escrow transport syste ~ ,~
4 has two stacking stations 482, 484 at which documents are stacked in a predetermined vertical orientation adjacent the 6 pairs of stacking wheels 247, 248 and 245, 246, respectively. ,, ~ - 7 The two stacks 482, 484 are sequentially formed with a first 8 orderly stack being Eormed at stacking position 482 by the 9 receipt of bills from document feed mechanism 240 and printed ;' 10 transaction statements from transaction statement printing i ~,~
11 mechanism 250. Upon completion of first denomination issue a 12 solenoid 486 responds to bit A3 to control the position of the 13 clamping mechanism 234. During the receipt of documents into 14 a stack'at either position 482 or second position 484, the ~, clamping mechanism is deenergized by a 0 in A3 and is thus moved 16 to a retracted position so t~at the pressure rollers 488 are ' 17 moved away from the drive belt 462 toward the axes of rotation ''' 18 490 for the stacker wheels 245-248. After the formation of the ' ;'~
19 first stack at position 482 by the orderly depo~it of bills ~`
.~ ~ . ..
and transaction statements in a,vertical orientation against '~
21 the belt 462, the clamping mechanism 234 is moved to a clamping ' -22 position wherein the first stack is constrained between the ' ;"~
23 pLessure rollers 488 and drive belt 462. After the first ~`h, "' i ' 24 stack has been clamped the belt drive mechanism 480 is activated `,~
25 to move the belt in a counterclockwise,~directio-n to transport, ,i ' `
26~ the first stack toward the second stacking position 484. Upon 27 arrival of the first stack at the second stacking position ,'~
28 the drive belt as sensed b~ an issue switch SWl whose output 29 is communicated to bit 00, the belt 462 is stopped with the first stack at the second stacking position 484 opposite stacker ,,~
.~ ~,, .
SA974017 -36 ~`

: . . . . . . , . . ,,; . , , -1~646;~
1 wheels 245, 246. Upon arrival of the first stack at the 2 second stacking position 484 the clamping mechanism 234 îs 3 moved to a release position and a second stack is formed by 4 the orderly addition of bills from the second document feed mechanism 242.
6 Upon completion of the second stack, the clamping 7 mechanism 234 is again moved to the clamping position and -8 the belt 462 is moved to carry the second stack toward a docu~
9 ment issue slot 492 which provides communication between the interior and the exterior of the terminal 10. A closure gate 11 494 is mechanically coupled to a solenoid 496 which becomes 12 activated to move the closure gate 494 from a closed position 13 498 to an alternate open position 500 in response to the 14 activation of a document escrow transport mechanism drive lS motor 502 in a direction which causes a stack to be moved 16 toward the slot 492. As soon as the second stack clears cash 17 issue position 504 as sensed by switch SW 1 closing, the escrow~
18 transport mechanism is deactivated and the second stack is 19 retained at the document iss~le position 504 with the ~orward portion of the stack extending through slot 492 and the rear~
21 ward portion of the stack in frictional engagement between the`
,~
22 belt 462 and a clamping roller 506 which is the forward most 23 clamping roller 488 mounted on clamping mechanism 234. As 24 soon as the escrow transport drive motor 502 is deactivated, the solenoid 496 is also deactivated causing the closure bar 26 494 which is lightly biased toward the closure position to 27 bear against the combined second stack of documents in an issue -~
28 position 504. Upon removal of the combined stack of documents ;, . .
29 by a user, the closure bar 494 continues to move to the closed ~ `~
;~ 30 and locked position 498 and is sensed by a switch 508 as the SA974017 ~ _37_ ~ ' '.

". :; ., , . . ~ , . . ~ , . . . . . . .

~)6~6~
1 locked position 498 is reached. The output of switch 508 is 2 communicated to bit 25 of the mechanical control subsystem 3 status sensing registers for feedback to the microprocessor 72.
4 As an alternative to the previously described method of dual denomination issue, whereby documents from the first 6 issue mechanism are fed first, the transaction statement is 7 added second and the document from the second issue mechanism 8 is added third, the statement printing could be first started 9 and continued concurrently while documents are issued from the 10 second issue mechanism, transported back to the first stacking ~ ;
11 position, and supplemented by documents from the first issue 12 mechanism. Finally, the printed statement can then be added 13 when available. The combined stack would then be issued to the 14 user. The closure gate 500 would then we opened when the escrow 15 transport is activated to run in a forward direction toward ~ ~ ~
16 the document issue slot. ~ -~: , 17 In the event that a sequence error, a bill overlap ~
. .:,, 18 or other error condition is detected while documents are being - ~
.:
19 stacked at one of the stacking positions 482, 484, the terminal is able to recover by transporting all previously stacked docu-21 ments to a reject bin 230 and reinitiating the entire document - 22 issue operation.
. ...
; 23 The drive mechanism for the belt 462 includes a drive `~
24 capstan 510 which is coupled to drive motor 502, a turn-around -~
roller 512 positioned at the forward end of the escrow transport 26 path opposite pressure roller 506, a plurality of path defining -~;~
. .~. ,: . . , 27 rollers 514 which are positioned to guide belt 462 between . 28 capstan 510 and turn-around roller 512 to constrain the belt 29 462 as it extends along a generally straight portion of the ^
escrow document path between capstan 510 and roller 512. A pair :, ,~' ;. ' SA974017 -38- ~ ;
. ;:.'.:

~Q646Z~L

1 of guide rollers 516, 518 g-lide the path of belt 462 2 past the reject bin 230. An idler belt 520 is wrapped part 3 way around capstan 510 to form a circular cornering path for 4 the document escrow transport path.which causes rearwardly ~:
moving documents to undergo an approximately 180 turn before 6 entering the reject bin 230. Rollers 522, 524 and 526 along 7 with capstan 510 define the path of the idler belt 520 to permit :~
8 documents to be clamped between idler belt 520 and transport . ~:
9 belt 462 as they turn the circular corner. Thus, if an error 10 condition or transaction cancellation condition is detected . `:
11 before the issuance of documen~, the motor 502 is activated to ..
12 drive belt 462 in a reverse direction to cause documents to be -~
13 moved through the circular corner while clamped between belts 14 462 and 520 to the reject bin 230. An escrow switch ESCSW2 is ;
positioned to sense documents moving along the escrow transport 16 path adjacent the reject bin 230. The completion of a reject ~:
17 operation is presumed when the transport belt 462 has continued. :
18 to move in the document reject direction for a predetermined `
..
19 period of time following the movement of docum~nts past switch ESCSW2. The output of ESCSW2 is communicated to bit 01 for 21 detection by the microprocessor 72. The activation and direction ..
22 of operation for the motor 502 is controlled by a pair of ;~
23 relays 530, 532. The motor 502 is a conventional capacitor 24 phase shift two phase motor connected for bidirectional . :
operation in response to the application of AC.power to one of 2~ the two winding inputs by relays 532 and 530. Relay 532 is .~
27 connected to control the direction of drive motor 502 rotation .:~ .
28 by energization of terminal 536 to cause drive motor 502 29 to rotate in an escrow reject direction in response to a one at. :~
, 30 driver bit position bit A0 and to rotate in an escrow issue ~.
J

~.

... .

~ G4G2~

1 direction upon energizatlon of terminal 534 in response to a 2 logic 0 at driver bit A0. ReLay 530 responds to a logic 1 at 3 driver bit A2 to turn the escrow motor on and a logic 0 at 4 driver bit A2 to turn the escrow motor off. ~ ;
Error detection logic and motor control circuitry for 6 the document handling mechanism is shown in Fig. 7. The three 7 photocells along the document transport path for the first docu-8 ment feed mechanism 240 are indicated as PCl, PC2 and PC3 while ;-9 the corresponding photocells for the second document feed mechanism 242 are indicated as PC10, PC20 and PC30 respectively.
11 A sensor 540 senses the activation of the clutch mechanism for 12 the first document feed mechanism wh:ile a sensor 54~ senses the 13 activation of the clutch mechanism for the second document feed :
14 mechanism 242. Driver bit A5, which selects the second document ;~ 15 feed mechanism 242 when at logic l,and its complement A5 are 16 utilized to multiplex the sensed document issued mechanism ~; , .~ .
17 status signals to make the document Eeed mechanism sensed feed~
18 back bits 03, 0~, 05, B.SoO and B.S.2 responsive to the selected 19 document feed mechanism. An OR gate 544 generates a signel which activates bit 05 as well as a reset signal RSTBA7 which 21 resets driver bit A7 to deactivate the selected document feed .,. . ~::: :
22 mechanism as soon as the presencè of a bill is sensed at the 23 first photocell of the selected document feed mechanism. It iS,h "~' '', 24 the signal RSTBA7 which causes the selected clutch to be -25 deactivated prior to the feeding of a second bill. An OR gate ~ ;~
26~ 546 generates a bit 04 signal upon sensing the presence of a :.... . . .
~ 27 bill at the second sensor of the activated document f.eed ;; ~
, .
.28 mechanism. An AND gate 548 generates an overlength signal, O.L., r~,, ''",,' 29 in response to the simultaneous interruption of light to photocells one and two of a selected document feed mechanism as indicated by -;' .

106~62~

1 the concurrence of signal bit 05 and bit 04. An OR gate 550 2 is connected to generate a parallel feed error signal, PFE, 3 in the event that ligh~ to any of the three photocells in the 4 unselected document feed mechanism are interrupted while the ~-other document feed mechanism is selected by bit A5. Such an 6 interruption would indicate the improper feeding of a bill from 7 the unselected document feed mechanism.
8 A sequence error detection circuit includes a flip 9 flop 552, AND gates 554, 556, and an OR gate 558 which responds ;~
to the outputs of AND gates 554, 556 to generate a sequence ; - .
11 error signal. Flip-flop 552 is connected to be reset whenever ~ ~
12 the bill feed command bit A7 is off and set whenever a bill - ;
13 passes the second photocell of a selected document feed mechanism.
14 If a bill passes the three photocells in the proper order, AND `;
~ - 15 gate 554 is disabled by the Q output of flip-flop 552 as the ```
- 16 bill passes photocell one and an AND gate 556 is disabled by .. ..
17 the ~ output of the previously set flip-flop 542 as the bill "~ 18 passes the third photocell. If a bill passes photocell 2 before .
~ 19 photocell 1 or photocell 3 before photocell 2 as might happen :~ 20 if a second bill is issued before a previous bill-reaches the 21 stacker wheels, a sequence error signal is generated by OR
22 gate 558. An OR gate 560 is connected to indicate the presence j 23 of a bill at the third photocell PC3 or PC30 of the selected `" 24 document feed mechanism by the generation of an output signal bit 03 and DFMPC3. The document transport motor 455 which ~ 26~ drives the document transport belt 452 of the first and second :~' . ~.. -;
.~ 27 document feed mechanism, the stacker wheel motor 244 which : . 28 drives the stacker wheels 244-248 for the first and second docu-29 ment feed mechanism 240, 242, and the printer motor 397 which 30 drives the print wheel and transport mechanism for the printer ^~
:'` . ' ...... ~' ' SA974017 ` -41- ~ ~

. ~: . ; , ~ , , . . . . ~ . .. . . : . ... .;

~ 46;~ :

1 mechanism 250 are also driven in common by a relay 562 which 2 activates the three notors in response to a logic 1 at driver 3 bit A6. ; ?
4 As shown in Fig. 8, the deposit mechanism includes a slot 570 through which an envelope containing deposit documents 6 may be inserted, a transport mechanism 572, and a deposit bin 7 574. A door 278 across the interior wall through which the 8 slot 570 extends is normally locked by a latch 572 but is free -~
9 to pivot about an axis 574 in response to the insertion of a document through slot 570 when latch 572 is in a raised position.
11 A solenoid 580 is connected to raise the latch 578 to an open -12 position in response to the activation of deposit transport `
13 motor 276. The solenoid 580 and the motor 276 are in turn `~
14 connected for activation by a relay 582 in response to the turning on of driver bit B4. Thus, as bit B4 is set to logic 1, 16 the latch 578 is raised to release the door 278 and the transport 17 mechanism 572 is turned on to receive and frictionally engage ;
. ~ .
- 18 any document whlch is inserted through slot 570. A switch 584 19 is positioned to sense the presence of latch 57~8 in t~e locked ~ ~`
position with the output thereof being communicated to bit 25 `~
:.
21 of the data register.
22 The depository transport mechanism 572 includes three 23 idler rollers 586, 588 and 590 positioned along the depository~
24 document path, a belt 59Z defining the depository document path, `~
and a capstan 594 connected to the drive belt 592 along the 26 depository path in response to the activation of motor 276. `
27 Pressure rollers 596 are positioned opposite the belt rollers 28 586, 588 and 590 on the opposite side of the deposit document 29 path from belt 592 to constrain deposited documents to the depository document path. ~n insertion switch 598 i5 positioned ;~
~;
SA974017 ~ -42-.- ~.

.~, . . . . . .. . . . . .

10646Z~ -1 at the forward end of the depository document path in the 2 vicinity of roller 586 to sense the insertion of a document 3 through a slot 570 and past the door 278. The output of 4 switch 598 is conveyed to data input position bit 26. A
second sensor switch 600 is positioned at the terminal end of 6 the depository document path adjacent the depository bin 574.
7 The output of switch 600 is connected to data input position 8 bit 27 to permit detection by microprocessor 72 of the presence --9 of deposited documents at the end of the depository document path. Microprocessor 72 can be assured that documents have 11 entered the depository bin 574 by maintaining the depository `~
12 transport mechanism 572 in an active status for a predetermined 13 period of time after the passage of documents beyond sensor 600 14 has been detected. Depository 274 thus provides a secure means -;
for receiving deposited documents having a first protection 16 door 278 which is automatically latched by the deactivation of 17 solenoid 580 in the event of a power failure. The depository 18 mechanism 572 may be completely controlled by the receipt of 19 simple control commands from the microprocessor 72 by the driver register of the mechanical control subsystem 61.
. ..
21 The credit card handling mechanism 226 is shown in 22 Fig. 9 and includes a card insertion slot 610, an open/close - -~
23 sign 612 illustrated in the closed position, the blocking roll~er 24 272 and a transport mechanism 614. When the terminal 10 is open ;~
to receive transaction requests from a user, a logic 1 is set 26 in driver position bit ~3 to activate solenoid 64 and cause the `;
27 rotation of sign 266 in a clockwise direction about axis 616.
28 As the sign 266 rotates about the axis, a "closed" sign is 29 rotated upward beyond the view of a window 618 and an "open" -word is rotated into the field of view for window 61 S~974017 _43_ . , `.

.

1~6~62~ ;

1 Simultaneously, a drive link 620 couples the sign 266 to latch -~
2 26~ to rotate latch 268 about an axis 622 to an open position 3 in which the blocking roller 272 is permitted to rise upon 4 insertion of a credit card 270 through the entry slot 610. The 5 credit card transport mechanism includes a belt 624 which is .
6 maintained in tension about credit card path defining rollers .
7 626, 628 and 630, idler rollers 632, 634 and a drive capstan 636.
8 The belt 624 is diverted to engage capstan 636 as it passes .;~
9 between rollers 628 and 630. The credit card path is defined .~ :~
by rollers 626, 628 and 630 which are driven by belt 624. Belt 11 624 passes adjacent the credit card path between rollers 626 . ~ .
. . .
~ 12 and 628 but does not define credit card path. Drive capstan 636 :: ..
. . ~. :
13 is coupled to a credit card transport drive motor 638. Positioned .
~ 14 adjacent the path defining roller 626, 628 a~d 630 are three , 15 pressure rollers 640 disposed on the opposite side of the credit 16 card transport path thereof for the purpose of constraining .~
17 an inserted credit card to the credit card transport path. A i` ~ ~ :
18 switch 642 having the output thereof connected to data sense 19 position bit 10 is disposed at the forward end.,of the credit `~
~: 20 card transport path to sense the insertion of a credit card 270 ;
21 through the slot 610 or the removal of a credit card 270 from 22 the slot 610 at the completion of a requested transaction. ~ :
23 A read head 644 is positioned along the credit card transportr.g ..:~
24 path to read information stored on a magnetic stripe of a .
25 credit card 270 as the card is transported beneath the read . :~
26 head 644. The output of read head 644 is communicated to read 27 data logic within the processor support subsystem 60 for 28 processing prior to communication. to the data processor 72 - -29 through processor support subsystem 60. A switch SW2 646 is 30 disposed along the credit card path approximately midway between ~
,' ~ ' ,:

,. .
SA974017 44~
:' '.

. .

~()6~

1 rollers 626 and 628 to sense the passage of a credi~ card 2 through ~he slot 610 and out of the control of a user.
3 A sensor 648 is positioned at the rearward end of the 4 credit card transport path to detect the arrival of a card 270 at a card escrow position after it has passed beneath read head 6 64 and to detect the passage of a retained credit card to the .
7 end of the credit card transport path prior to the deposit of 8 a retained card into a retention bln 650. Insurance of the 9 depositing of a retained card into bin 650 can be realized by :
maintaining the credit card transport mechanism active in a 11 credit card retention direction for a predetermined period of 12 time following the passage of a credit card beyond switch 648. .
13 The output of switch 648 is communicated to data assembly 14 position bit 1 15 Credit card transport drive motor 638 is a capacitor ;~
16 phase shift two phase AC motor which may be selectively driven 17 in either of the two directions of rotation by selectively .
:
18 activating one of two input terminals thereto under control 19 of a relay 654. Relay 654 is responsive to dr~ver position 20 bit A0 and causes the motor... 638 to move a credit card into :~
21 the terminal when set to logic 1 and move a credit card toward 22 the slot 610 when set to logic 0. A relay 656 is connected ..
23 in series between relay 654 and an AC power source to activate~ ~
24 the motor and the selected direction in response to a logic 1 . . ~ :.
.25 at driver position bit Al. The open sign 266 and credit card ;. .
26 transport mechanism 614 are thus controllable by the micro- ~
27 processor by the selective loading of data into the driver ~.
28 registers 216, 218 and 220 of the mechanical control subsystem 29 61.. All branching or decision making functions for the credit card handling system 226 are thus retained by the microprocessor 72 1~6~6;~ ~

1 while the actual execution of commanded func~ions is perormed 2 by the control mechanism subsystem 61 in direct response to 3 specific microprocessor commands.
4 Referring now to Fig. 10, the control mechanism for 5 the user panel door 16 is shown as including a lever arm 660 ~
6 which extends from a pivot axis 662 at one end thereof to the ,?
7 door 16 where the opposite end is connected to door 16 by 8 a slot 664 which receives a pin 666. The door 16 and lever 9 arm 660 are shown in primary closed position. The door 16 is ;~
,~ 10 mechanically coupled to a damping mechanism 660 which is , 11 schematically represented by damper 668 and is also connected ' ~ ' ~. :
12 to a spring 670 which urges the door 16 downward to a closed 13 position.
~' 14 A latching mechanism 674 includes a drive link 676, `' . . .. .
a closed latch 678 and an open latch 6800 The drive link 676 i,.~, ..
`~ 16 includes a lower slot 682 and an upper slot 684. The lower ,~
~ 17 slot 682 is engaged by a pin 686 on a'horizontally extending -,. ~ . . :. .
- 18 lever arm 688 of latch 678. Latch 678 is mounted to pivot ','~
; 19 about an axis 690 which extends generally parallel to the liEt ,,~
, 20 bar 660. A latching arm 692 of latch 678 extends generally ;~ 21 downward and toward the lever arm 660 at an oblique angle , ,, ' ; 22 with respect to horizontally ext`ending lever arm 688. The ` -~
23 open latch 680 includes a lever arm 696 which exten'ds generally, ;,~
,,(~ 24 horizontally from a pivot axis 698 extending generally parallel `~' ' 25 to lever arm 660 and a latching arm 702 which extends generally ,'~`
26, upward toward the path of motion of door lever arm 660 from ''~
27 axis 698 at an oblique angle with respect to lever arm 696. "'~ ~ , '; ~ 28 A pin 700,, which is mounted on lever arm 696, engages the upper ', 29 slot 684 of drive link 676.
: ~ ~
The drive link 676 is coupled to a solenoid 704 '',- ~

.: :. .
' SA974017 ~ -46- , ' , .

-. :

~6~6Z~L

1 which moves the drive link 576 vertically upward when 2 energized. ~ spring 706 pulls the drive link 676 vertically 3 down~ard when the solenoid 704 is not energized. A spring 708 4 is connected to bias the lever arm 688 of latch 678 downward while a spring 710 is connected to bias lever arm 696 of latch 6 680 vertically upward.
7 The door 16 and lever arm 660 are movable between 8 two extreme positions as the lever arm rotates about the 9 axis 662. The door 16 and arm 660 are shown in a down or :
10 closed and locked position with an alternate open or up and ~-11 latched position being indicated for lever arm 660 by dotted ~;
12 outline 712.
13 In the down and locked position in which the door 16 14 and lever arm S60 are shown, any attempt to raise the door 16 will exert a torque on latch 678 tending to rotate the latch 678 16 in a clockwise direction about the axis 690. However, ~he 17 pin 686 engages the bottom of lower slot 682 to oppose this 18 rotational torque. At the same time~ the pin 700 on lever 19 arm 69 engages the upper end o~ upper slot 684 causing drive 20 link 680 to rotate clockwise~about axis 698 to remove latching~ - -21 arm 702 from the path of motion of lever arm 660. Thus, while ~ `
22 the drive link 676 is in the lowèr or locked position as shown, ;
23 the latching of the lever arm 660 in the upper position 712 iS-'s `
24 disabled and the latching of lever arm 660 in the closed . . . ~ .:
25 position is enabled. ~ -26 Upon energization of solenoid 704, the drive link 676 ,~ .
27 is moved vertically upward to an open, unlocked position. In . 28 this position thelower end of lower slot 678 engages pin 686 29 to rotate latch 678 counterclockwise about axis 690 to remove latching arm 692 from the path of motion of the lever arm 660, ;,, SA974017 ~ -47- ~

~ .

, , ~, . . . .. . . ...
.. : . . ~ , .,; . . , . ,:: .

: ~L064623 ; 1 permitting the door 16 to be raised without interference. ?
2 At the same time, the open latch 680 is also permitted to 3 rotate counterclockwise about axis 698 with the latching ; 4 arm 702 being rotated into the path of the lever arm 660 with 5 the pin 700 engaging the top of slot 684 to prevent further .-~ :, .
6 counterclockwise rotation of lever arm 680 about axis 698. -7 As the door 16 and lever arm 660 are raised toward alternate i 8 position 612, the top 718 of lever arm 660 engages an angular 9 planar surface 720 of latching arm 702 causing latch 680 to ~ ~
10 be rotated clockwise with pin 700 moving downward in the ~ -11 upper slot 684. As the lever arm 660 moves past the latching 12 arm 702 to the open position 712, latching arm 702 is permitted 13 to snap baclc into the path of the lever arm 660 under the bias 14 of spring 710 to prevent the lowering of lever arm 660 and maintain arm 660 in the open position 712.
16 Upon termination of power to solenoid 704, whether 17 on command or as the result of a power fail~e, spring 706 18 returns drive link 676 to the vertically lowered or lock :~. ,,. ~, ....
19 position in whick it is primarily shown in Fig~ 10. As drive-link 676 moves vertically downward the pin 700 engages the top 21 of slot 684 causing latch 680 to rotate in a clockwise direction ~ ;
22 to remove the latching arm 702 from the path of motion for the 23 door lever arm 660. Door 16 is thus permitted to fall to a 24 closed position in a controlled manner under the influence of `~
spring 670 and damper 668. As the lower edge 722 of door lever 26 arm 660 approaches the closed position which is shown, lower 27 surface 722 engages an angular planar surface 724 on latching 28 arm 692 causing the arm to be rotated counterclockwise out of 29 the path of door lever arm 660 as the pin 686 rises within slot 682. After the upper surface 718 of door lever arm 660 clears '' " :

' , ~L~691~

1 the latching arm 692, latch 678 rotates under the influence 2 of spring 708 to bring latching arm 692 back into the path of 3 lever arm 660 and lock the door 16 in the closed position.
4 Latching mechanism 674 is thus a fail safe device which permits the door 16 and door lever arm 660 to be latched in an open 6 position 712 so long as solenoid 704 is energized but which 7 automatically locks the door in a closed position in the event ~'-8 of a power failure. -9 A control circuit permits a logic 1 at driver relay ~-register bit B0 to command a door open position and a logic 0 at 11 position B0 to command a door closed position. A door control 12 motor 728 has coupled thereto a first cam 730 having a rotating 13 bearing 732 eccentrically positioned thereon, A~so coupled to ` ~-14 motor 728 is a cam 734 having a concavity 736 therein which 15, extends over a small portion of the circum~erence of cam 734.
16 ~ cam follower 738 rides the cam to control the position of a ~' 17 switch 740 which is shown in a down position 742. A relay 744 18 responds to driver bit B0 to control the position of a switch `
., - ~,.
19 746 which is illustrated in a down position 74 The relay 744 responds to a logic 1 at driver bit B0 ~ -~
21 by changing switch 746 to an alternate door open position 750.
'~22 With the switch in position 750 `the solenoid 704 is activated :
~ 23 to move the latching mechanism 674 to a door open position, ' ~s -, 24 Simultaneously, the motor 728 is energized to rotate arm 730 ',' in a clockwise direction. As arm 730 rotates,the bearing 732 ' 26 engages the lower edge 722 of door lever arm 660 to raise the 27 door lever arm 660 and door 16 to the alternate open position -. 28 712 where,the door lever arm 660 is held open by latch 680 as ,'' J. ; . ~
29 previously explained. The cam 730 and bearing 732 then continue to rotate through a nearly complete revolution to ' ~:
. : . , ,, ~

1~6462~L ~
1 alternate position 754. Cam 734 rotates in a counterclockwise 2 direction concurrently with cam 730 with the cam follower 738 '~
3 engaging the outer circ~nference of cam 734. As the cams 730, ' ~' 4 734 approach one complete revolution, the follower 738 engages ,~ ~
a leading edge 756 of the cavity 736 on cam 734. As the cam ~ ~' 6 follower 738 moves radially inward following edge 756, the snap -` 7 action switch 740 is switched to an alternate position 758 to 8 terminate power to the motor 728. As this switching action 9 occurs, the cam follower 738 is in engagement with leading edge 756 of concavity 736 and cam 730 is in alternate position 754.
.. ~ ,. .
11 The door mechanism remains in this condition so long as a 12 logic 1 at bit B0 commands an open condition for door 16. ,~
13 Upon termination of the open command, relay 744 ' ', 14 returns switch 746 to position 748 to deenergize solenoid 704 `~
15 and cause the door lever arm 660 and door 16 to fall to a closed ,~ , 16 and latched position as previously explained. At the same time, ",i~' ~-,,, 17 switch position 748 causes motor 728 to be energized through 18 switch position 758 of switch 740. This energization causes ';
19 the motor 728 to begin rotating in a clockwise,~direction. As ,~
,.
'; 20 cam follower 738 engages the trailing edge 762 of concavity 736 ' ',~
,~ 21 it begins to move radially outward to return switch 740 to the, , ' ', 22 position 742 in which it lS shown. At this time the cam 730 23 has rotated to the position at which it is shown, and furthér~
24 energization of motor 728 is discontinued. The door mechanism - ,~
25 is now in position to be reopened in response to a logic 1 , ` 26 signal at driver register bit B0. ;'~ -' 27 User Communication Subsystem -~
. 28 ' Referring now to Fig. 11, there is shown the user '', 29 communication subsystem 62 which operates to control the keyboard '', 30 22 and optical guidance display 24. The portions of subsystem 62 ;~
,, ' , SA974017 ' -50- ',, , ' ', ~L~646;~
,,..
l which are common to each of the subsystems 60-64 include bus 2 interface logic 770, interrupt request flip-flop 772, command 3 decoder and latches 774, and roller gate 776 which ORs 4 the terminal reset signal with the commanded subsystem reset signal ADRST to generate reset signal RST. These common 6 elements operate as described in conjunction with processor 7 support subsystem 60 and mechanical control subsystem 61 except 8 that the command signals which are decoded and latched may be 9 peculiar to the user communication subsystem 62. These common 10 elements of subsystem 62 will therefore not be further ;
11 described.
; 12 Key scan and detection logic 778 operates by incre-13 mentally scanning column input lines to keyboard 22, while 14 sensing row output signals. Whenever an activated key is scanned by the column scan mechanism the scan signal is communicated 16 through the key to a row signal which is detected by the key 17 scan detection logic 778. Upon detection of a row signal by r'.`~ 18 the key scan and detection logic 778, an attentlon signal is !,', 19 generated which sets the interrupt request flip-flop 772. The ;~
`~ - 20 microprocessor 72 processes the interrupt request by generating 21 a read keyboard command whlch is latchèd and gated at the data 22 time to cause key scan and detection logic to gate onto the -23 data bus 777 a signal indicating the column which was being ;~
24 scanned when the row signal was detected and the keyboard row ~-`
.; ~
on which the signal was detected. The microprQcessor 72 is ' 26 thus able to determine the exact key which was activated and ~ -27 respond accordingly. ;
, 28 The code assignments for indicating the activation i :~ 29 of keyboard keys are given as follows by hexidecimal code, 30 row position, column position and designation: -~
, '~ ' SA974017 ~ -51~
;, , :.
~646Z~

1 00 Rl C8 Cancel .
2 03 R4 C8 Proceed .
, : . .
3 04 Rl C7 Key 3 4 05 R2 C7 Key 6 06 R3 C7 Key 9 :
6 07 R4 C7 Decimal Point. As an option, .
7 this key may alternatively repre~
8 sent triple zero, ''0.00". ~ ~ .
9 08 Rl C6 Key 2 ~ .
09 R2 C6 Key 5 11 OA R3 C6 Key 8 :
12 OB R4 C6 Key 0 -13 0C Rl C5 Key 1 ^~
14 0D R2 C5 Key 4 OE R3 C5 Key 7 i 16 OF R4 C5 Correction 17 10 Rl C4 TO CHECKING
18 ~ 11 R2 C4 TO SAVINGS
19 : 12 R3 C9 TO CREDIT CARD
13 R4 ~C4 . TO SPECIAL ACCOUNT (optional 21 : selection) ;'~ :~
22 14 Rl C3 FROM CHECKIN~
23 15 R2 C3 FROM SAVINGS r~
24 ~ 16 R3 C3 ~ FROM C Æ DIT CARD
17 R4 C3 FROM SPECIAL ACCOUNT (optional 26~ ~ selection) 27 18~ Rl C2 DEPOSIT

29 llA R3 C2 PAYME~ BY TRANSFER :
lC Rl Cl :WITHDRAW (cash issue) SA974017 -52~
, ~06~62~ ; :

1 lD R2 Cl OTHER (optional selection) 2 lE R3 Cl ACCOUNT INQUIRY
3 lF R4 Cl TRANSFER ;
~ 4 The backlights of the drivers of the keyboard 22 are `~
-~ 5 connected to individual backlight drivers 780 in a one to one 6 relationship. The backlight drivers 780 are in turn connected ; 7 to backlight registers 782 in a one to one relationship. The ; 8 backlight registers 782 include three 8 bit registers designated 9 A, B and C. Three command control signals, load A, load B ;~
.~. .
and load C, permit the selection of one of the three registers 11 for loading in accordance with information appearing on data ~ ~ -; 12 bus 777 as the load command is generated at data time. The ~ ~;
13 reset command clears all three registers to turn oEf the back- `
14 lights.
.. ..
The data bit assignments for register 782 are 16 sumarized as follows:
17 AO Withdraw light 18 Al Other light (optional selection function) -~19 A2 Account inquiry light A3 Transfer light 21 A4 Deposit light --~
22 A5 Payment by deposit light ~ -23 A6 Payment by transfer light . à
24 A7 Not implemented BO From checking light 26 ~ Bl From savings light 27 B2 From credit card light 28 B3 From specialaccount light ~optional selection) : , ; 29 ' B4 To checking light `
B5 To saving~ light ''; , '' ~' "
SA974017 -53- ;~
.. . .... .
.",: ' :
`: :

:. . .. . . .. . .

1~)64~21 1 ~6 To credit card light , 2 B7 To special account light (optional selection) ,~
3 Cl Test. This bit causes key scan al~d detect logic , 4 778 to respond as though the transfer key had '`~
'', 5been activated.
. ..
, 6C2-C6 Not implemented ,'~ 7 C7 Audio tone which is generated by a conventional 8 tone generator (not specifically shown) as a '~
:.. , , :
~; 9 user feedback signal upon activation of a key~
,~- 10 board 22 key.
11 The control circuitry for the 222 by 7 dot display 24 '~
. ~
12 includes a display driver 790, a gate 792, display buffer 794, 13 and address counter 796, a column counter 798 and display control '',`' 14 logic 800. Dot display 24,'while :it is in operation, is con-tlnually refreshed as columns of information are s~equentially 16 read from display buffer 794 and gated through gate 792 to - ;, ~, 17 activate display driver 790 to selectively turn on display dots; ,~
18 at~columns indicated by column counter 798. As the display~is 19 refreshed, address counter 796 and-column coun,ter 798 are~
sync;hronously~incremented by simultaneous step commands so that'~
21 address counter 796 addresses a storage location in display Z2 buffer 794 whlch corresponds to'"the current column~counter, 23~address signal 798. A reset~signal is generated by display r~S i'~
24 control logic 800 at the end of each refresh~"scan" to reset 25~ the address counter~796;and column counter 798,and thus~allow , ~,,;
2~ a new refresh cycle to start. These reset signals are also 27 generated in response to the subsystem reset signal RST which '~
28 also~causes a blanking of~the display. Control commands for the '','~
29 display control system~include a write data command which causes 30 data appearing on the data bus line 77 to be written into the ''~

' ' ~
; '' SA974017 -54- " ~

.: , , : , , ~646Z~

1 display buffer 794 starting with address ~ on the first 2 write command following a blank command and causes address 3 counter 796 to be incremented by a s~ep command upon termination 4 of the write data command. A display command causes the display 5 of the information stored in display buffer 794. Similarly, ~-6 the blank command causes the termination of the display of 7 information stored in display buffer 794. Display buffer 794 8 contains 224 addressable 8 bit storage locations with the 9 first address location and the address location following the 10 last address location containing display information being ll controled address locations. If all column locations for the ; ~
12 dot display are being utilized, this last display location -13 would occur at address 224. In general, however, this last 14 display location may occur at any acldress position~ depending 15 upon the length of the message being displayed. Bit position 0 16 is utilized for control information and bit positions 1 through `~
17 7 are operative to indicate a dot of display in the associated 18 column on the display 24. The bit 0 position of an address 19 location must contain a 1 for the first and last address 20 locations and a 0 for all display information address locations. ~
21 The presence of a logic 1 at the first and last address ~ }
22 identifies these words as control and allows bit position 1 23 to serve as a modifier. A 0 at bit position 1 indicates a 24 first word and first address position and a 1 at bit position 1 25 indicates the last address position. The bit 0 and bit 1 26 control signals are utilized to simplify the display control 27 logic 800 and to eliminate the need to scan the dot display 28 column locations for which no information is to be displayed. -~ ?
29 IWhen data is to be loaded into the display buffer 794 30 a blank command is first required to return the address counter .,. ' '`~ .

, ^~ ~

~ 64621 ' 1 796 and column counter 798 to address location 0. Column ~`
2 counter 798 generates no visible display at address 0. Display ; 3 information may then be loaded into the display buffer 794 `~ ;
4 by successive write data commands which cause the writing of -data from bus 777 into an address location Eollowed by the ; 6 incrementing of address counter 796. The information content 7 of bits 1 7 of the display address locations may contain any ' 8 selected information content chosen to generate a desired ,~
9 display pattern.
The use of a "dot image" rather than character format `~ 11 for the refresh buffer 794 allows the microprogram in data - 12 processor 54 to provide character font flexibility whereby -13 the terminal proprietor can specify in his initialization 14 message the text of the various display messages and further ; 15 can define unique graphics for display in the messages. As 16 an example which may save either memory storage space or message 17 transmission time, a word used commonly in many messages could `~ 18 be identified as a unique graphic and displayed as the ,i ~19 representation of a single character in a message. A second -example of a special graphic may be a foreign letter. This ~ 21 dot~technique also permits the use of variable width letters~ ~ -; 22 for greater readability and greater display capacity for a 23 given display size. ~ ~ ~s 24 Transaction Statement Dispenser Subsystem ~;~
~ 25 As shown in Fig. 12j the transaction.statement dis~
`- 2~ penser subsystem 63 controls and receives feedback and status 27 information for the printer 250. The elements of transaction . 28 statement dispenser subsystem 63 which are common to the ~ 29 subsystems 60-64 include bus interface logic 810, interrupt '~ 30 request flip-flop 812, a data bus 814, a command decoder and ~-.` , :

lO~i9,t~iZl ;: ~
1 latch 816 and OR gate 818 which generates the subsystem reset 2 signal RST in response to either the terminal reset signal or 3 a control command reset signal ADRST, a basic status register -~
4 820, basic status control logic 822, and basic status gate 824.
The printer 250 is controlled by loading inforn~ation into a 6 register 826 which includes five 8 bit bytes designated A, B, 7 C, D and control register. Information appearing on the data 8 bus 814 is selectively loaded into these registers at data ` ~-~
- 9 time in response to the commands load A, load B, load C, load D, and WF (WRITE FUNCTION), respectively. Information 11 written into registers A, B, C and D of register 826 determine 12 the character which is printed at a given column position of 13 a transaction statement for rows 1, 2, 3 and 4 respectively. `
14 The control register stores commands for controlling the operation of printer 250. Bit 0 of the control register is a 16 document feed bit and the writing oE a logic 1 into this bit `-17 position causes transaction statement form to be fed from a 18 hopper and transported to a print station in preparation for 19 the printing of a left-most column of charactexs. Bit position ~ ~;
1 is a print/increment command bit with a logic 1 in this bit 21 position commanding the printing of information indicated by 22 reglsters A, B, C and D at the present column location of the `~
- 23 transaction statement form followed by the increme~ting of the~
24 column location of the transaction statement form. Bits 2-7 25 of control register are not implemented. The set input to -.::; :.~
26~ interrupt request flip-flop 812 is controlled by an OR gate 828 27 which responds to basic status buts BS0, BSl and BS2 to generate 28 an interrupt request any time one of these bit positions assumes 29 a logic 1 condition. Within the basic status register 820, `
bit 0 represents an end of print bit. This bit position is SA974017 _57_ ..

:~L064~;2~ ~
1 turned on by an end of print signal (EOP) after all four 2 row positions of a columll have been printed and while the ~ -3 transaction statement form is being incremented. Bit position 1 4 of the basic status register is a card in place (CIP~ bit position and when set to logic l indicates that a preceding 6 transaction statement form feed operation has been completed 7 and the form is at the print station ready for the printing 8 of the first column. The CIP signal is generated only at the 9 leading edge of a CIP switch sensor as a transaction statement form enters the print station. After this bit position is 11 reset, it is not again set until a new transaction statement ~ .;
. 12 form enters the print station. Bit position 2 of the basic 13 status register is a card clear bit position (CCLR). A logic 1 14 in this bit position indicates that a transaction statement ;~
: . . .
form has ejected from the print station at the completion of 16 the printing information thereon and has reached the end of the ;~
17 form transport mechanism where it is about to enter the rotating ~`
18 stacker wheels of the document feed mechanism. Bit position 3 ;~
19 oP basic status register 820 is a card in place switch (CIPSW) bit position. This bit position remains set to logic 1 so long 21 as a transaction statement form is in the print station. It is 22 turned on as the card enters the station and turned off as a 23 card leaves the station at increment 41. Bit position 4 is theb 24 forms out (F. out) bit and is set to logic 1 when the forms out sensor switch indicates that there ~are insufficient trans~
~ . . .
' 26 action statement forms left in the hopper to complete a new ~ ~
:,~ ... , :
27 transaction request. Bit positions 5, 6 and 7 of basic status . 28 register 820 are not implemented. `
29 The bit positions of basic status register 820 are ::~
30 controlled in accordance with the following functions: ; ~
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SA974017 -58- , ~
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1 SET B.S.0 - SET BS ADl-~EOP ~
2 RST B.S,0 = RST B.S. ADl~RST ~ -3 SET B.S~l = SET B~S. ADl~CIP
4 RST B.S.l = KST B.S. ADl~RST
SET B.S.2 = SET B.S.-AD2+CCLR
6 RST B.S.2 = RST B.S.-AD2+RST
7 SET B.S.3 = SET B.S.-AD3+CIPSW
8 RST B.S.3 = RST B.S. AD3+RST
9 SET B.S.4 = SET B.S. AD4+F.Out RST B.S.4 = RST B.S. AD4+RST
n auxlliary status register 830 provides printer `
12 feedback information which supplements the information provided 13 by the basic status register 820. The latches of the auxiliary 14 status register 830 are set by the occurrence of a logic 1 on ` ~;
15 the corresponding input signals therefor and reset by a reset ; .
16 auxiliary status signal, RST A.S., which is generated by an 17 OR gate 832 in response to a WF command or an AD RST command. ;;
18 Bit position 0 of the auxiliary status register 830 is a count 19 error bit. As the print wheels are rotated, an indexing signa~
is generated by sensor 412 each time the print wheels rotate~
. . ~. .~, j~ 21 past a home position. A counter is also incremented beginning `~
~22 with the home position for each rotation of the print wheels 23 through a character position. If this counter does not store~
- .r' ,-: ~
24 count 63 when the home index signal is generated, the CE signal ~ ~`
is generated to turn on bit 0 of auxiliary sta.tus register 830.
26 Bit 1 of the auxiliary status xegister 830 is a misfire bit 27 (MFIRE). This signal is generated ~y sensing each print .. ~, ..
. 28 magnet while its driver is turned on. If any of the four ;;~`
29 print magnets is not energized while the driver is turned on, .~-30 a signal MFIRE is generated to turn on bit 1 of the auxiliary `~ -SA974017 -59- `
. ~``'' ';.,' 10~;46;21 1 status register 830. Bit 2 is a print magnet sense bit (PMS).
Z Signal PMS indicates that either at least one of the print 3 magnets is energized or by sensing a low voltage level at the 4 driver input thereto. Bit position 3 of the auxiliary status ~;
register 830 is the home emitter sense (HES) signal and is set 6 in response to the generation of the index home signal by 7 sensor ~12. Bit 4 is the increment feed sense bit (I/FS) and 8 is set to logic 1 whenever the incrementing solenoid 410 is 9 energized. Auxiliary status register 830 is read by the micro~
processor 72 by generating a READ A.S. control command which is 11 made available to a gate 863 to gate the contents of auxiliary 12 status register 830 onto subsystem data bus 814 at data time.
13 Operation Function Subsystem 14 As shown in Fig. 13, the operator function subsystem `
controls the operation oE the auxiliary memory 850 as well as 16 a four digit hexidecimal display 852 and data entry switches 17 854 on an operator panel which is accessible through an ~ -18 operator panel door at the rear of the terminal 10~ The elements ~;~
19 which are common to each of the subsystems 60-64 include bus ;~
inter~ace logic 856 and interrupt request flip-~lop 858, a data~
21 bus 860, command decoder and control circuitry 862, and an OR `
22 gate 864 which generates a subsystem reset signal RST in response 23 to a terminal reset signal or a command control reset signai ~s 24 ADRST, basic status control logic 866, an 8 bit basic status `~
register 868, and a gate 870 between the output of the basic 26 status latches 868 and the data bus 860. The operation of ``~
27 these common elements have been described in conjunction with 28 the processor support subsystem 60 and mechanical control sub-29 system 61 and will not be repeated at this time.
The control circuitry for the auxiliary memory 850 ., . . . : :

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1 includes a standby power source 872 and a power sensor 874 2 which senses AC and DC power level within the terminal 10 and 3 generates a power O~lt warning interrupt signal ~P0WI) which 4 activates the standby power to memory 850 in the event that a short duration AC utility power failure is detected as a warning 6 that logic power will soon be unavailable.
7 Signal POWI causes standby power circuits 872 to 8 switch auxiliary memory 850 from utility power to emergency 9 memory protect power (e.g., a battery~ and also generates an `
interrupt request of through flip-flop 858 of the mechanical 11 control subsystem 61. The microprocessor 72 responds to this 12 interrupt by storing in auxiliary memory 850 any critical 13 information such as cash counts or transaction counts which 14 are required ~or resumption of operation after power is restored.
A short time later, after the microprocessor has had time to 16 store pertinent parameters, access to memory 850 is disabled 17 by terminating a memory enable signal, MEN, which normally 18 enables an AND gate 875 which controls chip selection for 19 memory 850 operation. Shortly after-signal ME~ is terminated, 20 the power sensor 874 generates a power on reset signal,POR, ~ ~ ;
. .
21 to command a terminal reset through control gate 102 of 22 processor support subsystem 60. POR is an active low signal -~
23 that remains so long as there is any meaningful power to ;i `~
24 terminal 10. The resulting T. Reset signal constrains the 25 microprocessor to address the predetermined prQgram startup ~-26 memory location. -27 Upon reactivation of utility power, the POWI signal ~ ~
. 28 is terminated after all power signals are adequately available. ;~-3 29 The MEN signal is then generated followed by termination of signal POR to permit the microprocessor to begin executing " ~,', ~' ~

, .. . .. . .. . .. . . .

~ 6 ~

1 instructions starting with the reset memory address location.
2 The automatic resumption of terminal operation following a 3 power failure is thus implemented.
4 Two data bus cycles are required to write in~ormation into or read information from auxiliary memory 850. The first 6 is a write cycle which causes a desired address location to 7 be written into an address register 876. The second is a read 8 or write command which causes information on data bus 860 to 9 be received from or written into the memory 850. Upon genera-tion of the subsequent read or write command, a memory cycle 11 signal is generated by command decoder and control logic 862 12 which, during th~ command time, causes a read or write indication -~
13 to be set into a latch 878 and initiates a memory timing cycle ``
14 for memory timing circuitry 880. Circuitry 880 generates 15 appropriate timing signals for initiating chip select and `~
16 strobing information into the input data latches in the event 17 of a write cycle.
18 The operator switches 854 include a momentary push~
19 button execute switch 890, a 16 position rotary function `~
switch 892, a most significant 16 position hexidecimal rotary 21 data switch 894, a 16 position least significant hexidecimal ~;
22 data switch 896, and a toggle switch 898. A decoder and 23 latch 900 decodes and latches the output of switch 892 at 24 command time in the event that a command is received to read -the function switch 892. The latch is set by a command read 26 function switch signal, RFSWC, to prevent the data information ~`
27 from changing during the subsequent data time in Lhe event 28 that the function switch 892 is turned. At the immediately 29 subsequent data time, a read function switch gate signal, RFSWG, is generated to activate a gate 902 to gate the contents '; ' ~`,', :~,., ,, ~; ', . ~ .

~64 : -1 of latch 900 onto the data bus 860. The decoder output of 2 switch 892 is carried at li~ s AD0-AD3 of the data bus 860.
3 Similarly, a read data switch command causes the generation of 4 a read data switch command signal, RHDSWC, which causes a decoder and latch 904 to latch the decoder output o switches 6 894 and 896. During the subsequent data time a read data `
7 switch gate signal (RHDSWG) activates gate 906 to drive the ;~
8 data bus 860 with the decoder outputs from switches 894 and 896 9 with the outputs from switch 894 being presented on lines ~
10 AD0-AD3 in the outputs of switch 896 being presented on lines ~ -11 AD4 AD7. The outputs of toggle switch 898 and execute switch ~- ;
12 890 are connected to drive bit positions 3 and 4, respectively, 13 of the basic status register 868 which in turn drive an OR
14 gate 908 to set the interrupt request flip-flop 858. The ; ';
activation of the pushbutton switch 890 serves as an operator 16 command to have the microprocessor 72 sample and respond to ~;~
. .: , 17 the status of the rotary switches 892, 894 and 896 at the time ;
18 of activation of the pushbutton 890. The toggle switch 898 ``
19 is used to indicate a selected document feed mechanism 240 20 or 242 with a logic 1 output indicating the selection of the - ;~
21 second document feed mechanism 242.
22 There are 16 possible functions which are available 23 for selection by function selection switch 892. One position .
24 permits the loading of an encryption key A through the data 25 switches 894, 896 two digits at a time, 8 activations of `~
26 switch 890 being required to load all 16 digits (8 bytes). ~;
27 Another position permits the loading in a similar manner of 28 a backup ~ransmission encryption key, key C. Two other positions 29 command the resetting of key A and key C which are supposed ;~
to be reset prior to the selection of any other operator ~unction.

~A974017 -63-- - `

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~(~6462~
1 However, the microprocessor resets these keys upon selection 2 and command of an operator function even if the operator does 3 not. The maintenance operator is thus prevented from gaining 4 access to these keys~ Other positions permit the selective display or resetting of a consecutive decimal count which 6 indicates a number of issued bills. The applicable document 7 feed mechanism 240 or 242 is determined by the position of 8 toggle switch 898. A self test position commands the printing 9 and issuance of a transaction statement having a predetermined test message and the issuance of a single bill from a document 11 feed mechanism 240 or 242 indicated by toggle switch 898.
12 Only two bits of basic status register 8~6 are 13 implemented, Bit 1 responds to the execute switch 890 and 14 bit 3 responds to the toggle switch 898, The control signals 15 are:
16 SET B, S. l = SET B. S. -ADl+TOGGLE SWITCH
,: ~
17 RST B. S. 1- = RST B. S. ADl+RST ~ ~-18 SET B. S.4 = SET B.S. AD4+EXSW `~
19 RST B.S.4 = RST B . S . AD4+RST ; ;
The four digit hexidecimal display 852 is driven 21 in response to two registers. A lef~ register 912 drives the - -; - . .
~~ 22 two left-most digits while a right register 914 drives the - 23 two right-most digits, Command decoder and control circuitry ~
24 862 generates either a WLR command signal or a WRR command ,~ -;;
signal at data time in response to a command to~write information ~ , 26 into the left register or right register, respectively, In 27 addition, both signals may be generated simultaneously in ` , 28 response to a command to write the same data into both ;' 29 registers at the same time, This of course would cause the ` 30 left two digits to display the same informati~ as the right .,..................................................................... , ~ , : . .
: :
SA974017 -64- ~ `-~ ~ , ' ', .' , . .

1C164 E;;~ :
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1 two digits. A pair of blanking flip-flops 916, 918 permit 2 the selective blanking and unblanking of the two left and the .
3 two right hexidecimal display digits of display 852 in response 4 to blank left, unblank left, blank right and unblank right - :
commands from the command decoder and control circuitry 862.
6 These signals are generated in response to microprocessor ^.
7 command control signals for the proper implementation of . 8 (1) an unblank left and right command, (2~ an unblank left ;
9 and blank right command, (3) an unblank right and blank left ~-~
; 10 command, or (4) a blank left and blank right command.
11. Selective control of the blanking and unblanking of the two 12 left and two right hexidecimal display digits is thus provided.
13 Other commands from the microprocessor which are : ~
14 applicable to the operator function subsystem 64 includes :; ::
,~
15 write data to right register 914, write data to left register .
16 912 and write data to both right register 914 and left register . 17 912 simultaneously. These command signals cause the generation.
18 of appropriate WLR and WRR signals for the gating of the bus :. ...: ,:
19 information into the registers 912, 914 in correspondence., :,. . - .
20 therewith. In addition, there are several groups of four ;~
21 microprocessor commands, each of which command the appearance 22 of data an the data bus 860 with this data being written into ... -~
23 neither register 912 nor register 9149 register 912 but not ~: 24 register 914, register 914 but not 912, or both registers 412 ~.
!`1' ~ 25 and 914. Only the category of commands will b.e discussed ...
26 generally hereafter but it will be appreciated that each of the 27 four above-described variations are applicable for each command. ;
. . 28 A write auxiliary address command causes the transfer of .,, , . .;
29 information appearing on the bus 860into the memory address ;.
. 30 register 876. During the data time a store command is generated . . .
SA974017 -65- :
-:
.; , ' .:

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1 by the command decoder and control circuitry 816 to clock the latches of address register 876 and reset latches 882 of input register in preparation for a possible subsequent write command. A write auxiliary memory data command causes the information appearing on data bus 860 to be latched by latches 882 and written into the memory 850 at a previously defined memory address location. A read auxiliary memory data command causes information output from a previously defined address location of memory 850 to be transferred -~

to the data bus 860 at data time. A read data switch command signal causes the generation of signal RHDSWC at command ~;
time and signal RHDSWG at data time to gate the encoded representation of the status of switches 894 and 896 onto the data bus line 860. Similarly, a read function switch control command causes the generation signals RFSWC and ~- ~
~FSWG to cause the encoded output of function switch 892 ~ ~ -to be latched during command time and to be placed on the data bus line 860 during data time.
While there has been described above a particular embodi-ment of a transaction execution terminal ha~ing a basic microprocessor modular control system in accordance with :~ , the invention for the purpose of enabling a person of ordinary skill in the art to make and use the in~ention, it will be appreciated that the invention is not limitèd thereto. ;~
Accordingly, any modification, variation or equivalent ~`
1 arrangement within the scope of the attached claims should be considered to be within the scope of the inv~ntion.
, . '' ' ~' ' "

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~ SA9-74-017 -66- ~

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Claims (3)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1. A cash issue transaction execution terminal comprising:
a terminal data bus;
a plurality of terminal subsystems, each being connected to com-municate with programmable control subsystem via the data bus and being operable to execute terminal functions in response to information from the control subsystem and to accumulate information on the status of controlled functions for communication to the control subsystem, a programmable control subsystem which is operable to communicate with other terminal subsystems via the terminal data bus to control terminal operations, the control subsystem being operable to access a predetermined instruction location in response to a terminal reset command; and circuitry connected to detect irregular terminal conditions which indicate the inability of the control subsystem to properly execute instructions and generate a terminal reset signal in response to the detection of at least one of said irregular terminal conditions.

2. The cash issue transaction execution terminal as set forth in claim 1 above, wherein the detection circuitry includes a circuit for detecting an absence of control subsystem activity for a pre-determined period of time.

3. The cash issue transaction execution terminal as set forth in claim 2 above, wherein the detection circuitry includes a power sense circuit connected to sense a utility power interruption of at least a predetermined duration and generate a terminal reset signal after a predetermined delay following said power interruption detection.