AU2001229505A1 - Establishing thread priority in a processor or the like - Google Patents

Establishing thread priority in a processor or the like

Info

Publication number
AU2001229505A1
AU2001229505A1 AU2001229505A AU2950501A AU2001229505A1 AU 2001229505 A1 AU2001229505 A1 AU 2001229505A1 AU 2001229505 A AU2001229505 A AU 2001229505A AU 2950501 A AU2950501 A AU 2950501A AU 2001229505 A1 AU2001229505 A1 AU 2001229505A1
Authority
AU
Australia
Prior art keywords
processor
thread priority
establishing thread
establishing
priority
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001229505A
Inventor
Deborah T. Marr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of AU2001229505A1 publication Critical patent/AU2001229505A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2209/00—Indexing scheme relating to G06F9/00
    • G06F2209/50—Indexing scheme relating to G06F9/50
    • G06F2209/507—Low-level

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Bus Control (AREA)
AU2001229505A 2000-01-22 2001-01-17 Establishing thread priority in a processor or the like Abandoned AU2001229505A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/490,172 US8041754B1 (en) 2000-01-22 2000-01-22 Establishing thread priority in a processor or the like
US09490172 2000-01-22
PCT/US2001/001391 WO2001053939A2 (en) 2000-01-22 2001-01-17 Establishing thread priority in a processor or the like

Publications (1)

Publication Number Publication Date
AU2001229505A1 true AU2001229505A1 (en) 2001-07-31

Family

ID=23946893

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001229505A Abandoned AU2001229505A1 (en) 2000-01-22 2001-01-17 Establishing thread priority in a processor or the like

Country Status (3)

Country Link
US (2) US8041754B1 (en)
AU (1) AU2001229505A1 (en)
WO (1) WO2001053939A2 (en)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8041754B1 (en) * 2000-01-22 2011-10-18 Intel Corporation Establishing thread priority in a processor or the like
GB2372847B (en) * 2001-02-19 2004-12-29 Imagination Tech Ltd Control of priority and instruction rates on a multithreaded processor
WO2009157136A1 (en) * 2008-06-24 2009-12-30 パナソニック株式会社 Access control apparatus, access control program, and access control method
US8656145B2 (en) * 2008-09-19 2014-02-18 Qualcomm Incorporated Methods and systems for allocating interrupts in a multithreaded processor
US8578136B2 (en) 2010-06-15 2013-11-05 Arm Limited Apparatus and method for mapping architectural registers to physical registers
FR2993683B1 (en) * 2012-07-20 2014-08-01 Morpho METHOD FOR MANAGING EXECUTIVE WIRES IN A COMPUTER UNIT AND AGENCY COMPUTER UNIT FOR CARRYING OUT SAID METHOD
US9021493B2 (en) * 2012-09-14 2015-04-28 International Business Machines Corporation Management of resources within a computing environment
US10002031B2 (en) * 2013-05-08 2018-06-19 Nvidia Corporation Low overhead thread synchronization using hardware-accelerated bounded circular queues
US10248463B2 (en) * 2015-02-13 2019-04-02 Honeywell International Inc. Apparatus and method for managing a plurality of threads in an operating system
US10430342B2 (en) * 2015-11-18 2019-10-01 Oracle International Corporation Optimizing thread selection at fetch, select, and commit stages of processor core pipeline
US10069949B2 (en) 2016-10-14 2018-09-04 Honeywell International Inc. System and method for enabling detection of messages having previously transited network devices in support of loop detection
US10810086B2 (en) 2017-10-19 2020-10-20 Honeywell International Inc. System and method for emulation of enhanced application module redundancy (EAM-R)
US10783026B2 (en) 2018-02-15 2020-09-22 Honeywell International Inc. Apparatus and method for detecting network problems on redundant token bus control network using traffic sensor
US10831492B2 (en) 2018-07-05 2020-11-10 International Business Machines Corporation Most favored branch issue
JP7298624B2 (en) * 2018-12-11 2023-06-27 サンケン電気株式会社 Processor and pipeline processing method

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5220653A (en) * 1990-10-26 1993-06-15 International Business Machines Corporation Scheduling input/output operations in multitasking systems
US5495615A (en) * 1990-12-21 1996-02-27 Intel Corp Multiprocessor interrupt controller with remote reading of interrupt control registers
JP2908598B2 (en) 1991-06-06 1999-06-21 松下電器産業株式会社 Information processing device
DE69735575T2 (en) * 1996-08-20 2006-08-24 Compaq Computer Corp., Houston Method and apparatus for interrupt distribution in a scalable symmetric multiprocessor system without changing the bus width or the bus protocol
US5944809A (en) * 1996-08-20 1999-08-31 Compaq Computer Corporation Method and apparatus for distributing interrupts in a symmetric multiprocessor system
EP0827071B1 (en) 1996-08-27 2002-11-27 Matsushita Electric Industrial Co., Ltd. Multithreaded processor for processing multiple instruction streams independently of each other by flexibly controlling throughput in each instruction stream
US5799182A (en) * 1997-01-21 1998-08-25 Ford Motor Company Multiple thread micro-sequencer apparatus and method with a single processor
US6658447B2 (en) * 1997-07-08 2003-12-02 Intel Corporation Priority based simultaneous multi-threading
US6567839B1 (en) * 1997-10-23 2003-05-20 International Business Machines Corporation Thread switch control in a multithreaded processor system
US6076157A (en) * 1997-10-23 2000-06-13 International Business Machines Corporation Method and apparatus to force a thread switch in a multithreaded processor
US6212544B1 (en) 1997-10-23 2001-04-03 International Business Machines Corporation Altering thread priorities in a multithreaded processor
US6105051A (en) * 1997-10-23 2000-08-15 International Business Machines Corporation Apparatus and method to guarantee forward progress in execution of threads in a multithreaded processor
US6341342B1 (en) * 1997-11-04 2002-01-22 Compaq Information Technologies Group, L.P. Method and apparatus for zeroing a transfer buffer memory as a background task
US6219741B1 (en) * 1997-12-10 2001-04-17 Intel Corporation Transactions supporting interrupt destination redirection and level triggered interrupt semantics
US6018759A (en) * 1997-12-22 2000-01-25 International Business Machines Corporation Thread switch tuning tool for optimal performance in a computer processor
US6339808B1 (en) * 1999-01-04 2002-01-15 Advanced Micro Devices, Inc. Address space conversion to retain software compatibility in new architectures
US8041754B1 (en) * 2000-01-22 2011-10-18 Intel Corporation Establishing thread priority in a processor or the like
US6757811B1 (en) * 2000-04-19 2004-06-29 Hewlett-Packard Development Company, L.P. Slack fetch to improve performance in a simultaneous and redundantly threaded processor
US7694055B2 (en) * 2005-10-15 2010-04-06 International Business Machines Corporation Directing interrupts to currently idle processors

Also Published As

Publication number Publication date
US8516024B2 (en) 2013-08-20
US20120023502A1 (en) 2012-01-26
WO2001053939A3 (en) 2002-02-21
US8041754B1 (en) 2011-10-18
WO2001053939A2 (en) 2001-07-26

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