ATE350765T1 - Verfahren zur herstellung einer halbleitervorrichtunng und eine halbleitervorrichtung - Google Patents

Verfahren zur herstellung einer halbleitervorrichtunng und eine halbleitervorrichtung

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Publication number
ATE350765T1
ATE350765T1 AT02077552T AT02077552T ATE350765T1 AT E350765 T1 ATE350765 T1 AT E350765T1 AT 02077552 T AT02077552 T AT 02077552T AT 02077552 T AT02077552 T AT 02077552T AT E350765 T1 ATE350765 T1 AT E350765T1
Authority
AT
Austria
Prior art keywords
semiconductor device
producing
semiconductor
package leads
semiconductor material
Prior art date
Application number
AT02077552T
Other languages
English (en)
Inventor
Ronald Dekker
Henricus Godefridus Rafae Maas
Martinus Pieter Joh Versleijen
Original Assignee
Koninkl Philips Electronics Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv filed Critical Koninkl Philips Electronics Nv
Application granted granted Critical
Publication of ATE350765T1 publication Critical patent/ATE350765T1/de

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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Manufacture Of Macromolecular Shaped Articles (AREA)
  • Die Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
AT02077552T 1994-07-26 1995-07-05 Verfahren zur herstellung einer halbleitervorrichtunng und eine halbleitervorrichtung ATE350765T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP94202182 1994-07-26

Publications (1)

Publication Number Publication Date
ATE350765T1 true ATE350765T1 (de) 2007-01-15

Family

ID=8217069

Family Applications (2)

Application Number Title Priority Date Filing Date
AT02077552T ATE350765T1 (de) 1994-07-26 1995-07-05 Verfahren zur herstellung einer halbleitervorrichtunng und eine halbleitervorrichtung
AT95921959T ATE225985T1 (de) 1994-07-26 1995-07-05 Herstellungsmethode eines oberflächen- montierbaren bauteils und dieser selbst

Family Applications After (1)

Application Number Title Priority Date Filing Date
AT95921959T ATE225985T1 (de) 1994-07-26 1995-07-05 Herstellungsmethode eines oberflächen- montierbaren bauteils und dieser selbst

Country Status (7)

Country Link
US (1) US5753537A (de)
EP (2) EP1251557B1 (de)
KR (1) KR100380701B1 (de)
AT (2) ATE350765T1 (de)
DE (2) DE69535361T2 (de)
TW (1) TW345728B (de)
WO (1) WO1996003772A2 (de)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10503330A (ja) * 1995-05-10 1998-03-24 フィリップス エレクトロニクス ネムローゼ フェンノートシャップ 表面取付け用小形半導体デバイス
EP0860876A3 (de) * 1997-02-21 1999-09-22 DaimlerChrysler AG Anordnung und Verfahren zur Herstellung von CSP-Gehäusen für elektrische Bauteile
KR100390897B1 (ko) * 1997-12-29 2003-08-19 주식회사 하이닉스반도체 칩 크기 패키지의 제조방법
DE19818036B4 (de) * 1998-04-22 2005-05-19 Siemens Ag Verfahren zur Herstellung eines elektrotechnischen Bauteils mit einer kunststoffpassivierten Oberfläche, derartiges Bauteil und Anwendung dieses Bauteils
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TW345728B (en) 1998-11-21
EP0721661A1 (de) 1996-07-17
WO1996003772A2 (en) 1996-02-08
KR960705353A (ko) 1996-10-09
DE69528515D1 (de) 2002-11-14
EP1251557B1 (de) 2007-01-03
EP1251557A3 (de) 2003-04-09
EP1251557A2 (de) 2002-10-23
ATE225985T1 (de) 2002-10-15
DE69535361D1 (de) 2007-02-15
KR100380701B1 (ko) 2003-07-22
US5753537A (en) 1998-05-19
DE69535361T2 (de) 2007-10-04
DE69528515T2 (de) 2003-04-24
EP0721661B1 (de) 2002-10-09
WO1996003772A3 (en) 1996-04-18

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