My public Baremetal Raspberry Pi code

Bare metal example software projects for PolarFire SoC

PolarFire SoC Documentation

RPMsg implementation for small MCUs

This is the development home of the workflow management system Snakemake. For general information, see

U-Boot for Real-time Edge Software

Primary Git Repository for the Zephyr Project. Zephyr is a new generation, scalable, optimized, secure RTOS for multiple hardware architectures.

一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。

Python packages providing a library for Verification Stimulus and Coverage

Bare Metal Compatibility Library for the Freedom Platform

Curated list of project-based tutorials

SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)

Read-only mirror of Trusted Firmware-A

Systemverilog DPI-C call Python function

An opinionated build environment for EDA projects

Open Source Software for Developing on the Freedom E Platform - Deprecated

python wrapper to submit jobs to bsub (and later qsub)

SystemC/TLM-2.0 Co-simulation framework

STM32 stuff

Textual is a TUI (Text User Interface) framework for Python inspired by modern web development.

HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded functions, with ZERO learning-curve

Let's Build A Simple Interpreter

十分钟魔法练习 in Rust

Python tool for monitoring bsub jobs

RISCV model for Verilator/FPGA targets

task management & automation tool

Common Agent is a generic agent implemented in SystemVerilog, based on UVM methodology, which can be easily extended to create very fast an UVM based agent for any protocol.

UVM Auto Generate ; Verify Project Build; Verilog Instance