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1 Updated Aug 9, 2017

FPGA project

1 Updated Aug 10, 2019

Capture data from multiple ADCs concurrently using an FPGA. Stream the captured data out over ethernet + UDP. Tested on the Spartan 6 XC6SLX9, Wiznet W5500, and MCP3002 ADC.

Verilog 12 6 Updated Dec 10, 2016